dt-bindings: regulator: add gdsc-regulator bindings
Add bindings for gdsc-regulator on Sun Soc. Change-Id: I50eda2575b97580696ae5d91ce155c2ce21353cf Signed-off-by: Xubin Bai <quic_xubibai@quicinc.com>
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Xubin Bai
170
bindings/regulator/gdsc-regulator.yaml
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170
bindings/regulator/gdsc-regulator.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/regulator/gdsc-regulator.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. Global Distributed Switch Controller Regulator
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maintainers:
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- Xubin Bai <quic_xubibai@quicinc.com>
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description: |
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The GDSC driver, implemented under the regulator framework,
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is responsible for safely collapsing and restoring power to
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peripheral and multimedia cores on chipsets for power savings.
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properties:
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compatible:
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const: qcom,gdsc
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regulator-name:
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description: A string used as a descriptive name for regulator outputs.
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reg:
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description: The address of the GDSCR register.
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parent-supply:
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description: phandle to the parent supply regulator node.
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clocks:
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description: phandle to clock used by GDSC.
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clock-names:
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description: List of string names for core clocks.
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qcom,retain-regs:
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description: |
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Presence denotes a hardware requirement to enable the
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usage of retention registers which maintain their state
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after the GDSC is disabled and re-enabled.
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$ref: /schemas/types.yaml#/definitions/flag
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qcom,skip-logic-collapse:
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description: |
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Presence denotes a requirement to leave power to
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the core's logic enabled.
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$ref: /schemas/types.yaml#/definitions/flag
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qcom,support-hw-trigger:
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description: |
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Presence denotes a hardware feature to switch on/off this
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regulator based on internal HW signals to save more power.
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$ref: /schemas/types.yaml#/definitions/flag
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qcom,enable-root-clk:
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description: |
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Presence denotes that the clocks in the "clocks"
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property are required to be enabled before gdsc is
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turned on and disabled before turning off gdsc. This
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will be used in subsystems where reset is synchronous
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and root clk is active without sw being aware of its
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state. The clock-name which denotes the root clock
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should be named as "core_root_clk".
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$ref: /schemas/types.yaml#/definitions/flag
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qcom,force-enable-root-clk:
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description: |
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If set, denotes that the root clock should be force enabled
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before turning on the GDSC and then be immediately force
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disabled. Likewise for GDSC disable. This is used in cases
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where the core root clock needs to be force-enabled prior
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to turning on the core. The clock-name which denotes the
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root clock should be "core_root_clk".
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$ref: /schemas/types.yaml#/definitions/flag
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qcom,clk-dis-wait-val:
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description: |
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Input value for CLK_DIS_WAIT controls state transition
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delay after halting clock in the collapsible core.
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$ref: /schemas/types.yaml#/definitions/flag
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reg-names:
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description: |
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Names of the bases for the above "reg" registers.
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Ex. "base", "domain-addr", "sw-reset", "hw-ctrl-addr".
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qcom,no-status-check-on-disable:
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description: Do not poll the status bit when GDSC is disabled.
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$ref: /schemas/types.yaml#/definitions/flag
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qcom,gds-timeout:
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description: |
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Maximum time (in usecs) that might be taken by a GDSC to enable.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,reset-aon-logic:
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description: |
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If present, the GPU DEMET cells need to be reset while
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enabling the GX GDSC.
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$ref: /schemas/types.yaml#/definitions/flag
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qcom,support-cfg-gdscr:
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description: |
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Presence denotes HW supports CFG_GDSCR register
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when checking the status of gdsc.
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$ref: /schemas/types.yaml#/definitions/flag
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qcom,collapse-vote:
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description: |
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Phandle pointer to the register APCS_GDSC_BRANCH_ENA_VOTE
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that collapse GDSCs.
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$ref: /schemas/types.yaml#/definitions/phandle
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qcom,skip-disable:
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description: |
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If the disable skipping feature is allowed, then use mode
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control to enable and disable the feature at runtime instead
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of using it to enable and disable hardware triggering.
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$ref: /schemas/types.yaml#/definitions/flag
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vdd_parent-supply:
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description: |
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phandle to the regulator that this GDSC gates. If present,
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need to vote for a minimum operational voltage (LOW_SVS) on
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the GDSC parent regulator prior to configuring it. The vote
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is removed once the GDSC FSM has latched on to the new state.
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resets:
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minItems: 1
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maxItems: 2
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description: |
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reset specifier pair consisting of phandle for the reset
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controller and reset lines used by this controller. These
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can be supplied only if we support qcom,skip-logic-collapse.
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reset-names:
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description: |
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reset signal name strings sorted in the same order as
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the resets property. These can be supplied only if we
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support qcom,skip-logic-collapse.
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qcom,skip-disable-before-sw-enable:
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description: |
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Presence denotes a hardware requirement to leave the
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GDSC on that has been enabled by an entity external to HLOS.
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$ref: /schemas/types.yaml#/definitions/flag
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qcom,no-config-gdscr:
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description: |
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Presence denotes HW only supports a single register per GDSC.
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$ref: /schemas/types.yaml#/definitions/flag
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required:
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- compatible
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- regulator-name
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- reg
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additionalProperties: false
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examples:
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- |
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gdsc_oxili_gx: qcom,gdsc@fd8c4024 {
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compatible = "qcom,gdsc";
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regulator-name = "gdsc_oxili_gx";
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parent-supply = <&pm8841_s4>;
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reg = <0xfd8c4024 0x4>;
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clock-names = "core_clk";
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};
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...
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