ARM: dts: msm: add device tree files for sun target
Add device tree files required for DPU driver on sun target. Move bindings for all mdp, dsi, panels, hdcp to opensource project. Change-Id: I1c6575313e33c5727f48ce94fe8b51cd9c62995d Signed-off-by: Varsha Suresh <quic_varssure@quicinc.com> Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
This commit is contained in:
Varsha Suresh
committed by
Veera Sundaram Sankaran
Veera Sundaram Sankaran
parent
5da80fc643
commit
313d6ad696
6
Kbuild
Normal file
6
Kbuild
Normal file
@@ -0,0 +1,6 @@
|
|||||||
|
dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \
|
||||||
|
display/sun-sde-display-rumi-overlay.dtbo
|
||||||
|
|
||||||
|
always-y := $(dtb-y) $(dtbo-y)
|
||||||
|
subdir-y := $(dts-dirs)
|
||||||
|
clean-files := *.dtb *.dtbo
|
||||||
9
Makefile
Normal file
9
Makefile
Normal file
@@ -0,0 +1,9 @@
|
|||||||
|
KBUILD_OPTIONS+=KBUILD_EXTMOD_DTS=.
|
||||||
|
|
||||||
|
all: dtbs
|
||||||
|
|
||||||
|
clean:
|
||||||
|
$(MAKE) -C $(KERNEL_SRC) M=$(M) clean
|
||||||
|
|
||||||
|
%:
|
||||||
|
$(MAKE) -C $(KERNEL_SRC) M=$(M) $@ $(KBUILD_OPTIONS)
|
||||||
278
bindings/dsi.txt
Normal file
278
bindings/dsi.txt
Normal file
@@ -0,0 +1,278 @@
|
|||||||
|
Qualcomm Technologies Inc. snapdragon DSI output
|
||||||
|
|
||||||
|
DSI Controller:
|
||||||
|
Required properties:
|
||||||
|
- compatible:
|
||||||
|
* "qcom,mdss-dsi-ctrl"
|
||||||
|
- reg: Physical base address and length of the registers of controller
|
||||||
|
- reg-names: The names of register regions. The following regions are required:
|
||||||
|
* "dsi_ctrl"
|
||||||
|
- interrupts: The interrupt signal from the DSI block.
|
||||||
|
- power-domains: Should be <&mmcc MDSS_GDSC>.
|
||||||
|
- clocks: Phandles to device clocks.
|
||||||
|
- clock-names: the following clocks are required:
|
||||||
|
* "mdp_core"
|
||||||
|
* "iface"
|
||||||
|
* "bus"
|
||||||
|
* "core_mmss"
|
||||||
|
* "byte"
|
||||||
|
* "pixel"
|
||||||
|
* "core"
|
||||||
|
For DSIv2, we need an additional clock:
|
||||||
|
* "src"
|
||||||
|
For DSI6G v2.0 onwards, we need also need the clock:
|
||||||
|
* "byte_intf"
|
||||||
|
- assigned-clocks: Parents of "byte" and "pixel" for the given platform.
|
||||||
|
- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
|
||||||
|
by a DSI PHY block. See [1] for details on clock bindings.
|
||||||
|
- vdd-supply: phandle to vdd regulator device node
|
||||||
|
- vddio-supply: phandle to vdd-io regulator device node
|
||||||
|
- vdda-supply: phandle to vdda regulator device node
|
||||||
|
- phys: phandle to DSI PHY device node
|
||||||
|
- phy-names: the name of the corresponding PHY device
|
||||||
|
- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2)
|
||||||
|
- ports: Contains 2 DSI controller ports as child nodes. Each port contains
|
||||||
|
an endpoint subnode as defined in [2] and [3].
|
||||||
|
|
||||||
|
Optional properties:
|
||||||
|
- panel@0: Node of panel connected to this DSI controller.
|
||||||
|
See files in [4] for each supported panel.
|
||||||
|
- qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is
|
||||||
|
driving a panel which needs 2 DSI links.
|
||||||
|
- qcom,master-dsi: Boolean value indicating if the DSI controller is driving
|
||||||
|
the master link of the 2-DSI panel.
|
||||||
|
- qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is
|
||||||
|
driving a 2-DSI panel whose 2 links need receive command simultaneously.
|
||||||
|
- pinctrl-names: the pin control state names; should contain "default"
|
||||||
|
- pinctrl-0: the default pinctrl state (active)
|
||||||
|
- pinctrl-n: the "sleep" pinctrl state
|
||||||
|
- ports: contains DSI controller input and output ports as children, each
|
||||||
|
containing one endpoint subnode.
|
||||||
|
- qcom,dsi-ctrl-shared: Boolean value indicating if the DSI controller is
|
||||||
|
shared between dual displays.
|
||||||
|
|
||||||
|
DSI Endpoint properties:
|
||||||
|
- remote-endpoint: For port@0, set to phandle of the connected panel/bridge's
|
||||||
|
input endpoint. For port@1, set to the MDP interface output. See [2] for
|
||||||
|
device graph info.
|
||||||
|
|
||||||
|
- data-lanes: this describes how the physical DSI data lanes are mapped
|
||||||
|
to the logical lanes on the given platform. The value contained in
|
||||||
|
index n describes what physical lane is mapped to the logical lane n
|
||||||
|
(DATAn, where n lies between 0 and 3). The clock lane position is fixed
|
||||||
|
and can't be changed. Hence, they aren't a part of the DT bindings. See
|
||||||
|
[3] for more info on the data-lanes property.
|
||||||
|
|
||||||
|
For example:
|
||||||
|
|
||||||
|
data-lanes = <3 0 1 2>;
|
||||||
|
|
||||||
|
The above mapping describes that the logical data lane DATA0 is mapped to
|
||||||
|
the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2
|
||||||
|
to phys DATA1 and logic DATA3 to phys DATA2.
|
||||||
|
|
||||||
|
There are only a limited number of physical to logical mappings possible:
|
||||||
|
<0 1 2 3>
|
||||||
|
<1 2 3 0>
|
||||||
|
<2 3 0 1>
|
||||||
|
<3 0 1 2>
|
||||||
|
<0 3 2 1>
|
||||||
|
<1 0 3 2>
|
||||||
|
<2 1 0 3>
|
||||||
|
<3 2 1 0>
|
||||||
|
|
||||||
|
DSI PHY:
|
||||||
|
Required properties:
|
||||||
|
- compatible: Could be the following
|
||||||
|
* "qcom,dsi-phy-28nm-hpm"
|
||||||
|
* "qcom,dsi-phy-28nm-lp"
|
||||||
|
* "qcom,dsi-phy-20nm"
|
||||||
|
* "qcom,dsi-phy-28nm-8960"
|
||||||
|
* "qcom,dsi-phy-14nm"
|
||||||
|
* "qcom,dsi-phy-10nm"
|
||||||
|
- reg: Physical base address and length of the registers of PLL, PHY. Some
|
||||||
|
revisions require the PHY regulator base address, whereas others require the
|
||||||
|
PHY lane base address. See below for each PHY revision.
|
||||||
|
- reg-names: The names of register regions. The following regions are required:
|
||||||
|
For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY:
|
||||||
|
* "dsi_pll"
|
||||||
|
* "dsi_phy"
|
||||||
|
* "dsi_phy_regulator"
|
||||||
|
For DSI 14nm and 10nm PHYs:
|
||||||
|
* "dsi_pll"
|
||||||
|
* "dsi_phy"
|
||||||
|
* "dsi_phy_lane"
|
||||||
|
- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating
|
||||||
|
2 clocks: A byte clock (index 0), and a pixel clock (index 1).
|
||||||
|
- power-domains: Should be <&mmcc MDSS_GDSC>.
|
||||||
|
- clocks: Phandles to device clocks. See [1] for details on clock bindings.
|
||||||
|
- clock-names: the following clocks are required:
|
||||||
|
* "iface"
|
||||||
|
For 28nm HPM/LP, 28nm 8960 PHYs:
|
||||||
|
- vddio-supply: phandle to vdd-io regulator device node
|
||||||
|
For 20nm PHY:
|
||||||
|
- vddio-supply: phandle to vdd-io regulator device node
|
||||||
|
- vcca-supply: phandle to vcca regulator device node
|
||||||
|
For 14nm PHY:
|
||||||
|
- vcca-supply: phandle to vcca regulator device node
|
||||||
|
For 10nm PHY:
|
||||||
|
- vdds-supply: phandle to vdds regulator device node
|
||||||
|
|
||||||
|
Optional properties:
|
||||||
|
- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
|
||||||
|
regulator is wanted.
|
||||||
|
- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode
|
||||||
|
panels in microseconds. Driver uses this number to adjust
|
||||||
|
the clock rate according to the expected transfer time.
|
||||||
|
Increasing this value would slow down the mdp processing
|
||||||
|
and can result in slower performance.
|
||||||
|
Decreasing this value can speed up the mdp processing,
|
||||||
|
but this can also impact power consumption.
|
||||||
|
As a rule this time should not be higher than the time
|
||||||
|
that would be expected with the processing at the
|
||||||
|
dsi link rate since anyways this would be the maximum
|
||||||
|
transfer time that could be achieved.
|
||||||
|
If ping pong split is enabled, this time should not be higher
|
||||||
|
than two times the dsi link rate time.
|
||||||
|
If the property is not specified, then the default value is 14000 us.
|
||||||
|
|
||||||
|
- frame-threshold-time-us: For command mode panels, this specifies the idle
|
||||||
|
time for dsi controller where no active data is
|
||||||
|
send to the panel, as controller is done sending
|
||||||
|
active pixels. If there is no desired DSI clocks
|
||||||
|
specified, then clocks will be derived from this
|
||||||
|
threshold time, which has a default value in chipset
|
||||||
|
based on the CPU processing power.
|
||||||
|
|
||||||
|
- dsi_pll_codes: Contain an u32 array data to store dsi pll codes which were passed
|
||||||
|
from UEFI.
|
||||||
|
- qcom,dsi-phy-shared: Boolean value indicating if the DSI phy is shared
|
||||||
|
between dual displays.
|
||||||
|
|
||||||
|
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||||
|
[2] Documentation/devicetree/bindings/graph.txt
|
||||||
|
[3] Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||||
|
[4] Documentation/devicetree/bindings/display/panel/
|
||||||
|
|
||||||
|
Example:
|
||||||
|
dsi0: dsi@fd922800 {
|
||||||
|
compatible = "qcom,mdss-dsi-ctrl";
|
||||||
|
qcom,dsi-host-index = <0>;
|
||||||
|
interrupt-parent = <&mdp>;
|
||||||
|
interrupts = <4 0>;
|
||||||
|
reg-names = "dsi_ctrl";
|
||||||
|
reg = <0xfd922800 0x200>;
|
||||||
|
power-domains = <&mmcc MDSS_GDSC>;
|
||||||
|
clock-names =
|
||||||
|
"bus",
|
||||||
|
"byte",
|
||||||
|
"core",
|
||||||
|
"core_mmss",
|
||||||
|
"iface",
|
||||||
|
"mdp_core",
|
||||||
|
"pixel";
|
||||||
|
clocks =
|
||||||
|
<&mmcc MDSS_AXI_CLK>,
|
||||||
|
<&mmcc MDSS_BYTE0_CLK>,
|
||||||
|
<&mmcc MDSS_ESC0_CLK>,
|
||||||
|
<&mmcc MMSS_MISC_AHB_CLK>,
|
||||||
|
<&mmcc MDSS_AHB_CLK>,
|
||||||
|
<&mmcc MDSS_MDP_CLK>,
|
||||||
|
<&mmcc MDSS_PCLK0_CLK>;
|
||||||
|
|
||||||
|
assigned-clocks =
|
||||||
|
<&mmcc BYTE0_CLK_SRC>,
|
||||||
|
<&mmcc PCLK0_CLK_SRC>;
|
||||||
|
assigned-clock-parents =
|
||||||
|
<&dsi_phy0 0>,
|
||||||
|
<&dsi_phy0 1>;
|
||||||
|
|
||||||
|
vdda-supply = <&pma8084_l2>;
|
||||||
|
vdd-supply = <&pma8084_l22>;
|
||||||
|
vddio-supply = <&pma8084_l12>;
|
||||||
|
|
||||||
|
phys = <&dsi_phy0>;
|
||||||
|
phy-names ="dsi-phy";
|
||||||
|
|
||||||
|
qcom,dual-dsi-mode;
|
||||||
|
qcom,master-dsi;
|
||||||
|
qcom,sync-dual-dsi;
|
||||||
|
qcom,dsi-ctrl-shared;
|
||||||
|
|
||||||
|
qcom,mdss-mdp-transfer-time-us = <12000>;
|
||||||
|
frame-threshold-time-us = <800>;
|
||||||
|
|
||||||
|
pinctrl-names = "default", "sleep";
|
||||||
|
pinctrl-0 = <&dsi_active>;
|
||||||
|
pinctrl-1 = <&dsi_suspend>;
|
||||||
|
|
||||||
|
ports {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
port@0 {
|
||||||
|
reg = <0>;
|
||||||
|
dsi0_in: endpoint {
|
||||||
|
remote-endpoint = <&mdp_intf1_out>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
port@1 {
|
||||||
|
reg = <1>;
|
||||||
|
dsi0_out: endpoint {
|
||||||
|
remote-endpoint = <&panel_in>;
|
||||||
|
data-lanes = <0 1 2 3>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
panel: panel@0 {
|
||||||
|
compatible = "sharp,lq101r1sx01";
|
||||||
|
reg = <0>;
|
||||||
|
link2 = <&secondary>;
|
||||||
|
|
||||||
|
power-supply = <...>;
|
||||||
|
backlight = <...>;
|
||||||
|
|
||||||
|
port {
|
||||||
|
panel_in: endpoint {
|
||||||
|
remote-endpoint = <&dsi0_out>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
dsi_phy0: dsi-phy@fd922a00 {
|
||||||
|
compatible = "qcom,dsi-phy-28nm-hpm";
|
||||||
|
qcom,dsi-phy-index = <0>;
|
||||||
|
reg-names =
|
||||||
|
"dsi_pll",
|
||||||
|
"dsi_phy",
|
||||||
|
"dsi_phy_regulator";
|
||||||
|
reg = <0xfd922a00 0xd4>,
|
||||||
|
<0xfd922b00 0x2b0>,
|
||||||
|
<0xfd922d80 0x7b>;
|
||||||
|
clock-names = "iface";
|
||||||
|
clocks = <&mmcc MDSS_AHB_CLK>;
|
||||||
|
#clock-cells = <1>;
|
||||||
|
vddio-supply = <&pma8084_l12>;
|
||||||
|
|
||||||
|
qcom,dsi-phy-regulator-ldo-mode;
|
||||||
|
qcom,panel-allow-phy-poweroff;
|
||||||
|
qcom,dsi-phy-regulator-min-datarate-bps = <1200000000>;
|
||||||
|
qcom,panel-force-clock-lane-hs;
|
||||||
|
pll_codes_region = <&dsi_pll_codes_data>;
|
||||||
|
qcom,dsi-phy-shared;
|
||||||
|
};
|
||||||
|
|
||||||
|
dsi_pll_codes_data:dsi_pll_codes {
|
||||||
|
reg = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||||
|
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||||
|
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||||
|
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||||
|
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||||
|
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||||
|
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||||
|
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
|
||||||
|
label = "dsi_pll_codes";
|
||||||
|
};
|
||||||
1005
bindings/mdss-dsi-panel.txt
Normal file
1005
bindings/mdss-dsi-panel.txt
Normal file
File diff suppressed because it is too large
Load Diff
14
bindings/msm_hdcp.txt
Normal file
14
bindings/msm_hdcp.txt
Normal file
@@ -0,0 +1,14 @@
|
|||||||
|
MSM HDCP driver
|
||||||
|
|
||||||
|
Standalone driver managing HDCP related communications
|
||||||
|
between TZ and HLOS for MSM chipset.
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
|
||||||
|
compatible = "qcom,msm-hdcp";
|
||||||
|
|
||||||
|
Example:
|
||||||
|
|
||||||
|
qcom_msmhdcp: qcom,msm_hdcp {
|
||||||
|
compatible = "qcom,msm-hdcp";
|
||||||
|
};
|
||||||
297
bindings/sde-dp.txt
Normal file
297
bindings/sde-dp.txt
Normal file
@@ -0,0 +1,297 @@
|
|||||||
|
Qualcomm Technologies, Inc.
|
||||||
|
sde-dp is the master Display Port device which supports DP host controllers that are compatible with VESA Display Port interface specification.
|
||||||
|
DP Controller: Required properties:
|
||||||
|
- compatible: Should be "qcom,dp-display".
|
||||||
|
- reg: Base address and length of DP hardware's memory mapped regions.
|
||||||
|
- reg-names: A list of strings that name the list of regs. "dp_ctrl" - DP controller memory region.
|
||||||
|
"dp_ahb" - AHB memory region.
|
||||||
|
"dp_aux" - AUX memory region.
|
||||||
|
"dp_link" - LINK memory region.
|
||||||
|
"dp_p0" - PCLK0 memory region.
|
||||||
|
"dp_phy" - PHY memory region.
|
||||||
|
"dp_ln_tx0" - USB3 DP PHY combo TX-0 lane memory region.
|
||||||
|
"dp_ln_tx1" - USB3 DP PHY combo TX-1 lane memory region.
|
||||||
|
"dp_mmss_cc" - Display Clock Control memory region.
|
||||||
|
"dp_pll" - USB3 DP combo PLL memory region.
|
||||||
|
"usb3_dp_com" - USB3 DP PHY combo memory region.
|
||||||
|
"hdcp_physical" - DP HDCP memory region.
|
||||||
|
"dp_p1" - DP PCLK1 memory region.
|
||||||
|
"gdsc" - DISPCC GDSC memory region.
|
||||||
|
- cell-index: Specifies the controller instance.
|
||||||
|
- #clock-cells: Denotes the DP driver as a clock producer (has one or more clock outputs)
|
||||||
|
- clocks: Clocks required for Display Port operation.
|
||||||
|
- clock-names: Names of the clocks corresponding to handles. Following clocks are required:
|
||||||
|
"core_aux_clk", "core_usb_ref_clk_src", "core_usb_pipe_clk", "link_clk",
|
||||||
|
"link_clk_src", "link_iface_clk", "pixel_clk_rcg", "pixel_parent",
|
||||||
|
"pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk".
|
||||||
|
- vdda-1p2-supply: phandle to vdda 1.2V regulator node.
|
||||||
|
- vdda-0p9-supply: phandle to vdda 0.9V regulator node.
|
||||||
|
- interrupt-parent phandle to the interrupt parent device node.
|
||||||
|
- interrupts: The interrupt signal from the DSI block.
|
||||||
|
- qcom,aux-cfg0-settings: Specifies the DP AUX configuration 0 settings. The first
|
||||||
|
entry in this array corresponds to the register offset
|
||||||
|
within DP AUX, while the remaining entries indicate the
|
||||||
|
programmable values.
|
||||||
|
- qcom,aux-cfg1-settings: Specifies the DP AUX configuration 1 settings. The first
|
||||||
|
entry in this array corresponds to the register offset
|
||||||
|
within DP AUX, while the remaining entries indicate the
|
||||||
|
programmable values.
|
||||||
|
- qcom,aux-cfg2-settings: Specifies the DP AUX configuration 2 settings. The first
|
||||||
|
entry in this array corresponds to the register offset
|
||||||
|
within DP AUX, while the remaining entries indicate the
|
||||||
|
programmable values.
|
||||||
|
- qcom,aux-cfg3-settings: Specifies the DP AUX configuration 3 settings. The first
|
||||||
|
entry in this array corresponds to the register offset
|
||||||
|
within DP AUX, while the remaining entries indicate the
|
||||||
|
programmable values.
|
||||||
|
- qcom,aux-cfg4-settings: Specifies the DP AUX configuration 4 settings. The first
|
||||||
|
entry in this array corresponds to the register offset
|
||||||
|
within DP AUX, while the remaining entries indicate the
|
||||||
|
programmable values.
|
||||||
|
- qcom,aux-cfg5-settings: Specifies the DP AUX configuration 5 settings. The first
|
||||||
|
entry in this array corresponds to the register offset
|
||||||
|
within DP AUX, while the remaining entries indicate the
|
||||||
|
programmable values.
|
||||||
|
- qcom,aux-cfg6-settings: Specifies the DP AUX configuration 6 settings. The first
|
||||||
|
entry in this array corresponds to the register offset
|
||||||
|
within DP AUX, while the remaining entries indicate the
|
||||||
|
programmable values.
|
||||||
|
- qcom,aux-cfg7-settings: Specifies the DP AUX configuration 7 settings. The first
|
||||||
|
entry in this array corresponds to the register offset
|
||||||
|
within DP AUX, while the remaining entries indicate the
|
||||||
|
programmable values.
|
||||||
|
- qcom,aux-cfg8-settings: Specifies the DP AUX configuration 8 settings. The first
|
||||||
|
entry in this array corresponds to the register offset
|
||||||
|
within DP AUX, while the remaining entries indicate the
|
||||||
|
programmable values.
|
||||||
|
- qcom,aux-cfg9-settings: Specifies the DP AUX configuration 9 settings. The first
|
||||||
|
entry in this array corresponds to the register offset
|
||||||
|
within DP AUX, while the remaining entries indicate the
|
||||||
|
programmable values.
|
||||||
|
- qcom,max-pclk-frequency-khz: An integer specifying the max. pixel clock in KHz supported by Display Port.
|
||||||
|
- qcom,mst-enable: MST feature enable control node.
|
||||||
|
- qcom,dsc-feature-enable: DSC feature enable control node.
|
||||||
|
- qcom,fec-feature-enable: FEC feature enable control node.
|
||||||
|
- qcom,qos-cpu-mask: A u32 value indicating desired PM QoS CPU affine mask
|
||||||
|
- qcom,qos-cpu-latency-us: A u32 value indicating desired PM QoS CPU latency in usec
|
||||||
|
- qcom,altmode-dev: Phandle for the AltMode GLink driver.
|
||||||
|
- usb-controller: Phandle for the USB controller.
|
||||||
|
- qcom,pll-revision: PLL hardware revision.
|
||||||
|
- usb-phy: Phandle for USB PHY driver. This is used to register for USB cable events.
|
||||||
|
- qcom,dsc-continuous-pps: Control node for sending PPS every frame in hardware for DSC over DP.
|
||||||
|
This is needed by certain bridge chips where there is such a requirement to do so.
|
||||||
|
- qcom,dp-aux-switch: Phandle for the driver used to program the AUX switch for Display Port orientation.
|
||||||
|
- qcom,dp-hpd-gpio: HPD gpio for direct DP connector without USB PHY or AUX switch.
|
||||||
|
- qcom,dp-gpio-aux-switch: Gpio DP AUX switch chipset support.
|
||||||
|
- qcom,<type>-supply-entries: A node that lists the elements of the supply used by the a particular "type" of DP module. The module "types"
|
||||||
|
can be "core", "ctrl", "pll" and "phy". Within the same type,
|
||||||
|
there can be more than one instance of this binding,
|
||||||
|
in which case the entry would be appended with the
|
||||||
|
supply entry index.
|
||||||
|
e.g. qcom,ctrl-supply-entry@0
|
||||||
|
-- qcom,supply-name: name of the supply (vdd/vdda/vddio)
|
||||||
|
-- qcom,supply-min-voltage: minimum voltage level (uV)
|
||||||
|
-- qcom,supply-max-voltage: maximum voltage level (uV)
|
||||||
|
-- qcom,supply-enable-load: load drawn (uA) from enabled supply
|
||||||
|
-- qcom,supply-disable-load: load drawn (uA) from disabled supply
|
||||||
|
-- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on
|
||||||
|
-- qcom,supply-post-on-sleep: time to sleep (ms) after turning on
|
||||||
|
-- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off
|
||||||
|
-- qcom,supply-post-off-sleep: time to sleep (ms) after turning off
|
||||||
|
|
||||||
|
msm_ext_disp is a device which manages the interaction between external
|
||||||
|
display interfaces, e.g. Display Port, and the audio subsystem.
|
||||||
|
|
||||||
|
Optional properties:
|
||||||
|
- clock-mmrm: List of the clocks that enable setting the clk rate through MMRM driver.
|
||||||
|
The order of the list must match the 'clocks' and 'clock-names'
|
||||||
|
properties. The 'DISP_CC' ID of the clock must be used to enable
|
||||||
|
the property for the respective clock, whereas a value of zero
|
||||||
|
disables the property.
|
||||||
|
- vdd_mx-supply: phandle to vdda MX regulator node
|
||||||
|
- qcom,aux-en-gpio: Specifies the aux-channel enable gpio.
|
||||||
|
- qcom,aux-sel-gpio: Specifies the aux-channel select gpio.
|
||||||
|
- qcom,usbplug-cc-gpio: Specifies the usbplug orientation gpio.
|
||||||
|
- qcom,ext-disp: phandle for msm-ext-display module
|
||||||
|
- compatible: Must be "qcom,msm-ext-disp"
|
||||||
|
- qcom,dp-low-power-hw-hpd: Low power hardware HPD feature enable control node
|
||||||
|
- qcom,phy-version: Phy version
|
||||||
|
- qcom,pn-swap-lane-map: P/N swap configuration of each lane
|
||||||
|
- pinctrl-names: List of names to assign mdss pin states defined in pinctrl device node
|
||||||
|
Refer to pinctrl-bindings.txt
|
||||||
|
- pinctrl-<0..n>: Lists phandles each pointing to the pin configuration node within a pin
|
||||||
|
controller. These pin configurations are installed in the pinctrl
|
||||||
|
device node. Refer to pinctrl-bindings.txt
|
||||||
|
- qcom,max-lclk-frequency-khz: An integer specifying the max. link clock in KHz supported by Display Port.
|
||||||
|
- qcom,mst-fixed-topology-ports: u32 values of which MST output port to reserve, start from one
|
||||||
|
- qcom,hbr-rbr-voltage-swing: Specifies the voltage swing levels for HBR and RBR rates.
|
||||||
|
- qcom,hbr-rbr-pre-emphasis: Specifies the pre-emphasis levels for HBR and RBR rates.
|
||||||
|
- qcom,hbr2-3-voltage-swing: Specifies the voltage swing levels for HBR2 and HBR3 rates.
|
||||||
|
- qcom,hbr2-3-pre-emphasis: Specifies the pre-emphasis levels for HBR2 and HBR3 rates.
|
||||||
|
|
||||||
|
[Optional child nodes]: These nodes are for devices which are
|
||||||
|
dependent on msm_ext_disp. If msm_ext_disp is disabled then
|
||||||
|
these devices will be disabled as well. Ex. Audio Codec device.
|
||||||
|
|
||||||
|
- ext_disp_audio_codec: Node for Audio Codec.
|
||||||
|
- compatible : "qcom,msm-ext-disp-audio-codec-rx";
|
||||||
|
|
||||||
|
Example:
|
||||||
|
|
||||||
|
ext_disp: qcom,msm-ext-disp {
|
||||||
|
compatible = "qcom,msm-ext-disp";
|
||||||
|
|
||||||
|
ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
|
||||||
|
compatible = "qcom,msm-ext-disp-audio-codec-rx";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
sde_dp: qcom,dp_display@0 {
|
||||||
|
cell-index = <0>;
|
||||||
|
compatible = "qcom,dp-display";
|
||||||
|
|
||||||
|
qcom,dp-aux-switch = <&fsa4480>;
|
||||||
|
qcom,ext-disp = <&ext_disp>;
|
||||||
|
qcom,altmode-dev = <&altmode 0>;
|
||||||
|
usb-controller = <&usb0>;
|
||||||
|
|
||||||
|
reg = <0xae90000 0x0dc>,
|
||||||
|
<0xae90200 0x0c0>,
|
||||||
|
<0xae90400 0x508>,
|
||||||
|
<0xae91000 0x094>,
|
||||||
|
<0x88eaa00 0x200>,
|
||||||
|
<0x88ea200 0x200>,
|
||||||
|
<0x88ea600 0x200>,
|
||||||
|
<0xaf02000 0x1a0>,
|
||||||
|
<0x88ea000 0x200>,
|
||||||
|
<0x88e8000 0x20>,
|
||||||
|
<0x0aee1000 0x034>,
|
||||||
|
<0xae91400 0x094>,
|
||||||
|
<0xaf03000 0x8>;
|
||||||
|
reg-names = "dp_ahb", "dp_aux", "dp_link",
|
||||||
|
"dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
|
||||||
|
"dp_mmss_cc", "dp_pll", "usb3_dp_com",
|
||||||
|
"hdcp_physical", "dp_p1", "gdsc";
|
||||||
|
|
||||||
|
interrupt-parent = <&mdss_mdp>;
|
||||||
|
interrupts = <12 0>;
|
||||||
|
|
||||||
|
#clock-cells = <1>;
|
||||||
|
clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>,
|
||||||
|
<&clock_rpmh RPMH_CXO_CLK>,
|
||||||
|
<&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
|
||||||
|
<&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>,
|
||||||
|
<&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
|
||||||
|
<&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
|
||||||
|
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
|
||||||
|
<&sde_dp DP_PHY_PLL_VCO_DIV_CLK>,
|
||||||
|
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>,
|
||||||
|
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
|
||||||
|
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
|
||||||
|
clock-names = "core_aux_clk", "core_usb_ref_clk_src",
|
||||||
|
"core_usb_pipe_clk", "link_clk", "link_clk_src",
|
||||||
|
"link_iface_clk", "pixel_clk_rcg", "pixel_parent",
|
||||||
|
"pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk";
|
||||||
|
clock-mmrm = <0 0 0 0 DISP_CC_MDSS_DP_LINK_CLK_SRC 0 0 0 0 0 0>;
|
||||||
|
|
||||||
|
qcom,pll-revision = "5nm-v1";
|
||||||
|
qcom,phy-version = <0x420>;
|
||||||
|
qcom,dp-aux-switch = <&fsa4480>;
|
||||||
|
|
||||||
|
qcom,aux-cfg0-settings = [1c 00];
|
||||||
|
qcom,aux-cfg1-settings = [20 13 23 1d];
|
||||||
|
qcom,aux-cfg2-settings = [24 00];
|
||||||
|
qcom,aux-cfg3-settings = [28 00];
|
||||||
|
qcom,aux-cfg4-settings = [2c 0a];
|
||||||
|
qcom,aux-cfg5-settings = [30 26];
|
||||||
|
qcom,aux-cfg6-settings = [34 0a];
|
||||||
|
qcom,aux-cfg7-settings = [38 03];
|
||||||
|
qcom,aux-cfg8-settings = [3c bb];
|
||||||
|
qcom,aux-cfg9-settings = [40 03];
|
||||||
|
qcom,max-pclk-frequency-khz = <593470>;
|
||||||
|
qcom,mst-enable;
|
||||||
|
qcom,dsc-feature-enable;
|
||||||
|
qcom,fec-feature-enable;
|
||||||
|
qcom,dsc-continuous-pps;
|
||||||
|
qcom,qos-cpu-mask = <0xf>;
|
||||||
|
qcom,qos-cpu-latency-us = <300>;
|
||||||
|
vdda-1p2-supply = <&L6B>;
|
||||||
|
vdda-0p9-supply = <&L1B>;
|
||||||
|
vdd_mx-supply = <&VDD_MXA_LEVEL>;
|
||||||
|
|
||||||
|
qcom,hbr-rbr-voltage-swing = <0x07 0x0f 0x16 0x1f>,
|
||||||
|
<0x11 0x1e 0x1f 0xff>,
|
||||||
|
<0x16 0x1f 0xff 0xff>,
|
||||||
|
<0x1f 0xff 0xff 0xff>;
|
||||||
|
qcom,hbr-rbr-pre-emphasis = <0x00 0x0d 0x14 0x1a>,
|
||||||
|
<0x00 0x0e 0x15 0xff>,
|
||||||
|
<0x00 0x0e 0xff 0xff>,
|
||||||
|
<0x02 0xff 0xff 0xff>;
|
||||||
|
|
||||||
|
qcom,hbr2-3-voltage-swing = <0x02 0x12 0x16 0x1a>,
|
||||||
|
<0x09 0x19 0x1f 0xff>,
|
||||||
|
<0x10 0x1f 0xff 0xff>,
|
||||||
|
<0x1f 0xff 0xff 0xff>;
|
||||||
|
qcom,hbr2-3-pre-emphasis = <0x00 0x0c 0x15 0x1b>,
|
||||||
|
<0x02 0x0e 0x16 0xff>,
|
||||||
|
<0x02 0x11 0xff 0xff>,
|
||||||
|
<0x04 0xff 0xff 0xff>;
|
||||||
|
|
||||||
|
qcom,ctrl-supply-entries {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
qcom,ctrl-supply-entry@0 {
|
||||||
|
reg = <0>;
|
||||||
|
qcom,supply-name = "vdda-1p2";
|
||||||
|
qcom,supply-min-voltage = <1200000>;
|
||||||
|
qcom,supply-max-voltage = <1200000>;
|
||||||
|
qcom,supply-enable-load = <21700>;
|
||||||
|
qcom,supply-disable-load = <0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
qcom,phy-supply-entries {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
qcom,phy-supply-entry@0 {
|
||||||
|
reg = <0>;
|
||||||
|
qcom,supply-name = "vdda-0p9";
|
||||||
|
qcom,supply-min-voltage = <912000>;
|
||||||
|
qcom,supply-max-voltage = <912000>;
|
||||||
|
qcom,supply-enable-load = <115000>;
|
||||||
|
qcom,supply-disable-load = <0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
qcom,core-supply-entries {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
qcom,core-supply-entry@0 {
|
||||||
|
reg = <0>;
|
||||||
|
qcom,supply-name = "refgen";
|
||||||
|
qcom,supply-min-voltage = <0>;
|
||||||
|
qcom,supply-max-voltage = <0>;
|
||||||
|
qcom,supply-enable-load = <0>;
|
||||||
|
qcom,supply-disable-load = <0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
qcom,pll-supply-entries {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
qcom,pll-supply-entry@0 {
|
||||||
|
reg = <0>;
|
||||||
|
qcom,supply-name = "vdd_mx";
|
||||||
|
qcom,supply-min-voltage =
|
||||||
|
<RPMH_REGULATOR_LEVEL_TURBO>;
|
||||||
|
qcom,supply-max-voltage =
|
||||||
|
<RPMH_REGULATOR_LEVEL_MAX>;
|
||||||
|
qcom,supply-enable-load = <0>;
|
||||||
|
qcom,supply-disable-load = <0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
130
bindings/sde-dsi.txt
Normal file
130
bindings/sde-dsi.txt
Normal file
@@ -0,0 +1,130 @@
|
|||||||
|
Qualcomm Technologies, Inc.
|
||||||
|
|
||||||
|
mdss-dsi is the master DSI device which supports multiple DSI host controllers
|
||||||
|
that are compatible with MIPI display serial interface specification.
|
||||||
|
|
||||||
|
DSI Controller and PHY:
|
||||||
|
Required properties:
|
||||||
|
- compatible: Should be "qcom,dsi-ctrl-hw-v<version>". Supported
|
||||||
|
versions include 2.4, 2.5, and 2.6.
|
||||||
|
eg: qcom,dsi-ctrl-hw-v2.2, qcom,dsi-ctrl-hw-v2.3,
|
||||||
|
qcom,dsi-ctrl-hw-v2.4, qcom,dsi-ctrl-hw-v2.5,
|
||||||
|
qcom,dsi-ctrl-hw-v2.6
|
||||||
|
And for dsi phy driver:
|
||||||
|
qcom,dsi-phy-v3.0, qcom,dsi-phy-v4.0,
|
||||||
|
qcom,dsi-phy-v4.1, qcom,dsi-phy-v4.2
|
||||||
|
- reg: List of base address and length of memory mapped
|
||||||
|
regions of DSI controller, disp_cc and mdp_intf.
|
||||||
|
- reg-names: A list of strings that name the list of regs.
|
||||||
|
"dsi_ctrl" - DSI controller memory region.
|
||||||
|
"disp_cc_base" - Base address of disp_cc memory region.
|
||||||
|
"mdp_intf_base" - Base address of mdp_intf memory region.
|
||||||
|
- cell-index: Specifies the controller instance.
|
||||||
|
- clocks: Clocks required for DSI controller operation.
|
||||||
|
- clock-names: Names of the clocks corresponding to handles. Following
|
||||||
|
clocks are required:
|
||||||
|
"mdp_core_clk"
|
||||||
|
"iface_clk"
|
||||||
|
"core_mmss_clk"
|
||||||
|
"bus_clk"
|
||||||
|
"byte_clk"
|
||||||
|
"pixel_clk"
|
||||||
|
"core_clk"
|
||||||
|
"byte_clk_rcg"
|
||||||
|
"pixel_clk_rcg"
|
||||||
|
- pll-label Supported versions of DSI PLL:
|
||||||
|
dsi_pll_5nm
|
||||||
|
- gdsc-supply: phandle to gdsc regulator node.
|
||||||
|
- vdda-supply: phandle to vdda regulator node.
|
||||||
|
- vcca-supply: phandle to vcca regulator node.
|
||||||
|
- interrupt-parent phandle to the interrupt parent device node.
|
||||||
|
- interrupts: The interrupt signal from the DSI block.
|
||||||
|
- qcom,dsi-default-panel: Specifies the default panel.
|
||||||
|
- qcom,mdp: Specifies the mdp node which can find panel node from this.
|
||||||
|
- qcom,demura-panel-id: Specifies the u64 demura panel ID as an array <2>
|
||||||
|
If demura is not used this node must be set to <0,0>.
|
||||||
|
|
||||||
|
Bus Scaling Data:
|
||||||
|
- qcom,msm-bus,name: String property describing MDSS client.
|
||||||
|
- qcom,msm-bus,num-cases: This is the number of bus scaling use cases
|
||||||
|
defined in the vectors property. This must be
|
||||||
|
set to <2> for MDSS DSI driver where use-case 0
|
||||||
|
is used to remove BW votes from the system. Use
|
||||||
|
case 1 is used to generate bandwidth requestes
|
||||||
|
when sending command packets.
|
||||||
|
- qcom,msm-bus,num-paths: This represents number of paths in each bus
|
||||||
|
scaling usecase. This value depends on number of
|
||||||
|
AXI master ports dedicated to MDSS for
|
||||||
|
particular chipset.
|
||||||
|
- qcom,msm-bus,vectors-KBps: A series of 4 cell properties, with a format
|
||||||
|
of (src, dst, ab, ib) which is defined at
|
||||||
|
Documentation/devicetree/bindings/arm/msm/msm_bus.txt.
|
||||||
|
DSI driver should always set average bandwidth
|
||||||
|
(ab) to 0 and always use instantaneous
|
||||||
|
bandwidth(ib) values.
|
||||||
|
|
||||||
|
Optional properties:
|
||||||
|
- label: String to describe controller.
|
||||||
|
- qcom,platform-te-gpio: Specifies the gpio used for TE.
|
||||||
|
- qcom,panel-te-source: Specifies the source pin for Vsync from panel or WD Timer.
|
||||||
|
- qcom,dsi-ctrl: handle to dsi controller device
|
||||||
|
- qcom,dsi-phy: handle to dsi phy device
|
||||||
|
- qcom,dsi-ctrl-num: Specifies the DSI controllers to use for primary panel
|
||||||
|
- qcom,dsi-sec-ctrl-num: Specifies the DSI controllers to use for secondary panel
|
||||||
|
- qcom,dsi-phy-num: Specifies the DSI PHYs to use for primary panel
|
||||||
|
- qcom,dsi-sec-phy-num: Specifies the DSI PHYs to use for secondary panel
|
||||||
|
- qcom,dsi-select-clocks: Specifies the required clocks to use for primary panel
|
||||||
|
- qcom,dsi-select-sec-clocks: Specifies the required clocks to use for secondary panel
|
||||||
|
- qcom,dsi-display-list: Specifies the list of supported displays.
|
||||||
|
- qcom,dsi-manager: Specifies dsi manager is present
|
||||||
|
- qcom,dsi-display: Specifies dsi display is present
|
||||||
|
- qcom,hdmi-display: Specifies hdmi is present
|
||||||
|
- qcom,dp-display: Specified dp is present
|
||||||
|
- qcom,<type>-supply-entries: A node that lists the elements of the supply used by the
|
||||||
|
a particular "type" of DSI module. The module "types"
|
||||||
|
can be "core", "ctrl", and "phy". Within the same type,
|
||||||
|
there can be more than one instance of this binding,
|
||||||
|
in which case the entry would be appended with the
|
||||||
|
supply entry index.
|
||||||
|
e.g. qcom,ctrl-supply-entry@0
|
||||||
|
-- qcom,supply-name: name of the supply (vdd/vdda/vddio)
|
||||||
|
-- qcom,supply-min-voltage: minimum voltage level (uV)
|
||||||
|
-- qcom,supply-max-voltage: maximum voltage level (uV)
|
||||||
|
-- qcom,supply-enable-load: load drawn (uA) from enabled supply
|
||||||
|
-- qcom,supply-disable-load: load drawn (uA) from disabled supply
|
||||||
|
-- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on
|
||||||
|
-- qcom,supply-post-on-sleep: time to sleep (ms) after turning on
|
||||||
|
-- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off
|
||||||
|
-- qcom,supply-post-off-sleep: time to sleep (ms) after turning off
|
||||||
|
- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode
|
||||||
|
panels in microseconds. Driver uses this number to adjust
|
||||||
|
the clock rate according to the expected transfer time.
|
||||||
|
Increasing this value would slow down the mdp processing
|
||||||
|
and can result in slower performance.
|
||||||
|
Decreasing this value can speed up the mdp processing,
|
||||||
|
but this can also impact power consumption.
|
||||||
|
As a rule this time should not be higher than the time
|
||||||
|
that would be expected with the processing at the
|
||||||
|
dsi link rate since anyways this would be the maximum
|
||||||
|
transfer time that could be achieved.
|
||||||
|
If ping pong split enabled, this time should not be higher
|
||||||
|
than two times the dsi link rate time.
|
||||||
|
If the property is not specified, then the default value is 14000 us.
|
||||||
|
- qcom,dsi-phy-pll-bypass: A boolean property that enables bypassing hardware access in DSI
|
||||||
|
PHY/PLL drivers to allow the DSI driver to run on emulation platforms
|
||||||
|
that might be missing those modules.
|
||||||
|
- - qcom,null-insertion-enabled: A boolean to enable NULL packet insertion feature for DSI controller.
|
||||||
|
- ports: This video port is used when external bridge is present.
|
||||||
|
The connection is modeled using the OF graph bindings
|
||||||
|
specified in Documentation/devicetree/bindings/graph.txt.
|
||||||
|
Video port 0 reg 0 is for the bridge output. The remote
|
||||||
|
endpoint phandle should be mipi_dsi_device device node.
|
||||||
|
- qcom,dsi-pll-ssc-en: Boolean property to indicate that ssc is enabled.
|
||||||
|
- qcom,dsi-pll-ssc-mode: Spread-spectrum clocking. It can be either "down-spread"
|
||||||
|
or "center-spread". Default is "down-spread" if it is not specified.
|
||||||
|
- qcom,ssc-frequency-hz: Integer property to specify the spread frequency
|
||||||
|
to be programmed for the SSC.
|
||||||
|
- qcom,ssc-ppm: Integer property to specify the Parts per Million
|
||||||
|
value of SSC.
|
||||||
|
- qcom,avdd-regulator-gpio: Specifies the gpio pin used for avdd
|
||||||
|
power supply regulator.
|
||||||
23
bindings/sde-wb.txt
Normal file
23
bindings/sde-wb.txt
Normal file
@@ -0,0 +1,23 @@
|
|||||||
|
Qualcomm Technologies, Inc. Snapdragon Display Engine (SDE) writeback display
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
- compatible: "qcom,wb-display"
|
||||||
|
|
||||||
|
Optional properties:
|
||||||
|
- cell-index: Index of writeback device instance.
|
||||||
|
Default to 0 if not specified.
|
||||||
|
- label: String to describe this writeback display.
|
||||||
|
Default to "unknown" if not specified.
|
||||||
|
|
||||||
|
Example:
|
||||||
|
|
||||||
|
/ {
|
||||||
|
...
|
||||||
|
|
||||||
|
sde_wb: qcom,wb-display {
|
||||||
|
compatible = "qcom,wb-display";
|
||||||
|
cell-index = <2>;
|
||||||
|
label = "wb_display";
|
||||||
|
};
|
||||||
|
|
||||||
|
};
|
||||||
1081
bindings/sde.txt
Normal file
1081
bindings/sde.txt
Normal file
File diff suppressed because it is too large
Load Diff
335
display/sun-sde-common.dtsi
Normal file
335
display/sun-sde-common.dtsi
Normal file
@@ -0,0 +1,335 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||||
|
|
||||||
|
&soc {
|
||||||
|
mdss_mdp: qcom,mdss_mdp@ae00000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
compatible = "qcom,sde-kms";
|
||||||
|
reg = <0x0ae00000 0x93800>,
|
||||||
|
<0x0aeb0000 0x2008>,
|
||||||
|
<0x0af80000 0x7000>;
|
||||||
|
reg-names = "mdp_phys",
|
||||||
|
"vbif_phys",
|
||||||
|
"regdma_phys";
|
||||||
|
|
||||||
|
/* interrupt config */
|
||||||
|
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
#cooling-cells = <2>;
|
||||||
|
|
||||||
|
/* hw blocks */
|
||||||
|
qcom,sde-off = <0x1000>;
|
||||||
|
qcom,sde-len = <0x488>;
|
||||||
|
|
||||||
|
qcom,sde-ctl-off = <0x16000 0x17000 0x18000
|
||||||
|
0x19000 0x1a000 0x1b000>;
|
||||||
|
qcom,sde-ctl-size = <0x1000>;
|
||||||
|
qcom,sde-ctl-display-pref = "primary", "none", "none",
|
||||||
|
"none", "none", "none";
|
||||||
|
|
||||||
|
qcom,sde-mixer-off = <0x45000 0x46000 0x47000
|
||||||
|
0x48000 0x49000 0x4a000
|
||||||
|
0x4b000 0x4c000 0x0f0f
|
||||||
|
0x0f0f 0x0f0f 0x0f0f>;
|
||||||
|
qcom,sde-mixer-size = <0x400>;
|
||||||
|
qcom,sde-mixer-display-pref = "primary", "primary", "none",
|
||||||
|
"none", "none", "none", "none", "none",
|
||||||
|
"none", "none", "none", "none";
|
||||||
|
|
||||||
|
qcom,sde-mixer-dcwb-pref = "none", "none", "none", "none",
|
||||||
|
"none", "none", "none", "none",
|
||||||
|
"dcwb", "dcwb", "dcwb", "dcwb";
|
||||||
|
|
||||||
|
qcom,sde-dspp-top-off = <0x1300>;
|
||||||
|
qcom,sde-dspp-top-size = <0x8c>;
|
||||||
|
|
||||||
|
qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>;
|
||||||
|
qcom,sde-dspp-size = <0x1800>;
|
||||||
|
|
||||||
|
qcom,sde-dspp-rc-version = <0x00010001>;
|
||||||
|
qcom,sde-dspp-rc-off = <0x15800 0x14800 0x13800 0x12800>;
|
||||||
|
qcom,sde-dspp-rc-size = <0x100>;
|
||||||
|
qcom,sde-dspp-rc-mem-size = <2720>;
|
||||||
|
qcom,sde-dspp-rc-min-region-width = <20>;
|
||||||
|
|
||||||
|
qcom,sde-dnsc-blur-version = <0x100>;
|
||||||
|
qcom,sde-dnsc-blur-off = <0x7D000>;
|
||||||
|
qcom,sde-dnsc-blur-size = <0x40>;
|
||||||
|
qcom,sde-dnsc-blur-gaus-lut-off = <0x100>;
|
||||||
|
qcom,sde-dnsc-blur-gaus-lut-size = <0x400>;
|
||||||
|
qcom,sde-dnsc-blur-dither-off = <0x5E0>;
|
||||||
|
qcom,sde-dnsc-blur-dither-size = <0x20>;
|
||||||
|
|
||||||
|
qcom,sde-dest-scaler-top-off = <0x0008F000>;
|
||||||
|
qcom,sde-dest-scaler-top-size = <0x1C>;
|
||||||
|
qcom,sde-dest-scaler-off = <0x0 0x1000 0x2000 0x3000>;
|
||||||
|
qcom,sde-dest-scaler-size = <0x800>;
|
||||||
|
|
||||||
|
qcom,sde-wb-off = <0x65000 0x66000>;
|
||||||
|
qcom,sde-wb-size = <0x2c8>;
|
||||||
|
qcom,sde-wb-xin-id = <0xa 6>;
|
||||||
|
qcom,sde-wb-id = <1 2>;
|
||||||
|
|
||||||
|
qcom,sde-intf-off = <0x35000 0x36000 0x37000 0x38000>;
|
||||||
|
qcom,sde-intf-size = <0x4BC>;
|
||||||
|
qcom,sde-intf-type = "dp", "dsi", "dsi", "dp";
|
||||||
|
qcom,sde-intf-tear-irq-off = <0 0x36800 0x37800 0>;
|
||||||
|
|
||||||
|
qcom,sde-pp-off = <0x6a000 0x6b000 0x6c000 0x6d000
|
||||||
|
0x6e000 0x6f000 0x70000 0x71000
|
||||||
|
0x67000 0x67400 0x7f000 0x7f400>;
|
||||||
|
qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
|
||||||
|
qcom,sde-pp-size = <0x2c>;
|
||||||
|
qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1 0x2 0x2 0x3 0x3 0x4 0x4 0x5 0x5>;
|
||||||
|
|
||||||
|
qcom,sde-merge-3d-off = <0x4f000 0x50000 0x51000 0x52000 0x67700 0x7f700>;
|
||||||
|
qcom,sde-merge-3d-size = <0x1c>;
|
||||||
|
qcom,sde-pp-cwb = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1>;
|
||||||
|
|
||||||
|
qcom,sde-cdm-off = <0x7a200>;
|
||||||
|
qcom,sde-cdm-size = <0x240>;
|
||||||
|
|
||||||
|
qcom,sde-dsc-off = <0x81000 0x81000 0x82000 0x82000 0x83000 0x83000 0x84000 0x84000>;
|
||||||
|
qcom,sde-dsc-size = <0x8>;
|
||||||
|
qcom,sde-dsc-pair-mask = <2 1 4 3 6 5 8 7>;
|
||||||
|
qcom,sde-dsc-hw-rev = "dsc_1_2";
|
||||||
|
qcom,sde-dsc-enc = <0x100 0x200 0x100 0x200 0x100 0x200 0x100 0x200>;
|
||||||
|
qcom,sde-dsc-enc-size = <0x100>;
|
||||||
|
qcom,sde-dsc-ctl = <0xF00 0xF80 0xF00 0xF80 0xF00 0xF80 0xF00 0xF80>;
|
||||||
|
qcom,sde-dsc-ctl-size = <0x24>;
|
||||||
|
qcom,sde-dsc-native422-supp = <1 1 1 1 1 1 1 1>;
|
||||||
|
|
||||||
|
qcom,sde-dither-off = <0xe0 0xe0 0xe0
|
||||||
|
0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0>;
|
||||||
|
qcom,sde-cwb-dither = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1>;
|
||||||
|
qcom,sde-dither-version = <0x00020000>;
|
||||||
|
qcom,sde-dither-size = <0x20>;
|
||||||
|
|
||||||
|
qcom,sde-sspp-type = "vig", "vig", "vig", "vig",
|
||||||
|
"dma", "dma", "dma", "dma", "dma", "dma";
|
||||||
|
qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000
|
||||||
|
0x25000 0x27000 0x29000 0x2b000 0x2d000 0x2f000>;
|
||||||
|
qcom,sde-sspp-src-size = <0x344>;
|
||||||
|
|
||||||
|
qcom,sde-sspp-xin-id = <0 4 8 12 1 5 9 13 14 15>;
|
||||||
|
qcom,sde-sspp-excl-rect = <1 1 1 1 1 1 1 1 1 1>;
|
||||||
|
qcom,sde-sspp-smart-dma-priority = <7 8 9 10 1 2 3 4 5 6>;
|
||||||
|
qcom,sde-smart-dma-rev = "smart_dma_v2p5";
|
||||||
|
|
||||||
|
qcom,sde-mixer-pair-mask = <2 1 4 3 6 5 8 7 10 9 12 11>;
|
||||||
|
|
||||||
|
qcom,sde-mixer-blend-op-off = <0x40 0x70 0xa0 0xd0 0x100 0x130
|
||||||
|
0x160 0x190 0x1c0 0x1f0 0x220>;
|
||||||
|
|
||||||
|
qcom,sde-max-per-pipe-bw-kbps = <4500000 4500000
|
||||||
|
4500000 4500000
|
||||||
|
4500000 4500000
|
||||||
|
4500000 4500000
|
||||||
|
4500000 4500000>;
|
||||||
|
|
||||||
|
qcom,sde-max-per-pipe-bw-high-kbps = <5700000 5700000
|
||||||
|
5700000 5700000
|
||||||
|
5700000 5700000
|
||||||
|
5700000 5700000
|
||||||
|
5700000 5700000>;
|
||||||
|
|
||||||
|
/* offsets are relative to "mdp_phys + qcom,sde-off */
|
||||||
|
qcom,sde-sspp-clk-ctrl =
|
||||||
|
<0x4330 0>, <0x6330 0>, <0x8330 0>, <0xa330 0>,
|
||||||
|
<0x24330 0>, <0x26330 0>, <0x28330 0>, <0x2a330 0>,
|
||||||
|
<0x2c330 0>, <0x2e330 0>;
|
||||||
|
qcom,sde-sspp-clk-status =
|
||||||
|
<0x4334 0>, <0x6334 0>, <0x8334 0>, <0xa334 0>,
|
||||||
|
<0x24334 0>, <0x26334 0>, <0x28334 0>, <0x2a334 0>,
|
||||||
|
<0x2c334 0>, <0x2e334 0>;
|
||||||
|
qcom,sde-sspp-csc-off = <0x1a00>;
|
||||||
|
qcom,sde-csc-type = "csc-10bit";
|
||||||
|
qcom,sde-qseed-sw-lib-rev = "qseedv3lite";
|
||||||
|
qcom,sde-qseed-scalar-version = <0x3004>;
|
||||||
|
qcom,sde-sspp-qseed-off = <0xa00>;
|
||||||
|
qcom,sde-mixer-linewidth = <2560>;
|
||||||
|
qcom,sde-sspp-linewidth = <5120>;
|
||||||
|
qcom,sde-wb-linewidth = <4096>;
|
||||||
|
qcom,sde-dsc-linewidth = <2560>;
|
||||||
|
qcom,sde-max-dest-scaler-input-linewidth = <2048>;
|
||||||
|
qcom,sde-max-dest-scaler-output-linewidth = <2560>;
|
||||||
|
qcom,sde-wb-linewidth-linear = <8192>;
|
||||||
|
qcom,sde-mixer-blendstages = <0xb>;
|
||||||
|
qcom,sde-highest-bank-bit = <0x8 0x3>,
|
||||||
|
<0x7 0x2>;
|
||||||
|
qcom,sde-ubwc-version = <0x50000001>;
|
||||||
|
qcom,sde-ubwc-swizzle = <0x6>;
|
||||||
|
qcom,sde-ubwc-bw-calc-version = <0x1>;
|
||||||
|
qcom,sde-ubwc-static = <0x1>;
|
||||||
|
qcom,sde-macrotile-mode = <0x1>;
|
||||||
|
qcom,sde-smart-panel-align-mode = <0xc>;
|
||||||
|
qcom,sde-panic-per-pipe;
|
||||||
|
qcom,sde-has-cdp;
|
||||||
|
qcom,sde-has-src-split;
|
||||||
|
qcom,sde-pipe-order-version = <0x1>;
|
||||||
|
qcom,sde-has-dim-layer;
|
||||||
|
qcom,sde-has-dest-scaler;
|
||||||
|
qcom,sde-max-trusted-vm-displays = <1>;
|
||||||
|
|
||||||
|
qcom,sde-max-bw-low-kbps = <17000000>;
|
||||||
|
qcom,sde-max-bw-high-kbps = <27000000>;
|
||||||
|
qcom,sde-min-core-ib-kbps = <2500000>;
|
||||||
|
qcom,sde-min-llcc-ib-kbps = <0>;
|
||||||
|
qcom,sde-min-dram-ib-kbps = <800000>;
|
||||||
|
qcom,sde-dram-channels = <4>;
|
||||||
|
qcom,sde-num-nrt-paths = <0>;
|
||||||
|
|
||||||
|
qcom,sde-dspp-spr-off = <0x15400 0x14400 0x13400 0x12400>;
|
||||||
|
qcom,sde-dspp-spr-size = <0x200>;
|
||||||
|
qcom,sde-dspp-spr-version = <0x00020000>;
|
||||||
|
|
||||||
|
qcom,sde-dspp-demura-off = <0x15600 0x14600 0x13600 0x12600>;
|
||||||
|
qcom,sde-dspp-demura-size = <0xe4>;
|
||||||
|
qcom,sde-dspp-demura-version = <0x00020000>;
|
||||||
|
|
||||||
|
qcom,sde-lm-noise-off = <0x320>;
|
||||||
|
qcom,sde-lm-noise-version = <0x00010000>;
|
||||||
|
|
||||||
|
qcom,sde-uidle-off = <0x80000>;
|
||||||
|
qcom,sde-uidle-size = <0x80>;
|
||||||
|
|
||||||
|
qcom,sde-vbif-off = <0>;
|
||||||
|
qcom,sde-vbif-size = <0x1074>;
|
||||||
|
qcom,sde-vbif-id = <0>;
|
||||||
|
qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
|
||||||
|
qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3 3 3>;
|
||||||
|
|
||||||
|
qcom,sde-vbif-default-ot-rd-limit = <40>;
|
||||||
|
qcom,sde-vbif-default-ot-wr-limit = <32>;
|
||||||
|
qcom,sde-vbif-dynamic-ot-wr-limit = <62208000 2 124416000 6 497664000 16>;
|
||||||
|
|
||||||
|
qcom,sde-vbif-qos-rt-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>;
|
||||||
|
qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>;
|
||||||
|
qcom,sde-vbif-qos-cwb-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>;
|
||||||
|
qcom,sde-vbif-qos-lutdma-remap = <4 4 4 4 5 5 5 5 4 4 4 4 5 5 5 5>;
|
||||||
|
qcom,sde-vbif-qos-offline-wb-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>;
|
||||||
|
qcom,sde-vbif-qos-cnoc-remap = <3 3 4 4 5 5 5 5 3 3 4 4 5 5 5 5>;
|
||||||
|
qcom,sde-vbif-qos-wb-rot-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>;
|
||||||
|
|
||||||
|
qcom,sde-danger-lut = <0xffff 0xffff 0xffff 0xffff 0x0 0x0 0x0 0x0
|
||||||
|
0x0 0x0 0xffff 0xffff 0xffff 0xffff 0x0 0x0 0xffff0000 0xffff0000>;
|
||||||
|
|
||||||
|
qcom,sde-safe-lut = <0xff00 0xfff0 0xff00 0xfff0 0xffff 0xffff 0x0001 0x0001
|
||||||
|
0x03ff 0x03ff 0xff00 0xfff0 0xff00 0xfff0 0xffff 0xffff 0xff 0xff>;
|
||||||
|
|
||||||
|
qcom,sde-creq-lut = <0x00112233 0x44556666 0x00112233 0x66666666
|
||||||
|
0x00112233 0x44556666 0x00112233 0x66666666
|
||||||
|
0x0 0x0 0x0 0x0
|
||||||
|
0x77776666 0x66666540 0x77776666 0x66666540
|
||||||
|
0x77776541 0x0 0x77776541 0x0
|
||||||
|
0x00112233 0x44556666 0x00112233 0x66666666
|
||||||
|
0x00112233 0x44556666 0x00112233 0x66666666
|
||||||
|
0x0 0x0 0x0 0x0
|
||||||
|
0x55555544 0x33221100 0x55555544 0x33221100>;
|
||||||
|
|
||||||
|
qcom,sde-cdp-setting = <1 1>, <1 0>;
|
||||||
|
|
||||||
|
qcom,sde-qos-cpu-mask-performance = <0x3>;
|
||||||
|
qcom,sde-qos-cpu-dma-latency = <300>;
|
||||||
|
qcom,sde-qos-cpu-irq-latency = <300>;
|
||||||
|
|
||||||
|
/* offsets are relative to "mdp_phys + qcom,sde-off */
|
||||||
|
qcom,sde-reg-dma-off = <0 0x800>;
|
||||||
|
qcom,sde-reg-dma-id = <0 1>;
|
||||||
|
qcom,sde-reg-dma-version = <0x00030000>;
|
||||||
|
qcom,sde-reg-dma-trigger-off = <0x119c>;
|
||||||
|
qcom,sde-reg-dma-xin-id = <7>;
|
||||||
|
qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>;
|
||||||
|
|
||||||
|
qcom,sde-secure-sid-mask = <0x0002801 0x0002c01>;
|
||||||
|
|
||||||
|
qcom,sde-reg-bus,vectors-KBps = <0 0>,
|
||||||
|
<0 14000>,
|
||||||
|
<0 140000>,
|
||||||
|
<0 310000>;
|
||||||
|
|
||||||
|
qcom,sde-sspp-vig-blocks {
|
||||||
|
vcm@0 {
|
||||||
|
cell-index = <0>;
|
||||||
|
qcom,sde-vig-top-off = <0x700>;
|
||||||
|
qcom,sde-vig-csc-off = <0x1a00>;
|
||||||
|
qcom,sde-vig-qseed-off = <0xa00>;
|
||||||
|
qcom,sde-vig-qseed-size = <0xe0>;
|
||||||
|
qcom,sde-vig-gamut = <0x1d00 0x00060001>;
|
||||||
|
qcom,sde-vig-igc = <0x1d00 0x00060000>;
|
||||||
|
qcom,sde-vig-inverse-pma;
|
||||||
|
qcom,sde-fp16-igc = <0x200 0x00010000>;
|
||||||
|
qcom,sde-fp16-unmult = <0x200 0x00010000>;
|
||||||
|
qcom,sde-fp16-gc = <0x200 0x00010000>;
|
||||||
|
qcom,sde-fp16-csc = <0x200 0x00010000>;
|
||||||
|
qcom,sde-ucsc-igc = <0x700 0x00010000>;
|
||||||
|
qcom,sde-ucsc-unmult = <0x700 0x00010000>;
|
||||||
|
qcom,sde-ucsc-gc = <0x700 0x00010000>;
|
||||||
|
qcom,sde-ucsc-csc = <0x700 0x00010000>;
|
||||||
|
qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
vcm@1 {
|
||||||
|
cell-index = <1>;
|
||||||
|
qcom,sde-fp16-igc = <0x280 0x00010000>;
|
||||||
|
qcom,sde-fp16-unmult = <0x280 0x00010000>;
|
||||||
|
qcom,sde-fp16-gc = <0x280 0x00010000>;
|
||||||
|
qcom,sde-fp16-csc = <0x280 0x00010000>;
|
||||||
|
qcom,sde-ucsc-igc = <0x1700 0x00010000>;
|
||||||
|
qcom,sde-ucsc-unmult = <0x1700 0x00010000>;
|
||||||
|
qcom,sde-ucsc-gc = <0x1700 0x00010000>;
|
||||||
|
qcom,sde-ucsc-csc = <0x1700 0x00010000>;
|
||||||
|
qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
qcom,sde-sspp-dma-blocks {
|
||||||
|
dgm@0 {
|
||||||
|
cell-index = <0>;
|
||||||
|
qcom,sde-dma-top-off = <0x700>;
|
||||||
|
qcom,sde-fp16-igc = <0x200 0x00010000>;
|
||||||
|
qcom,sde-fp16-unmult = <0x200 0x00010000>;
|
||||||
|
qcom,sde-fp16-gc = <0x200 0x00010000>;
|
||||||
|
qcom,sde-fp16-csc = <0x200 0x00010000>;
|
||||||
|
qcom,sde-ucsc-igc = <0x700 0x00010000>;
|
||||||
|
qcom,sde-ucsc-unmult = <0x700 0x00010000>;
|
||||||
|
qcom,sde-ucsc-gc = <0x700 0x00010000>;
|
||||||
|
qcom,sde-ucsc-csc = <0x700 0x00010000>;
|
||||||
|
qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
dgm@1 {
|
||||||
|
cell-index = <1>;
|
||||||
|
qcom,sde-fp16-igc = <0x200 0x00010000>;
|
||||||
|
qcom,sde-fp16-unmult = <0x200 0x00010000>;
|
||||||
|
qcom,sde-fp16-gc = <0x200 0x00010000>;
|
||||||
|
qcom,sde-fp16-csc = <0x200 0x00010000>;
|
||||||
|
qcom,sde-ucsc-igc = <0x1700 0x00010000>;
|
||||||
|
qcom,sde-ucsc-unmult = <0x1700 0x00010000>;
|
||||||
|
qcom,sde-ucsc-gc = <0x1700 0x00010000>;
|
||||||
|
qcom,sde-ucsc-csc = <0x1700 0x00010000>;
|
||||||
|
qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
qcom,sde-dspp-blocks {
|
||||||
|
qcom,sde-dspp-igc = <0x1260 0x00040000>;
|
||||||
|
qcom,sde-dspp-hsic = <0x800 0x00010007>;
|
||||||
|
qcom,sde-dspp-memcolor = <0x880 0x00010007>;
|
||||||
|
qcom,sde-dspp-hist = <0x800 0x00010007>;
|
||||||
|
qcom,sde-dspp-sixzone = <0x900 0x00020000>;
|
||||||
|
qcom,sde-dspp-vlut = <0xa00 0x00010008>;
|
||||||
|
qcom,sde-dspp-gamut = <0x1000 0x00040003>;
|
||||||
|
qcom,sde-dspp-pcc = <0x1700 0x00040000>;
|
||||||
|
qcom,sde-dspp-gc = <0x17c0 0x00010008>;
|
||||||
|
qcom,sde-dspp-dither = <0x82c 0x00010007>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
17
display/sun-sde-display-cdp-overlay.dts
Normal file
17
display/sun-sde-display-cdp-overlay.dts
Normal file
@@ -0,0 +1,17 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
#include "sun-sde-display-cdp.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "Qualcomm Technologies, Inc. Sun CDP";
|
||||||
|
compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp";
|
||||||
|
qcom,msm-id = <618 0x10000>, <618 0x20000>;
|
||||||
|
qcom,board-id = <1 0>;
|
||||||
|
};
|
||||||
|
|
||||||
7
display/sun-sde-display-cdp.dtsi
Normal file
7
display/sun-sde-display-cdp.dtsi
Normal file
@@ -0,0 +1,7 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "sun-sde-display.dtsi"
|
||||||
|
|
||||||
9
display/sun-sde-display-emulated.dtsi
Normal file
9
display/sun-sde-display-emulated.dtsi
Normal file
@@ -0,0 +1,9 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
&mdss_mdp {
|
||||||
|
qcom,sde-emulated-env;
|
||||||
|
};
|
||||||
|
|
||||||
17
display/sun-sde-display-mtp-overlay.dts
Normal file
17
display/sun-sde-display-mtp-overlay.dts
Normal file
@@ -0,0 +1,17 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
#include "sun-sde-display-mtp.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "Qualcomm Technologies, Inc. Sun MTP";
|
||||||
|
compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp";
|
||||||
|
qcom,msm-id = <618 0x10000>, <618 0x20000>;
|
||||||
|
qcom,board-id = <8 0>;
|
||||||
|
};
|
||||||
|
|
||||||
7
display/sun-sde-display-mtp.dtsi
Normal file
7
display/sun-sde-display-mtp.dtsi
Normal file
@@ -0,0 +1,7 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "sun-sde-display.dtsi"
|
||||||
|
|
||||||
17
display/sun-sde-display-rumi-overlay.dts
Normal file
17
display/sun-sde-display-rumi-overlay.dts
Normal file
@@ -0,0 +1,17 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
#include "sun-sde-display-rumi.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "Qualcomm Technologies, Inc. Sun RUMI";
|
||||||
|
compatible = "qcom,sun-rumi", "qcom,sun", "qcom,rumi";
|
||||||
|
qcom,msm-id = <618 0x10000>;
|
||||||
|
qcom,board-id = <15 0>;
|
||||||
|
};
|
||||||
|
|
||||||
8
display/sun-sde-display-rumi.dtsi
Normal file
8
display/sun-sde-display-rumi.dtsi
Normal file
@@ -0,0 +1,8 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "sun-sde-display.dtsi"
|
||||||
|
#include "sun-sde-display-emulated.dtsi"
|
||||||
|
|
||||||
26
display/sun-sde-display.dtsi
Normal file
26
display/sun-sde-display.dtsi
Normal file
@@ -0,0 +1,26 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "sun-sde.dtsi"
|
||||||
|
#include <dt-bindings/clock/qcom,dispcc-sun.h>
|
||||||
|
|
||||||
|
&soc {
|
||||||
|
sde_wb1: qcom,wb-display@1 {
|
||||||
|
compatible = "qcom,wb-display";
|
||||||
|
cell-index = <0>;
|
||||||
|
label = "wb_display1";
|
||||||
|
};
|
||||||
|
|
||||||
|
sde_wb2: qcom,wb-display@2 {
|
||||||
|
compatible = "qcom,wb-display";
|
||||||
|
cell-index = <1>;
|
||||||
|
label = "wb_display2";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&mdss_mdp {
|
||||||
|
connectors = <&smmu_sde_unsec &sde_wb1 &sde_wb2>;
|
||||||
|
};
|
||||||
|
|
||||||
14
display/sun-sde.dts
Normal file
14
display/sun-sde.dts
Normal file
@@ -0,0 +1,14 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
#include "sun-sde.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
qcom,msm-id = <618 0x10000>;
|
||||||
|
qcom,board-id = <15 0>;
|
||||||
|
};
|
||||||
88
display/sun-sde.dtsi
Normal file
88
display/sun-sde.dtsi
Normal file
@@ -0,0 +1,88 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||||
|
#include <dt-bindings/clock/qcom,dispcc-sun.h>
|
||||||
|
#include <dt-bindings/clock/qcom,gcc-sun.h>
|
||||||
|
#include <dt-bindings/interconnect/qcom,sun.h>
|
||||||
|
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||||
|
#include <dt-bindings/clock/qcom,tcsrcc-sun.h>
|
||||||
|
#include "sun-sde-common.dtsi"
|
||||||
|
|
||||||
|
&soc {
|
||||||
|
smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
|
||||||
|
compatible = "qcom,smmu_sde_unsec";
|
||||||
|
iommus = <&apps_smmu 0x800 0x2>;
|
||||||
|
qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
|
||||||
|
qcom,iommu-faults = "non-fatal";
|
||||||
|
qcom,iommu-earlymap; /* for cont-splash */
|
||||||
|
dma-coherent;
|
||||||
|
};
|
||||||
|
|
||||||
|
smmu_sde_sec: qcom,smmu_sde_sec_cb {
|
||||||
|
compatible = "qcom,smmu_sde_sec";
|
||||||
|
iommus = <&apps_smmu 0x801 0x0>;
|
||||||
|
qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
|
||||||
|
qcom,iommu-faults = "non-fatal";
|
||||||
|
qcom,iommu-vmid = <0xa>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&mdss_mdp {
|
||||||
|
clocks =
|
||||||
|
<&gcc GCC_DISP_HF_AXI_CLK>,
|
||||||
|
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||||
|
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||||
|
<&dispcc DISP_CC_MDSS_MDP_CLK_SRC>,
|
||||||
|
<&dispcc DISP_CC_MDSS_VSYNC_CLK>,
|
||||||
|
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>;
|
||||||
|
clock-names = "gcc_bus",
|
||||||
|
"iface_clk", "branch_clk", "core_clk", "vsync_clk",
|
||||||
|
"lut_clk";
|
||||||
|
clock-rate = <0 0 575000000 575000000 19200000 575000000>;
|
||||||
|
clock-max-rate = <0 0 575000000 575000000 19200000 575000000>;
|
||||||
|
|
||||||
|
vdd-supply = <&disp_cc_mdss_core_gdsc>;
|
||||||
|
mmcx-supply = <&VDD_MMCX_LEVEL>;
|
||||||
|
|
||||||
|
qcom,sde-vm-exclude-reg-names = "ipcc_reg";
|
||||||
|
|
||||||
|
/* data and reg bus scale settings */
|
||||||
|
interconnects = <&mmss_noc MASTER_MDP &gem_noc SLAVE_LLCC>,
|
||||||
|
<&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
|
||||||
|
<&gem_noc MASTER_APPSS_PROC
|
||||||
|
&config_noc SLAVE_DISPLAY_CFG>;
|
||||||
|
interconnect-names = "qcom,sde-data-bus0",
|
||||||
|
"qcom,sde-ebi-bus", "qcom,sde-reg-bus";
|
||||||
|
|
||||||
|
qcom,sde-ib-bw-vote = <2500000 0 800000>;
|
||||||
|
qcom,sde-dspp-ltm-version = <0x00010002>;
|
||||||
|
/* offsets are based off dspp 0, 1, 2, and 3 */
|
||||||
|
qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300 0x12300>;
|
||||||
|
|
||||||
|
qcom,platform-supply-entries {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
qcom,platform-supply-entry@0 {
|
||||||
|
reg = <0>;
|
||||||
|
qcom,supply-name = "mmcx";
|
||||||
|
qcom,supply-min-voltage = <0>;
|
||||||
|
qcom,supply-max-voltage = <0>;
|
||||||
|
qcom,supply-enable-load = <0>;
|
||||||
|
qcom,supply-disable-load = <0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
qcom,platform-supply-entry@1 {
|
||||||
|
reg = <1>;
|
||||||
|
qcom,supply-name = "vdd";
|
||||||
|
qcom,supply-min-voltage = <0>;
|
||||||
|
qcom,supply-max-voltage = <0>;
|
||||||
|
qcom,supply-enable-load = <0>;
|
||||||
|
qcom,supply-disable-load = <0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
Reference in New Issue
Block a user