313d6ad696
Add device tree files required for DPU driver on sun target. Move bindings for all mdp, dsi, panels, hdcp to opensource project. Change-Id: I1c6575313e33c5727f48ce94fe8b51cd9c62995d Signed-off-by: Varsha Suresh <quic_varssure@quicinc.com> Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
89 lines
2.5 KiB
Plaintext
89 lines
2.5 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
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#include <dt-bindings/clock/qcom,dispcc-sun.h>
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#include <dt-bindings/clock/qcom,gcc-sun.h>
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#include <dt-bindings/interconnect/qcom,sun.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,tcsrcc-sun.h>
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#include "sun-sde-common.dtsi"
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&soc {
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smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
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compatible = "qcom,smmu_sde_unsec";
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iommus = <&apps_smmu 0x800 0x2>;
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qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-earlymap; /* for cont-splash */
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dma-coherent;
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};
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smmu_sde_sec: qcom,smmu_sde_sec_cb {
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compatible = "qcom,smmu_sde_sec";
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iommus = <&apps_smmu 0x801 0x0>;
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qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-vmid = <0xa>;
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};
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};
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&mdss_mdp {
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clocks =
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<&gcc GCC_DISP_HF_AXI_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_VSYNC_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>;
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clock-names = "gcc_bus",
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"iface_clk", "branch_clk", "core_clk", "vsync_clk",
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"lut_clk";
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clock-rate = <0 0 575000000 575000000 19200000 575000000>;
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clock-max-rate = <0 0 575000000 575000000 19200000 575000000>;
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vdd-supply = <&disp_cc_mdss_core_gdsc>;
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mmcx-supply = <&VDD_MMCX_LEVEL>;
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qcom,sde-vm-exclude-reg-names = "ipcc_reg";
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/* data and reg bus scale settings */
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interconnects = <&mmss_noc MASTER_MDP &gem_noc SLAVE_LLCC>,
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<&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
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<&gem_noc MASTER_APPSS_PROC
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&config_noc SLAVE_DISPLAY_CFG>;
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interconnect-names = "qcom,sde-data-bus0",
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"qcom,sde-ebi-bus", "qcom,sde-reg-bus";
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qcom,sde-ib-bw-vote = <2500000 0 800000>;
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qcom,sde-dspp-ltm-version = <0x00010002>;
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/* offsets are based off dspp 0, 1, 2, and 3 */
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qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300 0x12300>;
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qcom,platform-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,platform-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "mmcx";
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qcom,supply-min-voltage = <0>;
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qcom,supply-max-voltage = <0>;
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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};
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qcom,platform-supply-entry@1 {
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reg = <1>;
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qcom,supply-name = "vdd";
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qcom,supply-min-voltage = <0>;
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qcom,supply-max-voltage = <0>;
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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};
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};
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};
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