Merge 4625e901da on remote branch
Change-Id: Ia1a9c1e5252450da76cad8e306d648ecb6539816
This commit is contained in:
Linux Build Service Account
@@ -9,14 +9,15 @@ title: Last Level Cache Controller
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maintainers:
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- Rishabh Bhatnagar <rishabhb@codeaurora.org>
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- Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
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- Avinash Philip <quic_avinashp@quicinc.com>
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description: |
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LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
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that can be shared by multiple clients. Clients here are different cores in the
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SoC, the idea is to minimize the local caches at the clients and migrate to
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common pool of memory. Cache memory is divided into partitions called slices
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which are assigned to clients. Clients can query the slice details, activate
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and deactivate them.
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LLCC (Last Level Cache Controller) provides last level of cache memory in
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SoC, that can be shared by multiple clients. Clients here are different cores
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in the SoC, the idea is to minimize the local caches at the clients and
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migrate to common pool of memory. Cache memory is divided into partitions
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called slices which are assigned to clients. Clients can query the slice
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details, activate and deactivate them.
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properties:
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compatible:
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@@ -49,11 +50,43 @@ properties:
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maxItems: 1
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child-node:
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description: Container of llcc_perfmon node
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description: |
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- Container of llcc_perfmon node
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- Container of scid heuristics
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type: object
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properties:
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compatible:
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const: qcom,llcc-perfmon
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compatible:
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items:
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- const: qcom,llcc-perfmon
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- const: qcom,scid-heuristics
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qcom,heuristics_scid:
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$ref: '/schemas/types.yaml#/definitions/uint32'
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description: |
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SCID number of HEURISTICS SID
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freq,threshold_idx:
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$ref: '/schemas/types.yaml#/definitions/uint32-array'
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description: |
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CPU DVFS frequency threshold index
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minItems: 1
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maxItems: 2
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freq,threshold_residency:
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$ref: '/schemas/types.yaml#/definitions/uint32-array'
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description: |
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CPU DVFS frequency threshold Residency value in micro seconds
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minItems: 1
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maxItems: 2
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qcom,scid_heuristics_enabled:
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description: |
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On enabling this flag, Heristics driver will communicate to qcom
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control software to enable the Heristics based SCID functionality.
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type: boolean
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required:
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- compatible
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additionalProperties: false
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required:
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- compatible
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- reg
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@@ -78,7 +111,7 @@ allOf:
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- description: LLCC3 base register region
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- description: LLCC broadcast base register region
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reg-names:
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items:
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items:
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- const: llcc0_base
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- const: llcc1_base
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- const: llcc2_base
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@@ -89,8 +122,6 @@ additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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@@ -107,5 +138,13 @@ examples:
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llcc_perfmon {
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compatible = "qcom,llcc-perfmon";
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}
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scid_heuristics {
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compatible = "qcom,scid-heuristics";
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qcom,heuristics_scid = <32>;
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freq,threshold_idx = <11>, <10>;
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freq,threshold_residency = <5000>, <5000>;
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qcom,scid_heuristics_enabled;
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};
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};
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};
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@@ -1,10 +1,13 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/soc/qcom/qcom,secure-buffer.yaml#"
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$id: "http://devicetree.org/schemas/virtio/qcom,virtio-mem.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Qualcomm Technologies, Inc. Virtio-Mem bindings
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title: Qualcomm Technologies, Inc. Virtio-Mem
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maintainers:
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- Patrick Daly <quic_pdaly@quicinc.com>
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description: |
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QTI virtio mem driver supports Guest initiated memory hotplug operations
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@@ -16,6 +19,7 @@ properties:
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- const: qcom,virtio-mem
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qcom,block-size:
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$ref: '/schemas/types.yaml#/definitions/uint32'
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description:
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Minimum transfer size in bytes. Should be multiple of PAGE_SIZE.
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@@ -31,6 +35,11 @@ properties:
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is allowed to choose when adding hotpluggable memory for this
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device.
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qcom,initial-movable-zone-size:
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$ref: '/schemas/types.yaml#/definitions/uint32'
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description: |
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Initial size of movable zone.
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qcom,memory-encryption:
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type: boolean
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description: |
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@@ -39,14 +48,17 @@ properties:
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required:
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- compatible
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- qcom,size
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- qcom,max-size
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- qcom,ipa-range
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- qcom,block-size
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example:
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virtio_mem_device@0x60000000 {
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compatible = "qcom,virtio-mem";
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qcom,block_size = <0x400000>;
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qcom,size = <0x0 0x10000000>;
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qcom,ipa-range = <0x0 0x0 0xf 0xffffffff>;
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};
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additionalProperties: false
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examples:
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- |+
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virtio_mem_device@0x60000000 {
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compatible = "qcom,virtio-mem";
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qcom,block-size = <0x400000>;
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qcom,max-size = <0x0 0x10000000>;
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qcom,ipa-range = <0x0 0x0 0xf 0xffffffff>;
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};
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@@ -343,7 +343,7 @@
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x2000000>;
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size = <0x0 0x1000000>;
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linux,cma-default;
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};
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};
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@@ -156,19 +156,20 @@
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&pm7250b_adc_tm {
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interrupts = <0x8 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
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io-channels = <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>,
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<&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>;
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/* Channel nodes */
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pm7250b_usb_conn_therm {
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reg = <ADC5_AMUX_THM3_100K_PU>;
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reg = <0>;
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io-channels = <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>;
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qcom,ratiometric;
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qcom,hw-settle-time = <200>;
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qcom,hw-settle-time-us = <200>;
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};
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pm7250b_smb_skin_therm {
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reg = <ADC5_AMUX_THM1_100K_PU>;
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reg = <1>;
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io-channels = <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>;
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qcom,ratiometric;
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qcom,hw-settle-time = <200>;
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qcom,hw-settle-time-us = <200>;
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};
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};
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@@ -293,7 +294,7 @@
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sys-therm-7 {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM3_100K_PU>;
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thermal-sensors = <&pm7250b_adc_tm 0>;
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trips {
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active-config0 {
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temperature = <125000>;
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@@ -312,7 +313,7 @@
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sys-therm-6 {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM1_100K_PU>;
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thermal-sensors = <&pm7250b_adc_tm 1>;
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trips {
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active-config0 {
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temperature = <125000>;
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@@ -100,19 +100,19 @@
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};
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&pmk8350_adc_tm {
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io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>,
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<&pmk8350_vadc PM6450_ADC7_AMUX1_GPIO2_100K_PU>;
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/* Channel nodes */
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pmk8350_xo_therm {
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reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
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reg = <0>;
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io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>;
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qcom,ratiometric;
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qcom,hw-settle-time = <200>;
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qcom,hw-settle-time-us = <200>;
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};
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pm6450_quiet_therm {
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reg = <PM6450_ADC7_AMUX1_GPIO2_100K_PU>;
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reg = <1>;
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io-channels = <&pmk8350_vadc PM6450_ADC7_AMUX1_GPIO2_100K_PU>;
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qcom,ratiometric;
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qcom,hw-settle-time = <200>;
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qcom,hw-settle-time-us = <200>;
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};
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};
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@@ -233,34 +233,33 @@
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};
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&pm6150l_adc_tm {
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io-channels = <&pm6150l_vadc ADC5_AMUX_THM1_100K_PU>,
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<&pm6150l_vadc ADC5_AMUX_THM3_100K_PU>,
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<&pm6150l_vadc ADC5_GPIO1_100K_PU>,
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<&pm6150l_vadc ADC5_GPIO3_100K_PU>;
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/* Channel nodes */
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pa_therm2 {
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reg = <ADC5_AMUX_THM1_100K_PU>;
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reg = <0>;
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io-channels = <&pm6150l_vadc ADC5_AMUX_THM1_100K_PU>;
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qcom,ratiometric;
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qcom,hw-settle-time = <200>;
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qcom,hw-settle-time-us = <200>;
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};
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pa_therm1 {
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reg = <ADC5_AMUX_THM3_100K_PU>;
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reg = <1>;
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io-channels = <&pm6150l_vadc ADC5_AMUX_THM3_100K_PU>;
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qcom,ratiometric;
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qcom,hw-settle-time = <200>;
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qcom,hw-settle-time-us = <200>;
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};
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ufs_therm {
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reg = <ADC5_GPIO1_100K_PU>;
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reg = <2>;
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io-channels = <&pm6150l_vadc ADC5_GPIO1_100K_PU>;
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qcom,ratiometric;
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qcom,hw-settle-time = <200>;
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qcom,hw-settle-time-us = <200>;
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};
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wide_rfc_therm {
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reg = <ADC5_GPIO3_100K_PU>;
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reg = <3>;
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io-channels = <&pm6150l_vadc ADC5_GPIO3_100K_PU>;
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qcom,ratiometric;
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qcom,hw-settle-time = <200>;
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qcom,hw-settle-time-us = <200>;
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};
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};
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@@ -283,7 +282,7 @@
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xo-therm {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM1_100K_PU>;
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thermal-sensors = <&pmk8350_adc_tm 0>;
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trips {
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active-config0 {
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temperature = <125000>;
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@@ -302,7 +301,7 @@
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sys-therm-1 {
|
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polling-delay-passive = <0>;
|
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polling-delay = <0>;
|
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thermal-sensors = <&pm6150l_adc_tm ADC5_GPIO1_100K_PU>;
|
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thermal-sensors = <&pm6150l_adc_tm 2>;
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trips {
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active-config0 {
|
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temperature = <125000>;
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@@ -321,7 +320,7 @@
|
||||
sys-therm-2 {
|
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polling-delay-passive = <0>;
|
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polling-delay = <0>;
|
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thermal-sensors = <&pm6150l_adc_tm ADC5_GPIO3_100K_PU>;
|
||||
thermal-sensors = <&pm6150l_adc_tm 3>;
|
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trips {
|
||||
active-config0 {
|
||||
temperature = <125000>;
|
||||
@@ -340,7 +339,7 @@
|
||||
sys-therm-3 {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&pmk8350_adc_tm PM6450_ADC7_AMUX1_GPIO2_100K_PU>;
|
||||
thermal-sensors = <&pmk8350_adc_tm 1>;
|
||||
trips {
|
||||
active-config0 {
|
||||
temperature = <125000>;
|
||||
@@ -359,7 +358,7 @@
|
||||
sys-therm-4 {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&pm6150l_adc_tm ADC5_AMUX_THM1_100K_PU>;
|
||||
thermal-sensors = <&pm6150l_adc_tm 0>;
|
||||
trips {
|
||||
active-config0 {
|
||||
temperature = <125000>;
|
||||
@@ -378,7 +377,7 @@
|
||||
sys-therm-5 {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&pm6150l_adc_tm ADC5_AMUX_THM3_100K_PU>;
|
||||
thermal-sensors = <&pm6150l_adc_tm 1>;
|
||||
trips {
|
||||
active-config0 {
|
||||
temperature = <125000>;
|
||||
|
||||
@@ -722,25 +722,12 @@
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
cpu0_emerg: cpu0-emerg-cfg {
|
||||
temperature = <110000>;
|
||||
hysteresis = <10000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
reset-mon-cfg {
|
||||
temperature = <115000>;
|
||||
hysteresis = <0>;
|
||||
type = "hot";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
cpu00_cdev {
|
||||
trip = <&cpu0_emerg>;
|
||||
cooling-device = <&cpu0_pause 1 1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu-0-1 {
|
||||
@@ -1125,7 +1112,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
zeroc-0-step {
|
||||
zeroc-0 {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&tsens0 128>;
|
||||
@@ -1144,7 +1131,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
zeroc-1-step {
|
||||
zeroc-1 {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&tsens1 128>;
|
||||
|
||||
@@ -84,9 +84,9 @@
|
||||
};
|
||||
|
||||
pm6150l_adc_tm: adc_tm@3500 {
|
||||
compatible = "qcom,spmi-adc-tm5";
|
||||
reg = <0x3500>;
|
||||
interrupts = <0x4 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "threshold";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
|
||||
@@ -158,9 +158,9 @@
|
||||
};
|
||||
|
||||
pm7250b_adc_tm: adc_tm@3500 {
|
||||
compatible = "qcom,spmi-adc-tm5";
|
||||
reg = <0x3500>;
|
||||
interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "threshold";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
|
||||
@@ -116,9 +116,9 @@
|
||||
};
|
||||
|
||||
pmi632_adc_tm: adc_tm@3500 {
|
||||
compatible = "qcom,spmi-adc-tm5";
|
||||
reg = <0x3500>;
|
||||
interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "threshold";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
|
||||
@@ -183,9 +183,9 @@
|
||||
};
|
||||
|
||||
pmk8350_adc_tm: adc_tm@3400 {
|
||||
compatible = "qcom,spmi-adc-tm5-gen2";
|
||||
reg = <0x3400>;
|
||||
interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "threshold";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
|
||||
@@ -125,19 +125,20 @@
|
||||
|
||||
&pm7250b_adc_tm {
|
||||
interrupts = <0x8 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
|
||||
io-channels = <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>,
|
||||
<&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>;
|
||||
|
||||
/* Channel nodes */
|
||||
pm7250b_usb_conn_therm {
|
||||
reg = <ADC5_AMUX_THM3_100K_PU>;
|
||||
reg = <0>;
|
||||
io-channels = <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>;
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time = <200>;
|
||||
qcom,hw-settle-time-us = <200>;
|
||||
};
|
||||
|
||||
pm7250b_charger_skin_therm {
|
||||
reg = <ADC5_AMUX_THM1_100K_PU>;
|
||||
reg = <1>;
|
||||
io-channels = <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>;
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time = <200>;
|
||||
qcom,hw-settle-time-us = <200>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -252,7 +253,7 @@
|
||||
sys-therm-9 {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM3_100K_PU>;
|
||||
thermal-sensors = <&pm7250b_adc_tm 0>;
|
||||
trips {
|
||||
active-config0 {
|
||||
temperature = <125000>;
|
||||
@@ -271,7 +272,7 @@
|
||||
sys-therm-7 {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM1_100K_PU>;
|
||||
thermal-sensors = <&pm7250b_adc_tm 1>;
|
||||
trips {
|
||||
active-config0 {
|
||||
temperature = <125000>;
|
||||
|
||||
@@ -143,26 +143,26 @@
|
||||
};
|
||||
|
||||
&pmi632_adc_tm {
|
||||
io-channels = <&pmi632_vadc ADC5_GPIO1_100K_PU>,
|
||||
<&pmi632_vadc ADC5_GPIO2_100K_PU>,
|
||||
<&pmi632_vadc ADC5_GPIO3_100K_PU>;
|
||||
|
||||
/*Channel nodes */
|
||||
pmi632_usb_conn_therm {
|
||||
reg = <ADC5_GPIO1_100K_PU>;
|
||||
reg = <0>;
|
||||
io-channels = <&pmi632_vadc ADC5_GPIO1_100K_PU>;
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time = <200>;
|
||||
qcom,hw-settle-time-us = <200>;
|
||||
};
|
||||
|
||||
pmi632_charger_skin_temp {
|
||||
reg = <ADC5_GPIO2_100K_PU>;
|
||||
reg = <1>;
|
||||
io-channels = <&pmi632_vadc ADC5_GPIO2_100K_PU>;
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time = <200>;
|
||||
qcom,hw-settle-time-us = <200>;
|
||||
};
|
||||
|
||||
pmi632_smb_skin_therm {
|
||||
reg = <ADC5_GPIO3_100K_PU>;
|
||||
reg = <2>;
|
||||
io-channels = <&pmi632_vadc ADC5_GPIO3_100K_PU>;
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time = <200>;
|
||||
qcom,hw-settle-time-us = <200>;
|
||||
};
|
||||
|
||||
};
|
||||
@@ -262,7 +262,7 @@
|
||||
sys-therm-9 {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&pmi632_adc_tm ADC5_GPIO1_100K_PU>;
|
||||
thermal-sensors = <&pmi632_adc_tm 0>;
|
||||
trips {
|
||||
active-config0 {
|
||||
temperature = <125000>;
|
||||
@@ -281,7 +281,7 @@
|
||||
sys-therm-7 {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&pmi632_adc_tm ADC5_GPIO2_100K_PU>;
|
||||
thermal-sensors = <&pmi632_adc_tm 1>;
|
||||
trips {
|
||||
active-config0 {
|
||||
temperature = <125000>;
|
||||
@@ -300,7 +300,7 @@
|
||||
sys-therm-8 {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&pmi632_adc_tm ADC5_GPIO3_100K_PU>;
|
||||
thermal-sensors = <&pmi632_adc_tm 2>;
|
||||
trips {
|
||||
active-config0 {
|
||||
temperature = <125000>;
|
||||
|
||||
@@ -155,47 +155,47 @@
|
||||
};
|
||||
|
||||
&pmk8350_adc_tm {
|
||||
io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>,
|
||||
<&pmk8350_vadc PM6450_ADC7_AMUX1_GPIO2_100K_PU>,
|
||||
<&pmk8350_vadc PMK8350_ADC7_AMUX_THM2_100K_PU>,
|
||||
<&pmk8350_vadc PM6450_ADC7_AMUX4_GPIO5_100K_PU>,
|
||||
<&pmk8350_vadc PM6450_ADC7_AMUX3_GPIO4_100K_PU>,
|
||||
<&pmk8350_vadc PMK8350_ADC7_AMUX_THM3_100K_PU>;
|
||||
|
||||
/* Channel nodes */
|
||||
pmk8350_xo_therm {
|
||||
reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
|
||||
reg = <0>;
|
||||
io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>;
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time = <200>;
|
||||
qcom,hw-settle-time-us = <200>;
|
||||
};
|
||||
|
||||
pm6450_quiet_therm {
|
||||
reg = <PM6450_ADC7_AMUX1_GPIO2_100K_PU>;
|
||||
reg = <1>;
|
||||
io-channels = <&pmk8350_vadc PM6450_ADC7_AMUX1_GPIO2_100K_PU>;
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time = <200>;
|
||||
qcom,hw-settle-time-us = <200>;
|
||||
};
|
||||
|
||||
pmk8350_wide_rfc_therm {
|
||||
reg = <PMK8350_ADC7_AMUX_THM2_100K_PU>;
|
||||
reg = <2>;
|
||||
io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM2_100K_PU>;
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time = <200>;
|
||||
qcom,hw-settle-time-us = <200>;
|
||||
};
|
||||
|
||||
pm6450_rear_cam_flash_therm {
|
||||
reg = <PM6450_ADC7_AMUX4_GPIO5_100K_PU>;
|
||||
reg = <3>;
|
||||
io-channels = <&pmk8350_vadc PM6450_ADC7_AMUX4_GPIO5_100K_PU>;
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time = <200>;
|
||||
qcom,hw-settle-time-us = <200>;
|
||||
};
|
||||
|
||||
pm6450_pa2_therm {
|
||||
reg = <PM6450_ADC7_AMUX3_GPIO4_100K_PU>;
|
||||
reg = <4>;
|
||||
io-channels = <&pmk8350_vadc PM6450_ADC7_AMUX3_GPIO4_100K_PU>;
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time = <200>;
|
||||
qcom,hw-settle-time-us = <200>;
|
||||
};
|
||||
|
||||
pmk8350_pa1_therm {
|
||||
reg = <PMK8350_ADC7_AMUX_THM3_100K_PU>;
|
||||
reg = <5>;
|
||||
io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM3_100K_PU>;
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time = <200>;
|
||||
qcom,hw-settle-time-us = <200>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -284,7 +284,7 @@
|
||||
sys-therm-6 {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM1_100K_PU>;
|
||||
thermal-sensors = <&pmk8350_adc_tm 0>;
|
||||
trips {
|
||||
active-config0 {
|
||||
temperature = <125000>;
|
||||
@@ -303,7 +303,7 @@
|
||||
sys-therm-4 {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM2_100K_PU>;
|
||||
thermal-sensors = <&pmk8350_adc_tm 2>;
|
||||
trips {
|
||||
active-config0 {
|
||||
temperature = <125000>;
|
||||
@@ -322,7 +322,7 @@
|
||||
sys-therm-1 {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&pmk8350_adc_tm PM6450_ADC7_AMUX1_GPIO2_100K_PU>;
|
||||
thermal-sensors = <&pmk8350_adc_tm 1>;
|
||||
trips {
|
||||
active-config0 {
|
||||
temperature = <125000>;
|
||||
@@ -341,7 +341,7 @@
|
||||
sys-therm-3 {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&pmk8350_adc_tm PM6450_ADC7_AMUX4_GPIO5_100K_PU>;
|
||||
thermal-sensors = <&pmk8350_adc_tm 3>;
|
||||
trips {
|
||||
active-config0 {
|
||||
temperature = <125000>;
|
||||
@@ -360,7 +360,7 @@
|
||||
sys-therm-11 {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&pmk8350_adc_tm PM6450_ADC7_AMUX3_GPIO4_100K_PU>;
|
||||
thermal-sensors = <&pmk8350_adc_tm 4>;
|
||||
trips {
|
||||
active-config0 {
|
||||
temperature = <125000>;
|
||||
@@ -379,7 +379,7 @@
|
||||
sys-therm-5 {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM3_100K_PU>;
|
||||
thermal-sensors = <&pmk8350_adc_tm 5>;
|
||||
trips {
|
||||
active-config0 {
|
||||
temperature = <125000>;
|
||||
|
||||
@@ -707,17 +707,19 @@
|
||||
qcom,vmid = <45>;
|
||||
};
|
||||
|
||||
qcom,mem-buf-msgq {
|
||||
mem_buf_msgq: qcom,mem-buf-msgq {
|
||||
compatible = "qcom,mem-buf-msgq";
|
||||
qcom,msgq-names = "trusted_vm";
|
||||
};
|
||||
|
||||
virtio_mem_device {
|
||||
compatible = "qcom,virtio-mem";
|
||||
depends-on-supply = <&mem_buf_msgq>;
|
||||
/* Must be memory_block_size_bytes() aligned */
|
||||
qcom,max-size = <0x0 0x10000000>;
|
||||
qcom,max-size = <0x0 0x18000000>;
|
||||
qcom,ipa-range = <0x0 0x0 0xf 0xffffffff>;
|
||||
qcom,block-size = <0x400000>;
|
||||
qcom,initial-movable-zone-size = <0x2000000>;
|
||||
};
|
||||
|
||||
qcom,gunyah-panic-notifier {
|
||||
|
||||
@@ -923,6 +923,15 @@
|
||||
clocks = <&aoss_qmp QDSS_CLK>;
|
||||
clock-names = "qdss_clk";
|
||||
};
|
||||
|
||||
scid_heuristics {
|
||||
compatible = "qcom,scid-heuristics";
|
||||
qcom,heuristics_scid = <32>;
|
||||
/* Need to update different value for V2 device */
|
||||
freq,threshold_idx = <11>, <10>;
|
||||
freq,threshold_residency = <5000>, <5000>;
|
||||
qcom,scid_heuristics_enabled;
|
||||
};
|
||||
};
|
||||
|
||||
gic-interrupt-router {
|
||||
|
||||
@@ -3,6 +3,9 @@
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/qcom,gcc-tuna.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
|
||||
&arch_timer {
|
||||
clock-frequency = <500000>;
|
||||
};
|
||||
@@ -31,6 +34,83 @@
|
||||
};
|
||||
};
|
||||
|
||||
&ufsphy_mem {
|
||||
compatible = "qcom,ufs-phy-qrbtc-sdm845";
|
||||
|
||||
/* VDDA_UFS_CORE */
|
||||
vdda-phy-supply = <&L1F>;
|
||||
vdda-phy-max-microamp = <214160>;
|
||||
/*
|
||||
* Platforms supporting Gear 5 && Rate B require a different
|
||||
* voltage supply. Check the Power Grid document.
|
||||
*/
|
||||
vdda-phy-min-microvolt = <912000>;
|
||||
|
||||
/* VDDA_UFS_0_1P2 */
|
||||
vdda-pll-supply = <&L4B>;
|
||||
vdda-pll-max-microamp = <18340>;
|
||||
|
||||
/* Phy GDSC for VDD_MX, always on */
|
||||
vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>;
|
||||
|
||||
/* Qref power supply, Refer Qref diagram */
|
||||
vdda-qref-supply = <&L2B>;
|
||||
vdda-qref-max-microamp = <64500>;
|
||||
|
||||
/* Detect whether RH132 card based sequences to be used */
|
||||
qcom,soc_emulation_type_addr = <0x1fc8004>;
|
||||
qcom,soc_emulation_type_bits = <32>;
|
||||
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&ufshc_mem {
|
||||
limit-tx-hs-gear = <1>;
|
||||
limit-rx-hs-gear = <1>;
|
||||
limit-rate = <2>; /* HS Rate-B */
|
||||
rpm-level = <0>;
|
||||
spm-level = <0>;
|
||||
|
||||
vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
|
||||
|
||||
vcc-supply = <&L12B>;
|
||||
vcc-max-microamp = <1200000>;
|
||||
|
||||
vccq-supply = <&L3F>;
|
||||
vccq-max-microamp = <1200000>;
|
||||
|
||||
qcom,vddp-ref-clk-supply = <&L5B>;
|
||||
qcom,vddp-ref-clk-max-microamp = <100>;
|
||||
|
||||
qcom,vccq-parent-supply = <&S2B>;
|
||||
qcom,vccq-parent-max-microamp = <210000>;
|
||||
|
||||
clock-names =
|
||||
"core_clk",
|
||||
"bus_aggr_clk",
|
||||
"iface_clk",
|
||||
"core_clk_unipro",
|
||||
"core_clk_ice",
|
||||
"ref_clk",
|
||||
"tx_lane0_sync_clk",
|
||||
"rx_lane0_sync_clk",
|
||||
"rx_lane1_sync_clk";
|
||||
clocks =
|
||||
<&gcc GCC_UFS_PHY_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
|
||||
<&gcc GCC_UFS_PHY_AHB_CLK>,
|
||||
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
|
||||
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
|
||||
<&rpmhcc RPMH_CXO_PAD_CLK>,
|
||||
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
|
||||
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
|
||||
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
|
||||
|
||||
qcom,disable-lpm;
|
||||
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
dwc3@a600000 {
|
||||
usb-phy = <&usb_emuphy>, <&usb_nop_phy>;
|
||||
|
||||
260
qcom/tuna.dtsi
260
qcom/tuna.dtsi
@@ -12,9 +12,12 @@
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,tcsrcc-sun.h>
|
||||
#include <dt-bindings/clock/qcom,videocc-tuna.h>
|
||||
#include <dt-bindings/interconnect/qcom,tuna.h>
|
||||
#include <dt-bindings/interconnect/qcom,icc.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/soc/qcom,ipcc.h>
|
||||
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Tuna";
|
||||
@@ -45,6 +48,7 @@
|
||||
|
||||
aliases {
|
||||
serial0 = &qupv3_se7_2uart;
|
||||
ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
|
||||
};
|
||||
|
||||
cpus {
|
||||
@@ -343,6 +347,10 @@
|
||||
<CONTROL_TCS 0>,
|
||||
<FAST_PATH_TCS 1>;
|
||||
};
|
||||
|
||||
apps_bcm_voter: bcm_voter {
|
||||
compatible = "qcom,bcm-voter";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -751,15 +759,40 @@
|
||||
};
|
||||
|
||||
cambistmclkcc: clock-controller@1760000 {
|
||||
compatible = "qcom,dummycc";
|
||||
clock-output-names = "cambistmclkcc_clocks";
|
||||
compatible = "qcom,tuna-cambistmclkcc", "syscon";
|
||||
reg = <0x1760000 0x6000>;
|
||||
reg-name = "cc_base";
|
||||
vdd_mx-supply = <&VDD_MX_LEVEL>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&sleep_clk>,
|
||||
<&gcc GCC_CAMERA_AHB_CLK>;
|
||||
clock-names = "bi_tcxo",
|
||||
"sleep_clk",
|
||||
"iface";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
|
||||
cam_crm: syscon@adcd600 {
|
||||
compatible = "syscon";
|
||||
reg = <0xadcd600 0x2000>;
|
||||
};
|
||||
|
||||
camcc: clock-controller@ade0000 {
|
||||
compatible = "qcom,dummycc";
|
||||
clock-output-names = "camcc_clocks";
|
||||
compatible = "qcom,tuna-camcc", "syscon";
|
||||
reg = <0xade0000 0x20000>;
|
||||
reg-name = "cc_base";
|
||||
vdd_mm-supply = <&VDD_MM_LEVEL>;
|
||||
vdd_mx-supply = <&VDD_MX_LEVEL>;
|
||||
vdd_mxc-supply = <&VDD_MXC_LEVEL>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&sleep_clk>,
|
||||
<&gcc GCC_CAMERA_AHB_CLK>;
|
||||
clock-names = "bi_tcxo",
|
||||
"sleep_clk",
|
||||
"iface";
|
||||
qcom,cam_crm-crmc = <&cam_crm>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@@ -860,37 +893,244 @@
|
||||
reg = <0x1fc0000 0x30000>;
|
||||
};
|
||||
|
||||
clk_virt: interconnect@0 {
|
||||
compatible = "qcom,tuna-clk_virt";
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
mc_virt: interconnect@1 {
|
||||
compatible = "qcom,tuna-mc_virt";
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
config_noc: interconnect@1600000 {
|
||||
compatible = "qcom,tuna-cnoc_cfg";
|
||||
reg = <0x1600000 0x9200>;
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
qcom,skip-qos;
|
||||
};
|
||||
|
||||
cnoc_main: interconnect@1500000 {
|
||||
compatible = "qcom,tuna-cnoc_main";
|
||||
reg = <0x1500000 0x16080>;
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
qcom,skip-qos;
|
||||
};
|
||||
|
||||
system_noc: interconnect@1680000 {
|
||||
compatible = "qcom,tuna-system_noc";
|
||||
reg = <0x1680000 0x1d080>;
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
qcom,skip-qos;
|
||||
};
|
||||
|
||||
pcie_noc: interconnect@16c0000 {
|
||||
compatible = "qcom,tuna-pcie_anoc";
|
||||
reg = <0x16c0000 0x11400>;
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
qcom,skip-qos;
|
||||
};
|
||||
|
||||
aggre1_noc: interconnect@16e0000 {
|
||||
compatible = "qcom,tuna-aggre1_noc";
|
||||
reg = <0x16e0000 0x16400>;
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
qcom,skip-qos;
|
||||
};
|
||||
|
||||
aggre2_noc: interconnect@1700000 {
|
||||
compatible = "qcom,tuna-aggre2_noc";
|
||||
reg = <0x1700000 0x1f400>;
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
qcom,skip-qos;
|
||||
};
|
||||
|
||||
mmss_noc: interconnect@1780000 {
|
||||
compatible = "qcom,tuna-mmss_noc";
|
||||
reg = <0x1780000 0x7d800>;
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
qcom,skip-qos;
|
||||
};
|
||||
|
||||
gem_noc: interconnect@24100000 {
|
||||
compatible = "qcom,tuna-gem_noc";
|
||||
reg = <0x24100000 0x14d080>;
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
qcom,skip-qos;
|
||||
};
|
||||
|
||||
nsp_noc: interconnect@320c0000 {
|
||||
compatible = "qcom,tuna-nsp_noc";
|
||||
reg = <0x320c0000 0xe080>;
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
qcom,skip-qos;
|
||||
};
|
||||
|
||||
lpass_ag_noc: interconnect@7e40000 {
|
||||
compatible = "qcom,tuna-lpass_ag_noc";
|
||||
reg = <0x7e40000 0xe080>;
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
qcom,skip-qos;
|
||||
};
|
||||
|
||||
lpass_lpiaon_noc: interconnect@7400000 {
|
||||
compatible = "qcom,tuna-lpass_lpiaon_noc";
|
||||
reg = <0x7400000 0x19080>;
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
qcom,skip-qos;
|
||||
};
|
||||
|
||||
lpass_lpicx_noc: interconnect@7420000 {
|
||||
compatible = "qcom,tuna-lpass_lpicx_noc";
|
||||
reg = <0x7420000 0x44080>;
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
qcom,skip-qos;
|
||||
};
|
||||
|
||||
ufsphy_mem: ufsphy_mem@1d80000 {
|
||||
reg = <0x1d80000 0x2000>;
|
||||
reg-names = "phy_mem";
|
||||
#phy-cells = <0>;
|
||||
|
||||
lanes-per-direction = <2>;
|
||||
clock-names = "ref_clk_src",
|
||||
"ref_aux_clk", "qref_clk",
|
||||
"rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk",
|
||||
"rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk";
|
||||
clocks = <&rpmhcc RPMH_CXO_PAD_CLK>,
|
||||
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
|
||||
<&tcsrcc TCSR_UFS_CLKREF_EN>,
|
||||
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC>,
|
||||
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC>,
|
||||
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC>,
|
||||
<&ufs_phy_rx_symbol_0_clk>,
|
||||
<&ufs_phy_rx_symbol_1_clk>,
|
||||
<&ufs_phy_tx_symbol_0_clk>;
|
||||
resets = <&ufshc_mem 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ufshc_mem: ufshc@1d84000 {
|
||||
compatible = "qcom,ufshc";
|
||||
reg = <0x1d84000 0x3000>;
|
||||
reg-names = "ufs_mem";
|
||||
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phys = <&ufsphy_mem>;
|
||||
phy-names = "ufsphy";
|
||||
#reset-cells = <1>;
|
||||
|
||||
lanes-per-direction = <2>;
|
||||
clock-names =
|
||||
"core_clk",
|
||||
"bus_aggr_clk",
|
||||
"iface_clk",
|
||||
"core_clk_unipro",
|
||||
"core_clk_ice",
|
||||
"ref_clk",
|
||||
"tx_lane0_sync_clk",
|
||||
"rx_lane0_sync_clk",
|
||||
"rx_lane1_sync_clk";
|
||||
clocks =
|
||||
<&gcc GCC_UFS_PHY_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
|
||||
<&gcc GCC_UFS_PHY_AHB_CLK>,
|
||||
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
|
||||
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
|
||||
<&rpmhcc RPMH_LN_BB_CLK3>,
|
||||
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
|
||||
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
|
||||
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
|
||||
freq-table-hz =
|
||||
<100000000 403000000>,
|
||||
<0 0>,
|
||||
<0 0>,
|
||||
<100000000 403000000>,
|
||||
<100000000 403000000>,
|
||||
<0 0>,
|
||||
<0 0>,
|
||||
<0 0>,
|
||||
<0 0>;
|
||||
|
||||
interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
|
||||
interconnect-names = "ufs-ddr", "cpu-ufs";
|
||||
|
||||
/* set the dependency that smmu being probed before ufs */
|
||||
depends-on-supply = <&apps_smmu>;
|
||||
|
||||
iommus = <&apps_smmu 0x60 0x0>;
|
||||
qcom,iommu-dma = "bypass";
|
||||
dma-coherent;
|
||||
|
||||
qcom,bypass-pbl-rst-wa;
|
||||
qcom,max-cpus = <8>;
|
||||
|
||||
reset-gpios = <&tlmm 187 GPIO_ACTIVE_LOW>;
|
||||
resets = <&gcc GCC_UFS_PHY_BCR>;
|
||||
reset-names = "rst";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
#include "tuna-gdsc.dtsi"
|
||||
|
||||
&cam_cc_ipe_0_gdsc {
|
||||
compatible = "regulator-fixed";
|
||||
compatible = "qcom,gdsc";
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&cam_cc_ofe_gdsc {
|
||||
compatible = "regulator-fixed";
|
||||
compatible = "qcom,gdsc";
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&cam_cc_tfe_0_gdsc {
|
||||
compatible = "regulator-fixed";
|
||||
compatible = "qcom,gdsc";
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&cam_cc_tfe_1_gdsc {
|
||||
compatible = "regulator-fixed";
|
||||
compatible = "qcom,gdsc";
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&cam_cc_tfe_2_gdsc {
|
||||
compatible = "regulator-fixed";
|
||||
compatible = "qcom,gdsc";
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&cam_cc_titan_top_gdsc {
|
||||
compatible = "regulator-fixed";
|
||||
compatible = "qcom,gdsc";
|
||||
parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
|
||||
Reference in New Issue
Block a user