From c7f0e45be6ef0bd9870dfd9e11c5f73cbca626d7 Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Sat, 13 Apr 2024 00:00:24 +0530 Subject: [PATCH 01/13] ARM: dts: msm: Add interconnect devices for TUNA Add interconnect devices for clk_virt_noc, mc_virt_noc, aggre1_noc, aggre2_noc, cnoc_cfg_noc, cnoc_main_noc, gem_noc, lpass_ag_noc, lpass_lpiaon_noc, lpass_lpicx_noc, mmss_noc, nsp_noc, pcie_anoc and system_noc. This will allow consumers to get their path and set bandwidth constraints on them. Change-Id: I0f5946c8f529dd7716ab9890221b3a32c4a55570 Signed-off-by: Raviteja Laggyshetty --- qcom/tuna.dtsi | 127 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 127 insertions(+) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index f9893d7d..796d9b55 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -12,6 +12,8 @@ #include #include #include +#include +#include #include #include #include @@ -343,6 +345,10 @@ , ; }; + + apps_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + }; }; }; @@ -851,6 +857,127 @@ reg = <0x1fc0000 0x30000>; }; + clk_virt: interconnect@0 { + compatible = "qcom,tuna-clk_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect@1 { + compatible = "qcom,tuna-mc_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + config_noc: interconnect@1600000 { + compatible = "qcom,tuna-cnoc_cfg"; + reg = <0x1600000 0x9200>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; + + cnoc_main: interconnect@1500000 { + compatible = "qcom,tuna-cnoc_main"; + reg = <0x1500000 0x16080>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; + + system_noc: interconnect@1680000 { + compatible = "qcom,tuna-system_noc"; + reg = <0x1680000 0x1d080>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; + + pcie_noc: interconnect@16c0000 { + compatible = "qcom,tuna-pcie_anoc"; + reg = <0x16c0000 0x11400>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,tuna-aggre1_noc"; + reg = <0x16e0000 0x16400>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,tuna-aggre2_noc"; + reg = <0x1700000 0x1f400>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; + + mmss_noc: interconnect@1780000 { + compatible = "qcom,tuna-mmss_noc"; + reg = <0x1780000 0x7d800>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; + + gem_noc: interconnect@24100000 { + compatible = "qcom,tuna-gem_noc"; + reg = <0x24100000 0x14d080>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; + + nsp_noc: interconnect@320c0000 { + compatible = "qcom,tuna-nsp_noc"; + reg = <0x320c0000 0xe080>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; + + lpass_ag_noc: interconnect@7e40000 { + compatible = "qcom,tuna-lpass_ag_noc"; + reg = <0x7e40000 0xe080>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; + + lpass_lpiaon_noc: interconnect@7400000 { + compatible = "qcom,tuna-lpass_lpiaon_noc"; + reg = <0x7400000 0x19080>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; + + lpass_lpicx_noc: interconnect@7420000 { + compatible = "qcom,tuna-lpass_lpicx_noc"; + reg = <0x7420000 0x44080>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; }; #include "tuna-gdsc.dtsi" From cccca1d8ac50a0b9db3f16d7843f58d518eff284 Mon Sep 17 00:00:00 2001 From: Sayali Patil Date: Thu, 1 Aug 2024 11:39:14 +0530 Subject: [PATCH 02/13] ARM: dts: msm: Reduce common CMA region size for monaco Reduce the common CMA region size for monaco to 16MB. Change-Id: I1dce0f34b53fc03556caefb69c6ff97ff8b5de0c Signed-off-by: Sayali Patil --- qcom/monaco.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index ecb440e1..d75a52bd 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -343,7 +343,7 @@ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; reusable; alignment = <0x0 0x400000>; - size = <0x0 0x2000000>; + size = <0x0 0x1000000>; linux,cma-default; }; }; From 942e7f19e75d562380ee6e0795a1b03a57ba47d8 Mon Sep 17 00:00:00 2001 From: Patrick Daly Date: Mon, 8 Jul 2024 23:51:27 -0700 Subject: [PATCH 03/13] ARM: dts: msm: Fix dependency between virtio-mem and mem-buf-msgq The virtio-mem device has always had a dependency on mem-buf for plugging in memory. Previously, the ordering was not a concern, since hotplug was not done until userspace was up. However, in subsequent patches we will instead hotplug in memory as soon as the virtio-mem device probes. Change-Id: I9c4e4728a15ab32d65ffaea0ba2681a816a4abf0 Signed-off-by: Patrick Daly --- qcom/sun-vm.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/qcom/sun-vm.dtsi b/qcom/sun-vm.dtsi index 32240b3c..49949341 100644 --- a/qcom/sun-vm.dtsi +++ b/qcom/sun-vm.dtsi @@ -707,13 +707,14 @@ qcom,vmid = <45>; }; - qcom,mem-buf-msgq { + mem_buf_msgq: qcom,mem-buf-msgq { compatible = "qcom,mem-buf-msgq"; qcom,msgq-names = "trusted_vm"; }; virtio_mem_device { compatible = "qcom,virtio-mem"; + depends-on-supply = <&mem_buf_msgq>; /* Must be memory_block_size_bytes() aligned */ qcom,max-size = <0x0 0x10000000>; qcom,ipa-range = <0x0 0x0 0xf 0xffffffff>; From 5a1d998abd1724a64479b038e34d2a765f62e4f0 Mon Sep 17 00:00:00 2001 From: Patrick Daly Date: Tue, 30 Jul 2024 18:20:02 -0700 Subject: [PATCH 04/13] dt-bindings: Document qcom,initial-movable-zone-size property This property describes how large of a movable zone should be created when the virtio_mem device probes. Also, fix all errors reported by make dt_binding_check. Change-Id: I487ad7592d54021ddbb3caddb20774d3e076c766 Signed-off-by: Patrick Daly --- bindings/virtio/qcom,virtio-mem.yaml | 32 +++++++++++++++++++--------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/bindings/virtio/qcom,virtio-mem.yaml b/bindings/virtio/qcom,virtio-mem.yaml index 0239476f..a640cd9f 100644 --- a/bindings/virtio/qcom,virtio-mem.yaml +++ b/bindings/virtio/qcom,virtio-mem.yaml @@ -1,10 +1,13 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/soc/qcom/qcom,secure-buffer.yaml#" +$id: "http://devicetree.org/schemas/virtio/qcom,virtio-mem.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" -title: Qualcomm Technologies, Inc. Virtio-Mem bindings +title: Qualcomm Technologies, Inc. Virtio-Mem + +maintainers: + - Patrick Daly description: | QTI virtio mem driver supports Guest initiated memory hotplug operations @@ -16,6 +19,7 @@ properties: - const: qcom,virtio-mem qcom,block-size: + $ref: '/schemas/types.yaml#/definitions/uint32' description: Minimum transfer size in bytes. Should be multiple of PAGE_SIZE. @@ -31,6 +35,11 @@ properties: is allowed to choose when adding hotpluggable memory for this device. + qcom,initial-movable-zone-size: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: | + Initial size of movable zone. + qcom,memory-encryption: type: boolean description: | @@ -39,14 +48,17 @@ properties: required: - compatible - - qcom,size + - qcom,max-size - qcom,ipa-range - qcom,block-size -example: - virtio_mem_device@0x60000000 { - compatible = "qcom,virtio-mem"; - qcom,block_size = <0x400000>; - qcom,size = <0x0 0x10000000>; - qcom,ipa-range = <0x0 0x0 0xf 0xffffffff>; - }; +additionalProperties: false + +examples: + - |+ + virtio_mem_device@0x60000000 { + compatible = "qcom,virtio-mem"; + qcom,block-size = <0x400000>; + qcom,max-size = <0x0 0x10000000>; + qcom,ipa-range = <0x0 0x0 0xf 0xffffffff>; + }; From efdc75332158a7c1532189f4626c3c3761550345 Mon Sep 17 00:00:00 2001 From: Patrick Daly Date: Mon, 8 Jul 2024 22:20:03 -0700 Subject: [PATCH 05/13] ARM: dts: msm: Add qcom,initial-movable-zone-size property "qcom,initial-movable-zone-size" creates a movable zone of the given size before userspace starts. This is useful in a system where a userspace component (psi-daemon) is used to hotplug in memory on a on-demand basis. With swap disabled, the current tvm carveout size (68 Mb) hits out-of-memory condition before psi-deamon is started. Once psi-daemon is running, it detects the number of blocks added to the movable zone via "qti_virtio_mem/kernel_plugged" sysfs file, and can reduce or increment the number as necessary. Change-Id: I5b62b6227e8a357ba3012979ed4bf937f1810437 Signed-off-by: Patrick Daly --- qcom/sun-vm.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sun-vm.dtsi b/qcom/sun-vm.dtsi index 49949341..1f17f2f3 100644 --- a/qcom/sun-vm.dtsi +++ b/qcom/sun-vm.dtsi @@ -719,6 +719,7 @@ qcom,max-size = <0x0 0x10000000>; qcom,ipa-range = <0x0 0x0 0xf 0xffffffff>; qcom,block-size = <0x400000>; + qcom,initial-movable-zone-size = <0x2000000>; }; qcom,gunyah-panic-notifier { From cf2d1ea24de45936a225ad723d3b43db40d5f4d4 Mon Sep 17 00:00:00 2001 From: Patrick Daly Date: Tue, 30 Jul 2024 16:19:32 -0700 Subject: [PATCH 06/13] ARM: dts: msm: Increase virtio-mem maximum size ZRAM is being disabled on tuivm due to observed stability issues due to ZRAM's use of GFP_MEMALLOC. Increase maximum movable zone size to compensate. When kswapd swaps out pages, PF_MEMALLOC is set, which results in zram ignoring the min_watermark, and lowmem_reserve. This is problematic because we intend for movable memory to stay in ZONE_MOVABLE, rather than falling back to ZONE_NORMAL. If the later occurs to such a high degree that all ZONE_NORMAL memory is consumed, as is observed to be the case during a "C2PA" testcase, attempts to plug in additional ZONE_MOVABLE memory may fail due to requiring a small amount of GFP_KERNEL memory. Change-Id: Ic847e90514f80ccb91daa98849440d7a9b97f156 Signed-off-by: Patrick Daly --- qcom/sun-vm.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sun-vm.dtsi b/qcom/sun-vm.dtsi index 1f17f2f3..f2f25f6e 100644 --- a/qcom/sun-vm.dtsi +++ b/qcom/sun-vm.dtsi @@ -716,7 +716,7 @@ compatible = "qcom,virtio-mem"; depends-on-supply = <&mem_buf_msgq>; /* Must be memory_block_size_bytes() aligned */ - qcom,max-size = <0x0 0x10000000>; + qcom,max-size = <0x0 0x18000000>; qcom,ipa-range = <0x0 0x0 0xf 0xffffffff>; qcom,block-size = <0x400000>; qcom,initial-movable-zone-size = <0x2000000>; From 0231442fdfabf2383b39e61f9237d057b36069e0 Mon Sep 17 00:00:00 2001 From: Nitesh Kumar Date: Tue, 6 Aug 2024 21:41:02 +0530 Subject: [PATCH 07/13] ARM: dts: qcom: Remove cpu pause action on boot core Remove cpu pause action on boot core in Parrot. Change-Id: I59e4e6cfec9073cd94a5bf0fcff96158d4061835 Signed-off-by: Nitesh Kumar --- qcom/parrot-thermal.dtsi | 17 ++--------------- 1 file changed, 2 insertions(+), 15 deletions(-) diff --git a/qcom/parrot-thermal.dtsi b/qcom/parrot-thermal.dtsi index 5f8de85c..76f426f8 100644 --- a/qcom/parrot-thermal.dtsi +++ b/qcom/parrot-thermal.dtsi @@ -722,25 +722,12 @@ type = "passive"; }; - cpu0_emerg: cpu0-emerg-cfg { - temperature = <110000>; - hysteresis = <10000>; - type = "passive"; - }; - reset-mon-cfg { temperature = <115000>; hysteresis = <0>; type = "hot"; }; }; - - cooling-maps { - cpu00_cdev { - trip = <&cpu0_emerg>; - cooling-device = <&cpu0_pause 1 1>; - }; - }; }; cpu-0-1 { @@ -1125,7 +1112,7 @@ }; }; - zeroc-0-step { + zeroc-0 { polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&tsens0 128>; @@ -1144,7 +1131,7 @@ }; }; - zeroc-1-step { + zeroc-1 { polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&tsens1 128>; From 0a427da5683d36e296d5c3cee502f629c50b72ed Mon Sep 17 00:00:00 2001 From: Archana Sriram Date: Thu, 25 Jul 2024 11:20:23 +0530 Subject: [PATCH 08/13] ARM: dts: msm: Update PMIC adc_tm nodes for parrot Modify pmk8350, pm7250b and pm6150l adc_tm nodes to suit qcom-spmi-adc-tm5 thermal driver for parrot. Change-Id: I66b5eadec9d926dd6fa9be1074611eda870cec50 Signed-off-by: Archana Sriram --- qcom/parrot-pm7250b.dtsi | 17 ++++++------ qcom/parrot-pmic-overlay.dtsi | 51 +++++++++++++++++------------------ qcom/pm6150l.dtsi | 2 +- qcom/pm7250b.dtsi | 2 +- qcom/pmk8350.dtsi | 2 +- 5 files changed, 37 insertions(+), 37 deletions(-) diff --git a/qcom/parrot-pm7250b.dtsi b/qcom/parrot-pm7250b.dtsi index 5f5864bb..446ce814 100644 --- a/qcom/parrot-pm7250b.dtsi +++ b/qcom/parrot-pm7250b.dtsi @@ -156,19 +156,20 @@ &pm7250b_adc_tm { interrupts = <0x8 0x35 0x0 IRQ_TYPE_EDGE_RISING>; - io-channels = <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, - <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>; + /* Channel nodes */ pm7250b_usb_conn_therm { - reg = ; + reg = <0>; + io-channels = <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>; qcom,ratiometric; - qcom,hw-settle-time = <200>; + qcom,hw-settle-time-us = <200>; }; pm7250b_smb_skin_therm { - reg = ; + reg = <1>; + io-channels = <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>; qcom,ratiometric; - qcom,hw-settle-time = <200>; + qcom,hw-settle-time-us = <200>; }; }; @@ -293,7 +294,7 @@ sys-therm-7 { polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM3_100K_PU>; + thermal-sensors = <&pm7250b_adc_tm 0>; trips { active-config0 { temperature = <125000>; @@ -312,7 +313,7 @@ sys-therm-6 { polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM1_100K_PU>; + thermal-sensors = <&pm7250b_adc_tm 1>; trips { active-config0 { temperature = <125000>; diff --git a/qcom/parrot-pmic-overlay.dtsi b/qcom/parrot-pmic-overlay.dtsi index 59248e27..736ff379 100644 --- a/qcom/parrot-pmic-overlay.dtsi +++ b/qcom/parrot-pmic-overlay.dtsi @@ -100,19 +100,19 @@ }; &pmk8350_adc_tm { - io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>, - <&pmk8350_vadc PM6450_ADC7_AMUX1_GPIO2_100K_PU>; - + /* Channel nodes */ pmk8350_xo_therm { - reg = ; + reg = <0>; + io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>; qcom,ratiometric; - qcom,hw-settle-time = <200>; + qcom,hw-settle-time-us = <200>; }; pm6450_quiet_therm { - reg = ; + reg = <1>; + io-channels = <&pmk8350_vadc PM6450_ADC7_AMUX1_GPIO2_100K_PU>; qcom,ratiometric; - qcom,hw-settle-time = <200>; + qcom,hw-settle-time-us = <200>; }; }; @@ -233,34 +233,33 @@ }; &pm6150l_adc_tm { - io-channels = <&pm6150l_vadc ADC5_AMUX_THM1_100K_PU>, - <&pm6150l_vadc ADC5_AMUX_THM3_100K_PU>, - <&pm6150l_vadc ADC5_GPIO1_100K_PU>, - <&pm6150l_vadc ADC5_GPIO3_100K_PU>; - /* Channel nodes */ pa_therm2 { - reg = ; + reg = <0>; + io-channels = <&pm6150l_vadc ADC5_AMUX_THM1_100K_PU>; qcom,ratiometric; - qcom,hw-settle-time = <200>; + qcom,hw-settle-time-us = <200>; }; pa_therm1 { - reg = ; + reg = <1>; + io-channels = <&pm6150l_vadc ADC5_AMUX_THM3_100K_PU>; qcom,ratiometric; - qcom,hw-settle-time = <200>; + qcom,hw-settle-time-us = <200>; }; ufs_therm { - reg = ; + reg = <2>; + io-channels = <&pm6150l_vadc ADC5_GPIO1_100K_PU>; qcom,ratiometric; - qcom,hw-settle-time = <200>; + qcom,hw-settle-time-us = <200>; }; wide_rfc_therm { - reg = ; + reg = <3>; + io-channels = <&pm6150l_vadc ADC5_GPIO3_100K_PU>; qcom,ratiometric; - qcom,hw-settle-time = <200>; + qcom,hw-settle-time-us = <200>; }; }; @@ -283,7 +282,7 @@ xo-therm { polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM1_100K_PU>; + thermal-sensors = <&pmk8350_adc_tm 0>; trips { active-config0 { temperature = <125000>; @@ -302,7 +301,7 @@ sys-therm-1 { polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&pm6150l_adc_tm ADC5_GPIO1_100K_PU>; + thermal-sensors = <&pm6150l_adc_tm 2>; trips { active-config0 { temperature = <125000>; @@ -321,7 +320,7 @@ sys-therm-2 { polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&pm6150l_adc_tm ADC5_GPIO3_100K_PU>; + thermal-sensors = <&pm6150l_adc_tm 3>; trips { active-config0 { temperature = <125000>; @@ -340,7 +339,7 @@ sys-therm-3 { polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&pmk8350_adc_tm PM6450_ADC7_AMUX1_GPIO2_100K_PU>; + thermal-sensors = <&pmk8350_adc_tm 1>; trips { active-config0 { temperature = <125000>; @@ -359,7 +358,7 @@ sys-therm-4 { polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&pm6150l_adc_tm ADC5_AMUX_THM1_100K_PU>; + thermal-sensors = <&pm6150l_adc_tm 0>; trips { active-config0 { temperature = <125000>; @@ -378,7 +377,7 @@ sys-therm-5 { polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&pm6150l_adc_tm ADC5_AMUX_THM3_100K_PU>; + thermal-sensors = <&pm6150l_adc_tm 1>; trips { active-config0 { temperature = <125000>; diff --git a/qcom/pm6150l.dtsi b/qcom/pm6150l.dtsi index 8a440751..f7c8757e 100644 --- a/qcom/pm6150l.dtsi +++ b/qcom/pm6150l.dtsi @@ -84,9 +84,9 @@ }; pm6150l_adc_tm: adc_tm@3500 { + compatible = "qcom,spmi-adc-tm5"; reg = <0x3500>; interrupts = <0x4 0x35 0x0 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "threshold"; #address-cells = <1>; #size-cells = <0>; #thermal-sensor-cells = <1>; diff --git a/qcom/pm7250b.dtsi b/qcom/pm7250b.dtsi index 74f5460e..db5d2961 100644 --- a/qcom/pm7250b.dtsi +++ b/qcom/pm7250b.dtsi @@ -158,9 +158,9 @@ }; pm7250b_adc_tm: adc_tm@3500 { + compatible = "qcom,spmi-adc-tm5"; reg = <0x3500>; interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "threshold"; #address-cells = <1>; #size-cells = <0>; #thermal-sensor-cells = <1>; diff --git a/qcom/pmk8350.dtsi b/qcom/pmk8350.dtsi index a7d14676..5664c5a2 100644 --- a/qcom/pmk8350.dtsi +++ b/qcom/pmk8350.dtsi @@ -183,9 +183,9 @@ }; pmk8350_adc_tm: adc_tm@3400 { + compatible = "qcom,spmi-adc-tm5-gen2"; reg = <0x3400>; interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "threshold"; #address-cells = <1>; #size-cells = <0>; #thermal-sensor-cells = <1>; From fb44aa4c0116e01c52ff081a967e47caad34716d Mon Sep 17 00:00:00 2001 From: Archana Sriram Date: Thu, 1 Aug 2024 14:44:27 +0530 Subject: [PATCH 09/13] ARM: dts: msm: Update PMIC adc_tm nodes for ravelin Modify pmk8350, pm7250b and pmi632 adc_tm nodes to suit qcom-spmi-adc-tm5 thermal driver for ravelin. Change-Id: I00fc712cda79b52b74a0e11da34bb2eae25414d4 Signed-off-by: Archana Sriram --- qcom/pmi632.dtsi | 2 +- qcom/ravelin-pm7250b.dtsi | 17 ++++++------ qcom/ravelin-pmi632.dtsi | 26 +++++++++--------- qcom/ravelin-pmic-overlay.dtsi | 50 +++++++++++++++++----------------- 4 files changed, 48 insertions(+), 47 deletions(-) diff --git a/qcom/pmi632.dtsi b/qcom/pmi632.dtsi index a6c9a75c..81017af1 100644 --- a/qcom/pmi632.dtsi +++ b/qcom/pmi632.dtsi @@ -116,9 +116,9 @@ }; pmi632_adc_tm: adc_tm@3500 { + compatible = "qcom,spmi-adc-tm5"; reg = <0x3500>; interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "threshold"; #address-cells = <1>; #size-cells = <0>; #thermal-sensor-cells = <1>; diff --git a/qcom/ravelin-pm7250b.dtsi b/qcom/ravelin-pm7250b.dtsi index 750724d2..8c6d249c 100644 --- a/qcom/ravelin-pm7250b.dtsi +++ b/qcom/ravelin-pm7250b.dtsi @@ -125,19 +125,20 @@ &pm7250b_adc_tm { interrupts = <0x8 0x35 0x0 IRQ_TYPE_EDGE_RISING>; - io-channels = <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, - <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>; + /* Channel nodes */ pm7250b_usb_conn_therm { - reg = ; + reg = <0>; + io-channels = <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>; qcom,ratiometric; - qcom,hw-settle-time = <200>; + qcom,hw-settle-time-us = <200>; }; pm7250b_charger_skin_therm { - reg = ; + reg = <1>; + io-channels = <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>; qcom,ratiometric; - qcom,hw-settle-time = <200>; + qcom,hw-settle-time-us = <200>; }; }; @@ -252,7 +253,7 @@ sys-therm-9 { polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM3_100K_PU>; + thermal-sensors = <&pm7250b_adc_tm 0>; trips { active-config0 { temperature = <125000>; @@ -271,7 +272,7 @@ sys-therm-7 { polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM1_100K_PU>; + thermal-sensors = <&pm7250b_adc_tm 1>; trips { active-config0 { temperature = <125000>; diff --git a/qcom/ravelin-pmi632.dtsi b/qcom/ravelin-pmi632.dtsi index 518976db..9386912a 100644 --- a/qcom/ravelin-pmi632.dtsi +++ b/qcom/ravelin-pmi632.dtsi @@ -143,26 +143,26 @@ }; &pmi632_adc_tm { - io-channels = <&pmi632_vadc ADC5_GPIO1_100K_PU>, - <&pmi632_vadc ADC5_GPIO2_100K_PU>, - <&pmi632_vadc ADC5_GPIO3_100K_PU>; - + /*Channel nodes */ pmi632_usb_conn_therm { - reg = ; + reg = <0>; + io-channels = <&pmi632_vadc ADC5_GPIO1_100K_PU>; qcom,ratiometric; - qcom,hw-settle-time = <200>; + qcom,hw-settle-time-us = <200>; }; pmi632_charger_skin_temp { - reg = ; + reg = <1>; + io-channels = <&pmi632_vadc ADC5_GPIO2_100K_PU>; qcom,ratiometric; - qcom,hw-settle-time = <200>; + qcom,hw-settle-time-us = <200>; }; pmi632_smb_skin_therm { - reg = ; + reg = <2>; + io-channels = <&pmi632_vadc ADC5_GPIO3_100K_PU>; qcom,ratiometric; - qcom,hw-settle-time = <200>; + qcom,hw-settle-time-us = <200>; }; }; @@ -262,7 +262,7 @@ sys-therm-9 { polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&pmi632_adc_tm ADC5_GPIO1_100K_PU>; + thermal-sensors = <&pmi632_adc_tm 0>; trips { active-config0 { temperature = <125000>; @@ -281,7 +281,7 @@ sys-therm-7 { polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&pmi632_adc_tm ADC5_GPIO2_100K_PU>; + thermal-sensors = <&pmi632_adc_tm 1>; trips { active-config0 { temperature = <125000>; @@ -300,7 +300,7 @@ sys-therm-8 { polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&pmi632_adc_tm ADC5_GPIO3_100K_PU>; + thermal-sensors = <&pmi632_adc_tm 2>; trips { active-config0 { temperature = <125000>; diff --git a/qcom/ravelin-pmic-overlay.dtsi b/qcom/ravelin-pmic-overlay.dtsi index 915a1d83..d94c9230 100644 --- a/qcom/ravelin-pmic-overlay.dtsi +++ b/qcom/ravelin-pmic-overlay.dtsi @@ -155,47 +155,47 @@ }; &pmk8350_adc_tm { - io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>, - <&pmk8350_vadc PM6450_ADC7_AMUX1_GPIO2_100K_PU>, - <&pmk8350_vadc PMK8350_ADC7_AMUX_THM2_100K_PU>, - <&pmk8350_vadc PM6450_ADC7_AMUX4_GPIO5_100K_PU>, - <&pmk8350_vadc PM6450_ADC7_AMUX3_GPIO4_100K_PU>, - <&pmk8350_vadc PMK8350_ADC7_AMUX_THM3_100K_PU>; - + /* Channel nodes */ pmk8350_xo_therm { - reg = ; + reg = <0>; + io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>; qcom,ratiometric; - qcom,hw-settle-time = <200>; + qcom,hw-settle-time-us = <200>; }; pm6450_quiet_therm { - reg = ; + reg = <1>; + io-channels = <&pmk8350_vadc PM6450_ADC7_AMUX1_GPIO2_100K_PU>; qcom,ratiometric; - qcom,hw-settle-time = <200>; + qcom,hw-settle-time-us = <200>; }; pmk8350_wide_rfc_therm { - reg = ; + reg = <2>; + io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM2_100K_PU>; qcom,ratiometric; - qcom,hw-settle-time = <200>; + qcom,hw-settle-time-us = <200>; }; pm6450_rear_cam_flash_therm { - reg = ; + reg = <3>; + io-channels = <&pmk8350_vadc PM6450_ADC7_AMUX4_GPIO5_100K_PU>; qcom,ratiometric; - qcom,hw-settle-time = <200>; + qcom,hw-settle-time-us = <200>; }; pm6450_pa2_therm { - reg = ; + reg = <4>; + io-channels = <&pmk8350_vadc PM6450_ADC7_AMUX3_GPIO4_100K_PU>; qcom,ratiometric; - qcom,hw-settle-time = <200>; + qcom,hw-settle-time-us = <200>; }; pmk8350_pa1_therm { - reg = ; + reg = <5>; + io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM3_100K_PU>; qcom,ratiometric; - qcom,hw-settle-time = <200>; + qcom,hw-settle-time-us = <200>; }; }; @@ -284,7 +284,7 @@ sys-therm-6 { polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM1_100K_PU>; + thermal-sensors = <&pmk8350_adc_tm 0>; trips { active-config0 { temperature = <125000>; @@ -303,7 +303,7 @@ sys-therm-4 { polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM2_100K_PU>; + thermal-sensors = <&pmk8350_adc_tm 2>; trips { active-config0 { temperature = <125000>; @@ -322,7 +322,7 @@ sys-therm-1 { polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&pmk8350_adc_tm PM6450_ADC7_AMUX1_GPIO2_100K_PU>; + thermal-sensors = <&pmk8350_adc_tm 1>; trips { active-config0 { temperature = <125000>; @@ -341,7 +341,7 @@ sys-therm-3 { polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&pmk8350_adc_tm PM6450_ADC7_AMUX4_GPIO5_100K_PU>; + thermal-sensors = <&pmk8350_adc_tm 3>; trips { active-config0 { temperature = <125000>; @@ -360,7 +360,7 @@ sys-therm-11 { polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&pmk8350_adc_tm PM6450_ADC7_AMUX3_GPIO4_100K_PU>; + thermal-sensors = <&pmk8350_adc_tm 4>; trips { active-config0 { temperature = <125000>; @@ -379,7 +379,7 @@ sys-therm-5 { polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM3_100K_PU>; + thermal-sensors = <&pmk8350_adc_tm 5>; trips { active-config0 { temperature = <125000>; From f01e170291a5b66111731c5d851ec63289725003 Mon Sep 17 00:00:00 2001 From: Avinash Philip Date: Thu, 25 Jul 2024 00:32:35 +0530 Subject: [PATCH 10/13] dt-bindings: arm: msm: qcom,llcc: Add compatible for child node Child node support for SCID heuristics compatible device. Change-Id: Id1fb1e190181d39053dce629c6807262032744ad Signed-off-by: Avinash Philip --- bindings/arm/msm/qcom,llcc.yaml | 63 ++++++++++++++++++++++++++------- 1 file changed, 51 insertions(+), 12 deletions(-) diff --git a/bindings/arm/msm/qcom,llcc.yaml b/bindings/arm/msm/qcom,llcc.yaml index 20bf3c49..555eadf1 100644 --- a/bindings/arm/msm/qcom,llcc.yaml +++ b/bindings/arm/msm/qcom,llcc.yaml @@ -9,14 +9,15 @@ title: Last Level Cache Controller maintainers: - Rishabh Bhatnagar - Sai Prakash Ranjan + - Avinash Philip description: | - LLCC (Last Level Cache Controller) provides last level of cache memory in SoC, - that can be shared by multiple clients. Clients here are different cores in the - SoC, the idea is to minimize the local caches at the clients and migrate to - common pool of memory. Cache memory is divided into partitions called slices - which are assigned to clients. Clients can query the slice details, activate - and deactivate them. + LLCC (Last Level Cache Controller) provides last level of cache memory in + SoC, that can be shared by multiple clients. Clients here are different cores + in the SoC, the idea is to minimize the local caches at the clients and + migrate to common pool of memory. Cache memory is divided into partitions + called slices which are assigned to clients. Clients can query the slice + details, activate and deactivate them. properties: compatible: @@ -49,11 +50,43 @@ properties: maxItems: 1 child-node: - description: Container of llcc_perfmon node + description: | + - Container of llcc_perfmon node + - Container of scid heuristics type: object properties: - compatible: - const: qcom,llcc-perfmon + compatible: + items: + - const: qcom,llcc-perfmon + - const: qcom,scid-heuristics + + qcom,heuristics_scid: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: | + SCID number of HEURISTICS SID + freq,threshold_idx: + $ref: '/schemas/types.yaml#/definitions/uint32-array' + description: | + CPU DVFS frequency threshold index + minItems: 1 + maxItems: 2 + freq,threshold_residency: + $ref: '/schemas/types.yaml#/definitions/uint32-array' + description: | + CPU DVFS frequency threshold Residency value in micro seconds + minItems: 1 + maxItems: 2 + qcom,scid_heuristics_enabled: + description: | + On enabling this flag, Heristics driver will communicate to qcom + control software to enable the Heristics based SCID functionality. + type: boolean + + required: + - compatible + + additionalProperties: false + required: - compatible - reg @@ -78,7 +111,7 @@ allOf: - description: LLCC3 base register region - description: LLCC broadcast base register region reg-names: - items: + items: - const: llcc0_base - const: llcc1_base - const: llcc2_base @@ -89,8 +122,6 @@ additionalProperties: false examples: - | - #include - soc { #address-cells = <2>; #size-cells = <2>; @@ -107,5 +138,13 @@ examples: llcc_perfmon { compatible = "qcom,llcc-perfmon"; } + + scid_heuristics { + compatible = "qcom,scid-heuristics"; + qcom,heuristics_scid = <32>; + freq,threshold_idx = <11>, <10>; + freq,threshold_residency = <5000>, <5000>; + qcom,scid_heuristics_enabled; + }; }; }; From d06b485834ff5a5654cd78eb77cbd84994b477c3 Mon Sep 17 00:00:00 2001 From: Manish Pandey Date: Fri, 9 Aug 2024 10:51:50 +0530 Subject: [PATCH 11/13] ARM: dts: msm: Add UFS nodes for tuna pre-sil Add UFS host controller and PHY nodes for tuna soc. Change-Id: I27f7c09355c54de15d7f9544918db830496e6c1f Signed-off-by: Manish Pandey --- qcom/tuna-rumi.dtsi | 80 +++++++++++++++++++++++++++++++++++++++++ qcom/tuna.dtsi | 87 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 167 insertions(+) diff --git a/qcom/tuna-rumi.dtsi b/qcom/tuna-rumi.dtsi index 7ece493c..c72f91ac 100644 --- a/qcom/tuna-rumi.dtsi +++ b/qcom/tuna-rumi.dtsi @@ -3,6 +3,9 @@ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include +#include + &arch_timer { clock-frequency = <500000>; }; @@ -31,6 +34,83 @@ }; }; +&ufsphy_mem { + compatible = "qcom,ufs-phy-qrbtc-sdm845"; + + /* VDDA_UFS_CORE */ + vdda-phy-supply = <&L1F>; + vdda-phy-max-microamp = <214160>; + /* + * Platforms supporting Gear 5 && Rate B require a different + * voltage supply. Check the Power Grid document. + */ + vdda-phy-min-microvolt = <912000>; + + /* VDDA_UFS_0_1P2 */ + vdda-pll-supply = <&L4B>; + vdda-pll-max-microamp = <18340>; + + /* Phy GDSC for VDD_MX, always on */ + vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>; + + /* Qref power supply, Refer Qref diagram */ + vdda-qref-supply = <&L2B>; + vdda-qref-max-microamp = <64500>; + + /* Detect whether RH132 card based sequences to be used */ + qcom,soc_emulation_type_addr = <0x1fc8004>; + qcom,soc_emulation_type_bits = <32>; + + status = "ok"; +}; + +&ufshc_mem { + limit-tx-hs-gear = <1>; + limit-rx-hs-gear = <1>; + limit-rate = <2>; /* HS Rate-B */ + rpm-level = <0>; + spm-level = <0>; + + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + + vcc-supply = <&L12B>; + vcc-max-microamp = <1200000>; + + vccq-supply = <&L3F>; + vccq-max-microamp = <1200000>; + + qcom,vddp-ref-clk-supply = <&L5B>; + qcom,vddp-ref-clk-max-microamp = <100>; + + qcom,vccq-parent-supply = <&S2B>; + qcom,vccq-parent-max-microamp = <210000>; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&rpmhcc RPMH_CXO_PAD_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + + qcom,disable-lpm; + + status = "ok"; +}; + &usb0 { dwc3@a600000 { usb-phy = <&usb_emuphy>, <&usb_nop_phy>; diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index a1efb3ce..8d5154e3 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -17,6 +17,7 @@ #include #include #include +#include / { model = "Qualcomm Technologies, Inc. Tuna"; @@ -47,6 +48,7 @@ aliases { serial0 = &qupv3_se7_2uart; + ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ }; cpus { @@ -987,6 +989,91 @@ qcom,bcm-voters = <&apps_bcm_voter>; qcom,skip-qos; }; + + ufsphy_mem: ufsphy_mem@1d80000 { + reg = <0x1d80000 0x2000>; + reg-names = "phy_mem"; + #phy-cells = <0>; + + lanes-per-direction = <2>; + clock-names = "ref_clk_src", + "ref_aux_clk", "qref_clk", + "rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk", + "rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk"; + clocks = <&rpmhcc RPMH_CXO_PAD_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&tcsrcc TCSR_UFS_CLKREF_EN>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC>, + <&ufs_phy_rx_symbol_0_clk>, + <&ufs_phy_rx_symbol_1_clk>, + <&ufs_phy_tx_symbol_0_clk>; + resets = <&ufshc_mem 0>; + status = "disabled"; + }; + + ufshc_mem: ufshc@1d84000 { + compatible = "qcom,ufshc"; + reg = <0x1d84000 0x3000>; + reg-names = "ufs_mem"; + interrupts = ; + phys = <&ufsphy_mem>; + phy-names = "ufsphy"; + #reset-cells = <1>; + + lanes-per-direction = <2>; + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&rpmhcc RPMH_LN_BB_CLK3>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <100000000 403000000>, + <0 0>, + <0 0>, + <100000000 403000000>, + <100000000 403000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + + /* set the dependency that smmu being probed before ufs */ + depends-on-supply = <&apps_smmu>; + + iommus = <&apps_smmu 0x60 0x0>; + qcom,iommu-dma = "bypass"; + dma-coherent; + + qcom,bypass-pbl-rst-wa; + qcom,max-cpus = <8>; + + reset-gpios = <&tlmm 187 GPIO_ACTIVE_LOW>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + status = "disabled"; + }; }; #include "tuna-gdsc.dtsi" From 2e025643d44568c0c468df42e7d98f167dacd53b Mon Sep 17 00:00:00 2001 From: Ajit Pandey Date: Mon, 15 Jul 2024 15:51:06 +0530 Subject: [PATCH 12/13] ARM: dts: msm: Add support for camera clock controllers on Tuna Add support for CAMCC and CAM_BIST_MCLK_CC clock controller nodes on Tuna platform. While at it, move camcc gdsc's to real. Change-Id: I14e7add272a549cd21c39083a26baac4c50de31e Signed-off-by: Ajit Pandey --- qcom/tuna.dtsi | 46 ++++++++++++++++++++++++++++++++++++---------- 1 file changed, 36 insertions(+), 10 deletions(-) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index a1efb3ce..6c86c763 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -757,15 +757,40 @@ }; cambistmclkcc: clock-controller@1760000 { - compatible = "qcom,dummycc"; - clock-output-names = "cambistmclkcc_clocks"; + compatible = "qcom,tuna-cambistmclkcc", "syscon"; + reg = <0x1760000 0x6000>; + reg-name = "cc_base"; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "bi_tcxo", + "sleep_clk", + "iface"; #clock-cells = <1>; #reset-cells = <1>; }; + + cam_crm: syscon@adcd600 { + compatible = "syscon"; + reg = <0xadcd600 0x2000>; + }; + camcc: clock-controller@ade0000 { - compatible = "qcom,dummycc"; - clock-output-names = "camcc_clocks"; + compatible = "qcom,tuna-camcc", "syscon"; + reg = <0xade0000 0x20000>; + reg-name = "cc_base"; + vdd_mm-supply = <&VDD_MM_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + vdd_mxc-supply = <&VDD_MXC_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "bi_tcxo", + "sleep_clk", + "iface"; + qcom,cam_crm-crmc = <&cam_crm>; #clock-cells = <1>; #reset-cells = <1>; }; @@ -992,32 +1017,33 @@ #include "tuna-gdsc.dtsi" &cam_cc_ipe_0_gdsc { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; status = "ok"; }; &cam_cc_ofe_gdsc { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; status = "ok"; }; &cam_cc_tfe_0_gdsc { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; status = "ok"; }; &cam_cc_tfe_1_gdsc { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; status = "ok"; }; &cam_cc_tfe_2_gdsc { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; status = "ok"; }; &cam_cc_titan_top_gdsc { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; + parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>; status = "ok"; }; From b340945a3521c32e9a42b1e2db8b42a38fd566bd Mon Sep 17 00:00:00 2001 From: Avinash Philip Date: Fri, 19 Jul 2024 10:12:58 +0530 Subject: [PATCH 13/13] ARM: dts: msm: SLC SCID Heuristics support for sun Enables HEURISTICS SCID for sun. Change-Id: I1f52aeb0000c5835236bf6c04cc3c51e87cdfedf Signed-off-by: Avinash Philip --- qcom/sun.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index 19a60eaa..be6624b9 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -923,6 +923,15 @@ clocks = <&aoss_qmp QDSS_CLK>; clock-names = "qdss_clk"; }; + + scid_heuristics { + compatible = "qcom,scid-heuristics"; + qcom,heuristics_scid = <32>; + /* Need to update different value for V2 device */ + freq,threshold_idx = <11>, <10>; + freq,threshold_residency = <5000>, <5000>; + qcom,scid_heuristics_enabled; + }; }; gic-interrupt-router {