samsung_sm8750/android_kernel_samsung_sm8750-devicetrees
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Merge remote-tracking branch 'quic/display-kernel-dev.lnx.1.0' into display-kernel.lnx.11.0

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CRs              SHA_ID     Commit Message
----------------------------------------------------------------------
3880187           I385a554b ARM: dts: msm: Add spr pentile pack type for SPR panel
3854597           I0fd532d3 ARM: dts: msm: add battery_charger and qupv3_se15_i2c support
3860772           I01e0fedb ARM: dts: msm: move esync RCG to SDE DSI node
3867625           I1e3a94b2 ARM: dts: msm: update pm qos for sun target

CRs-Included: 3860772,3854597,3867625,3880187 .

Change-Id: I7019c8f8613969f8e30c517e844f43fdde748a83
Signed-off-by: lnxdisplay <lnxdisplay@localhost>
This commit is contained in:
lnxdisplay
2024-08-08 16:23:41 +05:30
parent 009f350e70 c9d0cbfd11
commit 304733efa4
12 changed files with 74 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi
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@@ -51,7 +51,7 @@
* # R B R B ... B R B R ... R B R B ... B R B R ... * # R B R B ... B R B R ... R B R B ... B R B R ...
* ############################################################### * ###############################################################
*/ */
qcom,spr-pentile-pack-type = "RG-BG Type A"; qcom,spr-pentile-pack-type = "BG-RG Type B";
qcom,mdss-dsi-panel-hdr-enabled; qcom,mdss-dsi-panel-hdr-enabled;
qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
15700 12250 35800 6750 2550>; 15700 12250 35800 6750 2550>;

14
display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi
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@@ -40,6 +40,20 @@
qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-check-enable;
qcom,mdss-dsi-te-using-te-pin; qcom,mdss-dsi-te-using-te-pin;
qcom,spr-pack-type = "pentile"; qcom,spr-pack-type = "pentile";
/*
* ###############################################################
* # Pentile SPR phases for SM8750 and later
* ###############################################################
* # RG/BG Type A BG/RG Type A GR/GB Type A GB/GR Type A
* # R B R B ... B R B R ... R B R B ... B R B R ...
* # G G G G ... G G G G ... G G G G ... G G G G ...
* #
* # RG/BG Type B BG/RG Type B GR/GB Type B GB/GR Type B
* # G G G G ... G G G G ... G G G G ... G G G G ...
* # R B R B ... B R B R ... R B R B ... B R B R ...
* ###############################################################
*/
qcom,spr-pentile-pack-type = "BG-RG Type B";
qcom,mdss-dsi-panel-hdr-enabled; qcom,mdss-dsi-panel-hdr-enabled;
qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
15700 12250 35800 6750 2550>; 15700 12250 35800 6750 2550>;

2
display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi
View File

@@ -53,7 +53,7 @@
* # R B R B ... B R B R ... R B R B ... B R B R ... * # R B R B ... B R B R ... R B R B ... B R B R ...
* ############################################################### * ###############################################################
*/ */
qcom,spr-pentile-pack-type = "RG-BG Type A"; qcom,spr-pentile-pack-type = "BG-RG Type B";
qcom,mdss-dsi-panel-hdr-enabled; qcom,mdss-dsi-panel-hdr-enabled;
qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
15700 12250 35800 6750 2550>; 15700 12250 35800 6750 2550>;

2
display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi
View File

@@ -41,7 +41,7 @@
* # R B R B ... B R B R ... R B R B ... B R B R ... * # R B R B ... B R B R ... R B R B ... B R B R ...
* ############################################################### * ###############################################################
*/ */
qcom,spr-pentile-pack-type = "RG-BG Type A"; qcom,spr-pentile-pack-type = "BG-RG Type B";
qcom,mdss-dsi-panel-hdr-enabled; qcom,mdss-dsi-panel-hdr-enabled;
qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
15700 12250 35800 6750 2550>; 15700 12250 35800 6750 2550>;

14
display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi
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@@ -33,6 +33,20 @@
qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-start = <0x2c>;
qcom,mdss-dsi-wr-mem-continue = <0x3c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>;
qcom,spr-pack-type = "pentile"; qcom,spr-pack-type = "pentile";
/*
* ###############################################################
* # Pentile SPR phases for SM8750 and later
* ###############################################################
* # RG/BG Type A BG/RG Type A GR/GB Type A GB/GR Type A
* # R B R B ... B R B R ... R B R B ... B R B R ...
* # G G G G ... G G G G ... G G G G ... G G G G ...
* #
* # RG/BG Type B BG/RG Type B GR/GB Type B GB/GR Type B
* # G G G G ... G G G G ... G G G G ... G G G G ...
* # R B R B ... B R B R ... R B R B ... B R B R ...
* ###############################################################
*/
qcom,spr-pentile-pack-type = "BG-RG Type B";
qcom,mdss-dsi-panel-hdr-enabled; qcom,mdss-dsi-panel-hdr-enabled;
qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
15700 12250 35800 6750 2550>; 15700 12250 35800 6750 2550>;

2
display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi
View File

@@ -46,7 +46,7 @@
* # R B R B ... B R B R ... R B R B ... B R B R ... * # R B R B ... B R B R ... R B R B ... B R B R ...
* ############################################################### * ###############################################################
*/ */
qcom,spr-pentile-pack-type = "RG-BG Type A"; qcom,spr-pentile-pack-type = "BG-RG Type B";
qcom,mdss-dsi-panel-hdr-enabled; qcom,mdss-dsi-panel-hdr-enabled;
qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
15700 12250 35800 6750 2550>; 15700 12250 35800 6750 2550>;

1
display/sun-sde-common.dtsi
View File

@@ -259,6 +259,7 @@
qcom,sde-cdp-setting = <1 1>, <1 0>; qcom,sde-cdp-setting = <1 1>, <1 0>;
qcom,sde-qos-cpu-mask = <0x3>;
qcom,sde-qos-cpu-mask-performance = <0x3>; qcom,sde-qos-cpu-mask-performance = <0x3>;
qcom,sde-qos-cpu-dma-latency = <300>; qcom,sde-qos-cpu-dma-latency = <300>;
qcom,sde-qos-cpu-irq-latency = <300>; qcom,sde-qos-cpu-irq-latency = <300>;

9
display/sun-sde-display-cdp.dtsi
View File

@@ -307,6 +307,13 @@
&dsi_nt37801_amoled_video &dsi_nt37801_amoled_video
&dsi_nt37801_amoled_video_cphy &dsi_nt37801_amoled_video_cphy
&dsi_nt37801_amoled_cmd_spr &dsi_nt37801_amoled_cmd_spr
&dsi_nt37801_amoled_vid_spr>; &dsi_nt37801_amoled_vid_spr
&dsi_nt37801_amoled_dsc_10b_cmd
&dsi_nt37801_amoled_dsc_10b_video
&dsi_nt37801_amoled_qsync_cmd
&dsi_nt37801_amoled_qsync_video
&dsi_nt37801_amoled_fhd_plus_cmd
&dsi_nt37801_amoled_cmd_ddicspr
&dsi_nt37801_amoled_video_ddicspr>;
}; };
}; };

9
display/sun-sde-display-mtp.dtsi
View File

@@ -289,5 +289,12 @@
&dsi_nt37801_amoled_video &dsi_nt37801_amoled_video
&dsi_nt37801_amoled_video_cphy &dsi_nt37801_amoled_video_cphy
&dsi_nt37801_amoled_cmd_spr &dsi_nt37801_amoled_cmd_spr
&dsi_nt37801_amoled_vid_spr>; &dsi_nt37801_amoled_vid_spr
&dsi_nt37801_amoled_dsc_10b_cmd
&dsi_nt37801_amoled_dsc_10b_video
&dsi_nt37801_amoled_qsync_cmd
&dsi_nt37801_amoled_qsync_video
&dsi_nt37801_amoled_fhd_plus_cmd
&dsi_nt37801_amoled_cmd_ddicspr
&dsi_nt37801_amoled_video_ddicspr>;
}; };

4
display/sun-sde-display-qrd.dtsi
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@@ -230,5 +230,7 @@
qcom,display-panels = <&dsi_nt37801_amoled_cmd qcom,display-panels = <&dsi_nt37801_amoled_cmd
&dsi_nt37801_amoled_cmd_cphy &dsi_nt37801_amoled_cmd_cphy
&dsi_nt37801_amoled_video &dsi_nt37801_amoled_video
&dsi_nt37801_amoled_video_cphy>; &dsi_nt37801_amoled_video_cphy
&dsi_nt37801_amoled_qsync_cmd_cphy
&dsi_nt37801_amoled_qsync_video_cphy>;
}; };

22
display/sun-sde-display.dtsi
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@@ -92,10 +92,17 @@
* MDP clock nodes, no actual vote shall be added and this * MDP clock nodes, no actual vote shall be added and this
* change is done just to satisfy sync state requirements. * change is done just to satisfy sync state requirements.
*/ */
<&dispcc DISP_CC_MDSS_MDP_CLK>; <&dispcc DISP_CC_MDSS_MDP_CLK>,
/*
* The esync clk RCG is only necessary here to set its parent
* to the pll dsi clk, which also needs to be available at the
* point that its known whether the clock will be used. After
* updating the parent, this clock handle is no longer needed.
*/
<&dispcc DISP_CC_ESYNC0_CLK_SRC>;
clock-names = "pll_byte_clk0", "pll_dsi_clk0", clock-names = "pll_byte_clk0", "pll_dsi_clk0",
"pll_byte_clk1", "pll_dsi_clk1", "pll_byte_clk1", "pll_dsi_clk1",
"mdp_core_clk"; "mdp_core_clk", "esync_clk_rcg";
vddio-supply = <&L12B>; vddio-supply = <&L12B>;
vci-supply = <&L13B>; vci-supply = <&L13B>;
vdd-supply = <&L11B>; vdd-supply = <&L11B>;
@@ -121,10 +128,17 @@
* MDP clock nodes, no actual vote shall be added and this * MDP clock nodes, no actual vote shall be added and this
* change is done just to satisfy sync state requirements. * change is done just to satisfy sync state requirements.
*/ */
<&dispcc DISP_CC_MDSS_MDP_CLK>; <&dispcc DISP_CC_MDSS_MDP_CLK>,
/*
* The esync clk RCG is only necessary here to set its parent
* to the pll dsi clk, which also needs to be available at the
* point that its known whether the clock will be used. After
* updating the parent, this clock handle is no longer needed.
*/
<&dispcc DISP_CC_ESYNC1_CLK_SRC>;
clock-names = "pll_byte_clk0", "pll_dsi_clk0", clock-names = "pll_byte_clk0", "pll_dsi_clk0",
"pll_byte_clk1", "pll_dsi_clk1", "pll_byte_clk1", "pll_dsi_clk1",
"mdp_core_clk"; "mdp_core_clk", "esync_clk_rcg";
vddio-supply = <&L12B>; vddio-supply = <&L12B>;
vci-supply = <&L13B>; vci-supply = <&L13B>;
vdd-supply = <&L11B>; vdd-supply = <&L11B>;

12
display/sun-sde.dtsi
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@@ -313,15 +313,13 @@
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK>, <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
<&mdss_dsi_phy0 1>,
<&dispcc DISP_CC_ESYNC0_CLK>, <&dispcc DISP_CC_ESYNC0_CLK>,
<&dispcc DISP_CC_ESYNC0_CLK_SRC>,
<&dispcc DISP_CC_OSC_CLK>, <&dispcc DISP_CC_OSC_CLK>,
<&dispcc DISP_CC_MDSS_ESC0_CLK>, <&dispcc DISP_CC_MDSS_ESC0_CLK>,
<&rpmhcc RPMH_CXO_CLK>; <&rpmhcc RPMH_CXO_CLK>;
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
"pixel_clk", "pixel_clk_rcg", "pll_dsi_clk", "pixel_clk", "pixel_clk_rcg", "esync_clk", "osc_clk",
"esync_clk", "esync_clk_rcg", "osc_clk", "esc_clk", "xo"; "esc_clk", "xo";
}; };
&mdss_dsi1 { &mdss_dsi1 {
@@ -332,15 +330,13 @@
<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
<&dispcc DISP_CC_MDSS_PCLK1_CLK>, <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>,
<&mdss_dsi_phy1 1>,
<&dispcc DISP_CC_ESYNC1_CLK>, <&dispcc DISP_CC_ESYNC1_CLK>,
<&dispcc DISP_CC_ESYNC1_CLK_SRC>,
<&dispcc DISP_CC_OSC_CLK>, <&dispcc DISP_CC_OSC_CLK>,
<&dispcc DISP_CC_MDSS_ESC1_CLK>, <&dispcc DISP_CC_MDSS_ESC1_CLK>,
<&rpmhcc RPMH_CXO_CLK>; <&rpmhcc RPMH_CXO_CLK>;
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
"pixel_clk", "pixel_clk_rcg", "pll_dsi_clk", "pixel_clk", "pixel_clk_rcg", "esync_clk", "osc_clk",
"esync_clk", "esync_clk_rcg", "osc_clk", "esc_clk", "xo"; "esc_clk", "xo";
}; };
&mdss_dsi_phy0 { &mdss_dsi_phy0 {