diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi index 45becd88..29afd64e 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi @@ -51,7 +51,7 @@ * # R B R B ... B R B R ... R B R B ... B R B R ... * ############################################################### */ - qcom,spr-pentile-pack-type = "RG-BG Type A"; + qcom,spr-pentile-pack-type = "BG-RG Type B"; qcom,mdss-dsi-panel-hdr-enabled; qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 15700 12250 35800 6750 2550>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi index 62b5e7fe..08e9b8b7 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi @@ -40,6 +40,20 @@ qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; qcom,spr-pack-type = "pentile"; + /* + * ############################################################### + * # Pentile SPR phases for SM8750 and later + * ############################################################### + * # RG/BG Type A BG/RG Type A GR/GB Type A GB/GR Type A + * # R B R B ... B R B R ... R B R B ... B R B R ... + * # G G G G ... G G G G ... G G G G ... G G G G ... + * # + * # RG/BG Type B BG/RG Type B GR/GB Type B GB/GR Type B + * # G G G G ... G G G G ... G G G G ... G G G G ... + * # R B R B ... B R B R ... R B R B ... B R B R ... + * ############################################################### + */ + qcom,spr-pentile-pack-type = "BG-RG Type B"; qcom,mdss-dsi-panel-hdr-enabled; qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 15700 12250 35800 6750 2550>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi index 0aadeb93..5f34e53e 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi @@ -53,7 +53,7 @@ * # R B R B ... B R B R ... R B R B ... B R B R ... * ############################################################### */ - qcom,spr-pentile-pack-type = "RG-BG Type A"; + qcom,spr-pentile-pack-type = "BG-RG Type B"; qcom,mdss-dsi-panel-hdr-enabled; qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 15700 12250 35800 6750 2550>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi index fe91c356..26b49ed2 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi @@ -41,7 +41,7 @@ * # R B R B ... B R B R ... R B R B ... B R B R ... * ############################################################### */ - qcom,spr-pentile-pack-type = "RG-BG Type A"; + qcom,spr-pentile-pack-type = "BG-RG Type B"; qcom,mdss-dsi-panel-hdr-enabled; qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 15700 12250 35800 6750 2550>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi index 0e1886aa..21e44730 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi @@ -33,6 +33,20 @@ qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; qcom,spr-pack-type = "pentile"; + /* + * ############################################################### + * # Pentile SPR phases for SM8750 and later + * ############################################################### + * # RG/BG Type A BG/RG Type A GR/GB Type A GB/GR Type A + * # R B R B ... B R B R ... R B R B ... B R B R ... + * # G G G G ... G G G G ... G G G G ... G G G G ... + * # + * # RG/BG Type B BG/RG Type B GR/GB Type B GB/GR Type B + * # G G G G ... G G G G ... G G G G ... G G G G ... + * # R B R B ... B R B R ... R B R B ... B R B R ... + * ############################################################### + */ + qcom,spr-pentile-pack-type = "BG-RG Type B"; qcom,mdss-dsi-panel-hdr-enabled; qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 15700 12250 35800 6750 2550>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi index 38821fc6..64d790cd 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi @@ -46,7 +46,7 @@ * # R B R B ... B R B R ... R B R B ... B R B R ... * ############################################################### */ - qcom,spr-pentile-pack-type = "RG-BG Type A"; + qcom,spr-pentile-pack-type = "BG-RG Type B"; qcom,mdss-dsi-panel-hdr-enabled; qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 15700 12250 35800 6750 2550>; diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index 7e0b89cc..8a68f314 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -259,6 +259,7 @@ qcom,sde-cdp-setting = <1 1>, <1 0>; + qcom,sde-qos-cpu-mask = <0x3>; qcom,sde-qos-cpu-mask-performance = <0x3>; qcom,sde-qos-cpu-dma-latency = <300>; qcom,sde-qos-cpu-irq-latency = <300>; diff --git a/display/sun-sde-display-cdp.dtsi b/display/sun-sde-display-cdp.dtsi index 2049962d..b2dd5503 100644 --- a/display/sun-sde-display-cdp.dtsi +++ b/display/sun-sde-display-cdp.dtsi @@ -307,6 +307,13 @@ &dsi_nt37801_amoled_video &dsi_nt37801_amoled_video_cphy &dsi_nt37801_amoled_cmd_spr - &dsi_nt37801_amoled_vid_spr>; + &dsi_nt37801_amoled_vid_spr + &dsi_nt37801_amoled_dsc_10b_cmd + &dsi_nt37801_amoled_dsc_10b_video + &dsi_nt37801_amoled_qsync_cmd + &dsi_nt37801_amoled_qsync_video + &dsi_nt37801_amoled_fhd_plus_cmd + &dsi_nt37801_amoled_cmd_ddicspr + &dsi_nt37801_amoled_video_ddicspr>; }; }; diff --git a/display/sun-sde-display-mtp.dtsi b/display/sun-sde-display-mtp.dtsi index baa362b2..b62cf120 100644 --- a/display/sun-sde-display-mtp.dtsi +++ b/display/sun-sde-display-mtp.dtsi @@ -289,5 +289,12 @@ &dsi_nt37801_amoled_video &dsi_nt37801_amoled_video_cphy &dsi_nt37801_amoled_cmd_spr - &dsi_nt37801_amoled_vid_spr>; + &dsi_nt37801_amoled_vid_spr + &dsi_nt37801_amoled_dsc_10b_cmd + &dsi_nt37801_amoled_dsc_10b_video + &dsi_nt37801_amoled_qsync_cmd + &dsi_nt37801_amoled_qsync_video + &dsi_nt37801_amoled_fhd_plus_cmd + &dsi_nt37801_amoled_cmd_ddicspr + &dsi_nt37801_amoled_video_ddicspr>; }; diff --git a/display/sun-sde-display-qrd.dtsi b/display/sun-sde-display-qrd.dtsi index c1339749..2e91032c 100644 --- a/display/sun-sde-display-qrd.dtsi +++ b/display/sun-sde-display-qrd.dtsi @@ -230,5 +230,7 @@ qcom,display-panels = <&dsi_nt37801_amoled_cmd &dsi_nt37801_amoled_cmd_cphy &dsi_nt37801_amoled_video - &dsi_nt37801_amoled_video_cphy>; + &dsi_nt37801_amoled_video_cphy + &dsi_nt37801_amoled_qsync_cmd_cphy + &dsi_nt37801_amoled_qsync_video_cphy>; }; diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index c779d0fd..03774135 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -92,10 +92,17 @@ * MDP clock nodes, no actual vote shall be added and this * change is done just to satisfy sync state requirements. */ - <&dispcc DISP_CC_MDSS_MDP_CLK>; + <&dispcc DISP_CC_MDSS_MDP_CLK>, + /* + * The esync clk RCG is only necessary here to set its parent + * to the pll dsi clk, which also needs to be available at the + * point that its known whether the clock will be used. After + * updating the parent, this clock handle is no longer needed. + */ + <&dispcc DISP_CC_ESYNC0_CLK_SRC>; clock-names = "pll_byte_clk0", "pll_dsi_clk0", "pll_byte_clk1", "pll_dsi_clk1", - "mdp_core_clk"; + "mdp_core_clk", "esync_clk_rcg"; vddio-supply = <&L12B>; vci-supply = <&L13B>; vdd-supply = <&L11B>; @@ -121,10 +128,17 @@ * MDP clock nodes, no actual vote shall be added and this * change is done just to satisfy sync state requirements. */ - <&dispcc DISP_CC_MDSS_MDP_CLK>; + <&dispcc DISP_CC_MDSS_MDP_CLK>, + /* + * The esync clk RCG is only necessary here to set its parent + * to the pll dsi clk, which also needs to be available at the + * point that its known whether the clock will be used. After + * updating the parent, this clock handle is no longer needed. + */ + <&dispcc DISP_CC_ESYNC1_CLK_SRC>; clock-names = "pll_byte_clk0", "pll_dsi_clk0", "pll_byte_clk1", "pll_dsi_clk1", - "mdp_core_clk"; + "mdp_core_clk", "esync_clk_rcg"; vddio-supply = <&L12B>; vci-supply = <&L13B>; vdd-supply = <&L11B>; diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index f0d8064c..3c3f1462 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -313,15 +313,13 @@ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, <&dispcc DISP_CC_MDSS_PCLK0_CLK>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, - <&mdss_dsi_phy0 1>, <&dispcc DISP_CC_ESYNC0_CLK>, - <&dispcc DISP_CC_ESYNC0_CLK_SRC>, <&dispcc DISP_CC_OSC_CLK>, <&dispcc DISP_CC_MDSS_ESC0_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "pll_dsi_clk", - "esync_clk", "esync_clk_rcg", "osc_clk", "esc_clk", "xo"; + "pixel_clk", "pixel_clk_rcg", "esync_clk", "osc_clk", + "esc_clk", "xo"; }; &mdss_dsi1 { @@ -332,15 +330,13 @@ <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, <&dispcc DISP_CC_MDSS_PCLK1_CLK>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, - <&mdss_dsi_phy1 1>, <&dispcc DISP_CC_ESYNC1_CLK>, - <&dispcc DISP_CC_ESYNC1_CLK_SRC>, <&dispcc DISP_CC_OSC_CLK>, <&dispcc DISP_CC_MDSS_ESC1_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "pll_dsi_clk", - "esync_clk", "esync_clk_rcg", "osc_clk", "esc_clk", "xo"; + "pixel_clk", "pixel_clk_rcg", "esync_clk", "osc_clk", + "esc_clk", "xo"; }; &mdss_dsi_phy0 {