ARM: dts: msm: Reduce SE8 CLK to operate in lowSVS

To handle power regression at SE8 end reduce
SCL clock, which makes the QUP clock domain to
run in LowSVS instead of SVS. And the theoritical
latency calculated for this change is minimal, around
0.3 msec for 200 xfers.

CRs-Fixed: 3859750
Change-Id: I256e745a6edbdb356b297cf4d8909ca214840120
Signed-off-by: Lokesh Kumar Aakulu <quic_lkumar@quicinc.com>
This commit is contained in:
Lokesh Kumar Aakulu
2024-07-18 09:37:08 -07:00
committed by Camera Software Integration
parent d156c92d31
commit 29e9e7351f
4 changed files with 8 additions and 8 deletions

View File

@@ -585,8 +585,8 @@
}; };
&i3c3 { &i3c3 {
se-clock-frequency = <100000000>; se-clock-frequency = <64000000>;
i3c-scl-hz = <12500000>; i3c-scl-hz = <8300000>;
dfs-index = <0>; dfs-index = <0>;
i2c-scl-hz = <1000000>; i2c-scl-hz = <1000000>;
qcom,pm-ctrl-client; qcom,pm-ctrl-client;

View File

@@ -643,8 +643,8 @@
}; };
&i3c3 { &i3c3 {
se-clock-frequency = <100000000>; se-clock-frequency = <64000000>;
i3c-scl-hz = <12500000>; i3c-scl-hz = <8300000>;
dfs-index = <0>; dfs-index = <0>;
i2c-scl-hz = <1000000>; i2c-scl-hz = <1000000>;
qcom,pm-ctrl-client; qcom,pm-ctrl-client;

View File

@@ -585,8 +585,8 @@
}; };
&i3c3 { &i3c3 {
se-clock-frequency = <100000000>; se-clock-frequency = <64000000>;
i3c-scl-hz = <12500000>; i3c-scl-hz = <8300000>;
dfs-index = <0>; dfs-index = <0>;
i2c-scl-hz = <1000000>; i2c-scl-hz = <1000000>;
qcom,pm-ctrl-client; qcom,pm-ctrl-client;

View File

@@ -585,8 +585,8 @@
}; };
&i3c3 { &i3c3 {
se-clock-frequency = <100000000>; se-clock-frequency = <64000000>;
i3c-scl-hz = <12500000>; i3c-scl-hz = <8300000>;
dfs-index = <0>; dfs-index = <0>;
i2c-scl-hz = <1000000>; i2c-scl-hz = <1000000>;
qcom,pm-ctrl-client; qcom,pm-ctrl-client;