ARM: dts: msm: Reduce SE8 CLK to operate in lowSVS
To handle power regression at SE8 end reduce SCL clock, which makes the QUP clock domain to run in LowSVS instead of SVS. And the theoritical latency calculated for this change is minimal, around 0.3 msec for 200 xfers. CRs-Fixed: 3859750 Change-Id: I256e745a6edbdb356b297cf4d8909ca214840120 Signed-off-by: Lokesh Kumar Aakulu <quic_lkumar@quicinc.com>
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Camera Software Integration
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@@ -585,8 +585,8 @@
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&i3c3 {
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&i3c3 {
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se-clock-frequency = <100000000>;
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se-clock-frequency = <64000000>;
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i3c-scl-hz = <12500000>;
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i3c-scl-hz = <8300000>;
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dfs-index = <0>;
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dfs-index = <0>;
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i2c-scl-hz = <1000000>;
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i2c-scl-hz = <1000000>;
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qcom,pm-ctrl-client;
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qcom,pm-ctrl-client;
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@@ -643,8 +643,8 @@
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};
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};
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&i3c3 {
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&i3c3 {
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se-clock-frequency = <100000000>;
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se-clock-frequency = <64000000>;
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i3c-scl-hz = <12500000>;
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i3c-scl-hz = <8300000>;
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dfs-index = <0>;
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dfs-index = <0>;
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i2c-scl-hz = <1000000>;
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i2c-scl-hz = <1000000>;
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qcom,pm-ctrl-client;
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qcom,pm-ctrl-client;
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@@ -585,8 +585,8 @@
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};
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};
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&i3c3 {
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&i3c3 {
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se-clock-frequency = <100000000>;
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se-clock-frequency = <64000000>;
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i3c-scl-hz = <12500000>;
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i3c-scl-hz = <8300000>;
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dfs-index = <0>;
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dfs-index = <0>;
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i2c-scl-hz = <1000000>;
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i2c-scl-hz = <1000000>;
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qcom,pm-ctrl-client;
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qcom,pm-ctrl-client;
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@@ -585,8 +585,8 @@
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};
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};
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&i3c3 {
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&i3c3 {
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se-clock-frequency = <100000000>;
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se-clock-frequency = <64000000>;
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i3c-scl-hz = <12500000>;
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i3c-scl-hz = <8300000>;
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dfs-index = <0>;
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dfs-index = <0>;
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i2c-scl-hz = <1000000>;
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i2c-scl-hz = <1000000>;
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qcom,pm-ctrl-client;
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qcom,pm-ctrl-client;
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