ARM: dts: msm: Fix config values for QMP PHY

Fix values for QMP PHY configs according to updates from Hardware
Settings team which allow resolving Host mode enumeration issues for
SuperSpeed devices.

Change-Id: I4ad0ff3df8b8b8588679e93135aaac72c537015c
Signed-off-by: Ronak Vijay Raheja <quic_rraheja@quicinc.com>
This commit is contained in:
Ronak Vijay Raheja
2024-01-17 16:29:12 -08:00
parent 77314aed5c
commit 29471c0db8

View File

@@ -234,11 +234,11 @@
USB3_DP_QSERDES_RXA_SIGDET_ENABLES 0x0C
USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04
USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E
USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0x22
USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x12
USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0xDA
USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x3F
USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0xDB
USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0x3F
USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0xBF
USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0xFF
USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0xDF
USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0xED
USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0x19
USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x09
USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0x91
@@ -284,11 +284,11 @@
USB3_DP_QSERDES_RXB_SIGDET_ENABLES 0x0C
USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04
USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E
USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0x22
USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0x12
USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0xDA
USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x3F
USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xDB
USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0xBF
USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0xBF
USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0xBF
USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0xDF
USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xFD
USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0x19
USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x09
USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0x91
@@ -305,16 +305,16 @@
USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20
USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13
USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21
USB3_DP_PCS_RX_SIGDET_LVL 0x99
USB3_DP_PCS_RX_SIGDET_LVL 0x55
USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7
USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H 0x03
USB3_DP_PCS_CDR_RESET_TIME 0x0A
USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88
USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13
USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0xD4
USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x30
USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C
USB3_DP_PCS_EQ_CONFIG1 0x4B
USB3_DP_PCS_EQ_CONFIG5 0x10
USB3_DP_PCS_USB3_POWER_STATE_CONFIG1 0x68
USB3_DP_PCS_USB3_POWER_STATE_CONFIG1 0x7F
USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8
USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07
USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40