ARM: dts: msm: Fix config values for QMP PHY
Fix values for QMP PHY configs according to updates from Hardware Settings team which allow resolving Host mode enumeration issues for SuperSpeed devices. Change-Id: I4ad0ff3df8b8b8588679e93135aaac72c537015c Signed-off-by: Ronak Vijay Raheja <quic_rraheja@quicinc.com>
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@@ -234,11 +234,11 @@
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USB3_DP_QSERDES_RXA_SIGDET_ENABLES 0x0C
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USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04
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USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E
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USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0x22
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USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x12
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USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0xDA
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USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x3F
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USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0xDB
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USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0x3F
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USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0xBF
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USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0xFF
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USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0xDF
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USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0xED
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USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0x19
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USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x09
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USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0x91
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@@ -284,11 +284,11 @@
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USB3_DP_QSERDES_RXB_SIGDET_ENABLES 0x0C
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USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04
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USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E
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USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0x22
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USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0x12
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USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0xDA
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USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x3F
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USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xDB
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USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0xBF
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USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0xBF
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USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0xBF
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USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0xDF
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USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xFD
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USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0x19
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USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x09
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USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0x91
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@@ -305,16 +305,16 @@
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USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20
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USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13
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USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21
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USB3_DP_PCS_RX_SIGDET_LVL 0x99
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USB3_DP_PCS_RX_SIGDET_LVL 0x55
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USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7
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USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H 0x03
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USB3_DP_PCS_CDR_RESET_TIME 0x0A
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USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88
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USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13
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USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0xD4
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USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x30
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USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C
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USB3_DP_PCS_EQ_CONFIG1 0x4B
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USB3_DP_PCS_EQ_CONFIG5 0x10
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USB3_DP_PCS_USB3_POWER_STATE_CONFIG1 0x68
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USB3_DP_PCS_USB3_POWER_STATE_CONFIG1 0x7F
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USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8
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USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07
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USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40
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