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ARM: dts: msm: enable display support for vtdr panel on tuna CDP

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Enable display support for vtdr6130 panel on tuna CDP platform.

Change-Id: I38016bc3ab0aaf82c27ae96ba01bd914022d07f7
Signed-off-by: Abhinav Saurabh <quic_abhisaur@quicinc.com>
Signed-off-by: lnxdisplay <lnxdisplay@localhost>
This commit is contained in:
Abhinav Saurabh
2024-10-23 10:59:37 +05:30
committed by lnxdisplay
parent 14871db80d
commit 259a4eb1c2
4 changed files with 350 additions and 0 deletions
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189
display/tuna-sde-display-common.dtsi
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@@ -27,6 +27,12 @@
#include "dsi-panel-sim-dualmipi-video.dtsi"
#include "dsi-panel-sim-sec-hd-cmd.dtsi"
#include "dsi-panel-sim-video.dtsi"
#include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi"
#include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi"
#include "dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi"
#include "dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi"
#include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi"
#include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi"
#include "dsi-panel-ext-bridge-1080p.dtsi"
#include "tuna-sde-display-pinctrl.dtsi"
@@ -121,6 +127,189 @@
/* PHY TIMINGS REVISION YYG with reduced margins */
&dsi_vtdr6130_amoled_cmd {
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1";
qcom,dsi-dyn-clk-enable;
qcom,esd-check-enabled;
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
qcom,mdss-dsi-panel-status-value = <0x9c>;
qcom,mdss-dsi-panel-status-read-length = <1>;
qcom,mdss-dsi-panel-hdr-enabled;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
07 08 02 04 00 19 0c];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>;
};
timing@1 {
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
07 08 02 04 00 19 0c];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>;
};
timing@2 {
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
07 08 02 04 00 19 0c];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>;
};
timing@3 {
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
07 08 02 04 00 19 0c];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>;
};
};
};
&dsi_vtdr6130_amoled_video {
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1";
qcom,dsi-supported-dfps-list = <144 120 90 60>;
qcom,mdss-dsi-pan-enable-dynamic-fps;
qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
qcom,dsi-dyn-clk-enable;
qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp";
qcom,esd-check-enabled;
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
qcom,mdss-dsi-panel-status-value = <0x9c>;
qcom,mdss-dsi-panel-status-read-length = <1>;
qcom,mdss-dsi-panel-hdr-enabled;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
07 08 02 04 00 19 0c];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
qcom,dsi-dyn-clk-list = <847480320 844537680 841595040>;
};
};
};
&dsi_vtdr6130_amoled_120hz_cmd {
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
qcom,esd-check-enabled;
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
qcom,mdss-dsi-panel-status-value = <0x9c>;
qcom,mdss-dsi-panel-status-read-length = <1>;
qcom,mdss-dsi-panel-hdr-enabled;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07
06 07 02 04 00 16 0b];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
timing@1 {
qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07
06 07 02 04 00 16 0b];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
timing@2 {
qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07
06 07 02 04 00 16 0b];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_vtdr6130_amoled_120hz_video {
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
qcom,dsi-supported-dfps-list = <120 90 60>;
qcom,mdss-dsi-pan-enable-dynamic-fps;
qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
qcom,esd-check-enabled;
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
qcom,mdss-dsi-panel-status-value = <0x9c>;
qcom,mdss-dsi-panel-status-read-length = <1>;
qcom,mdss-dsi-panel-hdr-enabled;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07
06 07 02 04 00 16 0b];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_vtdr6130_amoled_qsync_144hz_cmd {
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
qcom,esd-check-enabled;
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
qcom,mdss-dsi-panel-status-value = <0x9c>;
qcom,mdss-dsi-panel-status-read-length = <1>;
qcom,mdss-dsi-panel-hdr-enabled;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
07 08 02 04 00 19 0c];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_vtdr6130_amoled_qsync_144hz_video {
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
qcom,esd-check-enabled;
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
qcom,mdss-dsi-panel-status-value = <0x9c>;
qcom,mdss-dsi-panel-status-read-length = <1>;
qcom,mdss-dsi-panel-hdr-enabled;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
07 08 02 04 00 19 0c];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_nt37801_amoled_cmd {
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1";