From 259a4eb1c2f999cff963a0a33a32f5592f8445e6 Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Wed, 23 Oct 2024 10:59:37 +0530 Subject: [PATCH] ARM: dts: msm: enable display support for vtdr panel on tuna CDP Enable display support for vtdr6130 panel on tuna CDP platform. Change-Id: I38016bc3ab0aaf82c27ae96ba01bd914022d07f7 Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- display/trustedvm-tuna-sde-display-cdp.dtsi | 62 +++++++ display/tuna-sde-display-cdp.dtsi | 70 ++++++++ display/tuna-sde-display-common.dtsi | 189 ++++++++++++++++++++ display/tuna-sde-display.dtsi | 29 +++ 4 files changed, 350 insertions(+) diff --git a/display/trustedvm-tuna-sde-display-cdp.dtsi b/display/trustedvm-tuna-sde-display-cdp.dtsi index bd14043b..06e55839 100644 --- a/display/trustedvm-tuna-sde-display-cdp.dtsi +++ b/display/trustedvm-tuna-sde-display-cdp.dtsi @@ -5,6 +5,38 @@ #include "trustedvm-tuna-sde-display.dtsi" +&dsi_vtdr6130_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + &dsi_nt37801_amoled_cmd { qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -124,6 +156,36 @@ qcom,platform-sec-reset-gpio = <&tlmm 126 0>; }; +&dsi_vtdr6130_amoled_120hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + &dsi_sim_cmd { qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; }; diff --git a/display/tuna-sde-display-cdp.dtsi b/display/tuna-sde-display-cdp.dtsi index c275438b..cbc2df0f 100644 --- a/display/tuna-sde-display-cdp.dtsi +++ b/display/tuna-sde-display-cdp.dtsi @@ -5,6 +5,43 @@ #include "tuna-sde-display.dtsi" +&dsi_vtdr6130_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + &dsi_nt37801_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; @@ -146,6 +183,39 @@ qcom,platform-sec-reset-gpio = <&tlmm 126 0>; }; +&dsi_vtdr6130_amoled_120hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + &dsi_sim_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/tuna-sde-display-common.dtsi b/display/tuna-sde-display-common.dtsi index 21e45a58..beb59396 100644 --- a/display/tuna-sde-display-common.dtsi +++ b/display/tuna-sde-display-common.dtsi @@ -27,6 +27,12 @@ #include "dsi-panel-sim-dualmipi-video.dtsi" #include "dsi-panel-sim-sec-hd-cmd.dtsi" #include "dsi-panel-sim-video.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi" +#include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi" +#include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi" #include "dsi-panel-ext-bridge-1080p.dtsi" #include "tuna-sde-display-pinctrl.dtsi" @@ -121,6 +127,189 @@ /* PHY TIMINGS REVISION YYG with reduced margins */ +&dsi_vtdr6130_amoled_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,dsi-dyn-clk-enable; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + + timing@3 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + }; +}; + +&dsi_vtdr6130_amoled_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,dsi-supported-dfps-list = <144 120 90 60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <847480320 844537680 841595040>; + }; + }; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-supported-dfps-list = <120 90 60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_nt37801_amoled_cmd { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; diff --git a/display/tuna-sde-display.dtsi b/display/tuna-sde-display.dtsi index cbcbda6f..a3568aac 100644 --- a/display/tuna-sde-display.dtsi +++ b/display/tuna-sde-display.dtsi @@ -86,6 +86,35 @@ connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2>; }; +&dsi_vtdr6130_amoled_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@1 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@2 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@3 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + }; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,ulps-enabled; +}; + &dsi_nt37801_amoled_cmd { qcom,mdss-dsi-display-timings { timing@0 {