samsung_sm8750/android_kernel_samsung_sm8750-devicetrees
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Merge 6de4b33143 on remote branch

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Change-Id: I3b4795cf42884b703303ff02bdcd8e2d86e81edc
This commit is contained in:
Linux Build Service Account
2024-04-16 15:47:11 -07:00
parent 5ed65a4e9d 6de4b33143
commit 23109442e4
13 changed files with 140 additions and 53 deletions
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1
Kbuild
View File

@@ -8,6 +8,7 @@ dtbo-y += sun-kiwi-bt.dtbo
dtbo-y += sun-peach-bt-v8.dtbo
dtbo-y += sun-kiwi-bt-v8.dtbo
dtbo-y += sun-wcn788x-v8.dtbo
dtbo-y += sunp-hdk-peach-bt-v8.dtbo
endif
always-y := $(dtb-y) $(dtbo-y)

4
sun-kiwi-bt-v8.dts
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@@ -12,6 +12,8 @@
/ {
model = "Qualcomm Technologies, Inc. Sun SoCs";
compatible = "qcom,sun", "qcom,sunp";
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
<0x100026a 0x10000>, <0x100026a 0x20000>,
<0x100027f 0x10000>, <0x100027f 0x20000>;
qcom,board-id = <0x60001 0>, <0x50008 0>, <0x20015 0>;
};

35
sun-kiwi-bt-v8.dtsi
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@@ -5,9 +5,10 @@
*/
#include <dt-bindings/interconnect/qcom,sun.h>
#include <dt-bindings/clock/qcom,rpmh.h>
&pm8550ve_f_gpios {
bt_uwb_en: bt_uwb_en {
bt_en: bt_en {
pins = "gpio3";
function = "normal";
input-disable;
@@ -15,6 +16,14 @@
bias-disable;
power-source = <1>;
};
bt_fmd_clk_en: bt_fmd_clk_en {
pins = "gpio6";
function = "normal";
input-enable;
output-disable;
bias-disable;
power-source = <1>;
};
};
&tlmm {
@@ -29,13 +38,19 @@
&soc {
bluetooth: bt_kiwi {
compatible = "qcom,kiwi";
pinctrl-names = "bt_uwb_en", "sw_ctrl";
pinctrl-0 = <&bt_uwb_en>;
nvmem-cells = <&fmd_set>;
nvmem-cell-names = "fmd_set";
clocks = <&rpmhcc RPMH_RF_CLK1>;
clock-names = "bt_rf_clk1";
pinctrl-names = "bt_en", "sw_ctrl", "bt_fmd_clk_en";
pinctrl-0 = <&bt_en>;
pinctrl-1 = <&cnss_bt_sw_ctrl>;
pinctrl-2 = <&bt_fmd_clk_en>;
/* List of GPIOs to be setup for interrupt wakeup capable*/
mpm_wake_set_gpios = <18>;
qcom,wl-reset-gpio = <&tlmm 16 0>; /* WL_EN */
qcom,bt-sw-ctrl-gpio = <&tlmm 18 0>; /* SW_CTRL */
qcom,bt-fmd-clk-gpio = <&pm8550ve_f_gpios 6 0>; /* FMD_CLK_CTRL */
qcom,bt-reset-gpio = <&pm8550ve_f_gpios 3 0>; /* BT_EN */
qcom,qmp = <&aoss_qmp>;
@@ -47,13 +62,13 @@
qcom,bt-vdd-rfa1-supply = <&S7I>; /* BT RFA1.2 LDO */
qcom,bt-vdd-rfa2-supply = <&S3G>; /* BT RFA1.8 LDO */
qcom,bt-vdd18-aon-config = <1800000 1800000 0 1>;
qcom,bt-vdd12-io-config = <1200000 1200000 0 1>;
qcom,bt-ant-ldo-config = <1800000 1800000 0 1>;
qcom,bt-vdd-aon-config = <916000 1100000 0 1>;
qcom,bt-vdd-rfaOp8-config = <916000 1100000 0 1>;
qcom,bt-vdd-rfa1-config = <1316000 1340000 0 1>;
qcom,bt-vdd-rfa2-config = <1864000 2000000 0 1>;
qcom,bt-vdd18-aon-config = <1800000 1800000 0 1 1>;
qcom,bt-vdd12-io-config = <1200000 1200000 0 1 1>;
qcom,bt-ant-ldo-config = <1800000 1800000 0 1 0>;
qcom,bt-vdd-aon-config = <916000 1100000 0 1 0>;
qcom,bt-vdd-rfaOp8-config = <916000 1100000 0 1 0>;
qcom,bt-vdd-rfa1-config = <1316000 1340000 0 1 0>;
qcom,bt-vdd-rfa2-config = <1864000 2000000 0 1 0>;
qcom,pdc_init_table =
"{class: wlan_pdc, ss: rf, res: s3g.v, upval: 1856}",

4
sun-kiwi-bt.dts
View File

@@ -12,6 +12,8 @@
/ {
model = "Qualcomm Technologies, Inc. Sun SoCs";
compatible = "qcom,sun", "qcom,sunp", "qcom,sun-mtp", "qcom,sun-cdp";
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
<0x100026a 0x10000>, <0x100026a 0x20000>,
<0x100027f 0x10000>, <0x100027f 0x20000>;
qcom,board-id = <0x20001 0>, <0x20008 0>, <0x40015 0>;
};

14
sun-kiwi-bt.dtsi
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@@ -47,13 +47,13 @@
qcom,bt-vdd-rfa1-supply = <&S7I>; /* BT RFA1.2 LDO */
qcom,bt-vdd-rfa2-supply = <&S3G>; /* BT RFA1.8 LDO */
qcom,bt-vdd18-aon-config = <1800000 1800000 0 1>;
qcom,bt-vdd12-io-config = <1200000 1200000 0 1>;
qcom,bt-ant-ldo-config = <1800000 1800000 0 1>;
qcom,bt-vdd-aon-config = <916000 1100000 0 1>;
qcom,bt-vdd-rfaOp8-config = <916000 1100000 0 1>;
qcom,bt-vdd-rfa1-config = <1316000 1340000 0 1>;
qcom,bt-vdd-rfa2-config = <1864000 2000000 0 1>;
qcom,bt-vdd18-aon-config = <1800000 1800000 0 1 0>;
qcom,bt-vdd12-io-config = <1200000 1200000 0 1 0>;
qcom,bt-ant-ldo-config = <1800000 1800000 0 1 0>;
qcom,bt-vdd-aon-config = <916000 1100000 0 1 0>;
qcom,bt-vdd-rfaOp8-config = <916000 1100000 0 1 0>;
qcom,bt-vdd-rfa1-config = <1316000 1340000 0 1 0>;
qcom,bt-vdd-rfa2-config = <1864000 2000000 0 1 0>;
qcom,pdc_init_table =
"{class: wlan_pdc, ss: rf, res: s3g.v, upval: 1856}",

6
sun-peach-bt-v8.dts
View File

@@ -13,7 +13,9 @@
model = "Qualcomm Technologies, Inc. Sun SoCs";
compatible = "qcom,sun", "qcom,sunp";
qcom,msm-id = <618 0x10000>, <618 0x20000>,
<639 0x10000>, <639 0x20000>;
<639 0x10000>, <639 0x20000>,
<0x100026a 0x10000>, <0x100026a 0x20000>,
<0x100027f 0x10000>, <0x100027f 0x20000>;
qcom,board-id = <0x50001 0>, <0x40008 0>, <0x3000B 0>, <0x2000B 0>,
<0x30015 0>, <0x10021 0>, <0x60008 0>, <0x40108 0>;
<0x30015 0>, <0x10021 0>, <0x60008 0>, <0x40108 0>;
};

37
sun-peach-bt-v8.dtsi
View File

@@ -5,6 +5,7 @@
*/
#include <dt-bindings/interconnect/qcom,sun.h>
#include <dt-bindings/clock/qcom,rpmh.h>
&pm8550ve_f_gpios {
bt_uwb_en: bt_uwb_en {
@@ -15,6 +16,14 @@
bias-disable;
power-source = <1>;
};
bt_fmd_clk_en: bt_fmd_clk_en {
pins = "gpio6";
function = "normal";
input-enable;
output-disable;
bias-disable;
power-source = <1>;
};
};
&tlmm {
@@ -29,14 +38,20 @@
&soc {
bluetooth: bt_peach {
compatible = "qcom,peach-bt";
nvmem-cells = <&fmd_set>;
nvmem-cell-names = "fmd_set";
clocks = <&rpmhcc RPMH_RF_CLK1>;
clock-names = "bt_rf_clk1";
qcom,peach-bt;
pinctrl-names = "bt_uwb_en", "sw_ctrl";
pinctrl-names = "bt_uwb_en", "sw_ctrl", "bt_fmd_clk_en";
pinctrl-0 = <&bt_uwb_en>;
pinctrl-1 = <&cnss_bt_sw_ctrl>;
pinctrl-2 = <&bt_fmd_clk_en>;
/* List of GPIOs to be setup for interrupt wakeup capable*/
mpm_wake_set_gpios = <18>;
mpm_wake_set_gpios = <18 9>;
qcom,wl-reset-gpio = <&tlmm 16 0>; /* WL_EN */
qcom,bt-sw-ctrl-gpio = <&tlmm 18 0>; /* SW_CTRL */
qcom,bt-fmd-clk-gpio = <&pm8550ve_f_gpios 6 0>; /* FMD_CLK_CTRL */
qcom,bt-reset-gpio = <&pm8550ve_f_gpios 3 0>; /* BT_EN */
qcom,qmp = <&aoss_qmp>;
@@ -49,14 +64,14 @@
qcom,bt-vdd-rfa1p8-supply = <&S3G>; /* RFA_1P8 */
qcom,bt-vdd-rfa1p25-supply = <&S7I>; /* RFA_1P2 */
qcom,bt-vdd18-aon-config = <1800000 1800000 0 1>;
qcom,bt-vdd12-io-config = <1200000 1200000 0 1>;
qcom,bt-ant-ldo-config = <1800000 1860000 0 1>;
qcom,bt-vdd-aon-config = <876000 1000000 0 1>;
qcom,bt-vdd-dig-config = <876000 1000000 0 1>;
qcom,bt-vdd-rfa0p75-config = <876000 1000000 0 1>;
qcom,bt-vdd-rfa1p8-config = <1860000 2000000 0 1>;
qcom,bt-vdd-rfa1p25-config = <1312000 1340000 0 1>;
qcom,bt-vdd18-aon-config = <1800000 1800000 0 1 1>;
qcom,bt-vdd12-io-config = <1200000 1200000 0 1 1>;
qcom,bt-ant-ldo-config = <1800000 1860000 0 1 0>;
qcom,bt-vdd-aon-config = <876000 1000000 0 1 0>;
qcom,bt-vdd-dig-config = <876000 1000000 0 1 0>;
qcom,bt-vdd-rfa0p75-config = <876000 1000000 0 1 0>;
qcom,bt-vdd-rfa1p8-config = <1860000 2000000 0 1 0>;
qcom,bt-vdd-rfa1p25-config = <1312000 1340000 0 1 0>;
qcom,pdc_init_table =
"{class: wlan_pdc, ss: rf, res: s5f.m, enable: 1}",
@@ -76,7 +91,7 @@
// FM changes
&qupv3_se5_i2c {
status = "ok";
nq@64 {
fm_rtc6226: nq@64 {
compatible = "rtc6226";
reg = <0x64>;
fmint-gpio = <&tlmm 84 0>;

6
sun-peach-bt.dts
View File

@@ -13,6 +13,8 @@
model = "Qualcomm Technologies, Inc. Sun SoCs";
compatible = "qcom,sun", "qcom,sunp";
qcom,msm-id = <618 0x10000>, <618 0x20000>,
<639 0x10000>, <639 0x20000>;
qcom,board-id = <1 0>, <8 0>, <0x1000B 0>, <0x15 0>, <0x60008 0>, <0x10108 0>;
<639 0x10000>, <639 0x20000>,
<0x100026a 0x10000>, <0x100026a 0x20000>,
<0x100027f 0x10000>, <0x100027f 0x20000>;
qcom,board-id = <1 0>, <8 0>, <0x1000B 0>, <0x15 0>, <0x108 0>;
};

16
sun-peach-bt.dtsi
View File

@@ -49,14 +49,14 @@
qcom,bt-vdd-rfa1p8-supply = <&S3G>; /* RFA_1P8 */
qcom,bt-vdd-rfa1p25-supply = <&S7I>; /* RFA_1P2 */
qcom,bt-vdd18-aon-config = <1800000 1800000 0 1>;
qcom,bt-vdd12-io-config = <1200000 1200000 0 1>;
qcom,bt-ant-ldo-config = <1800000 1860000 0 1>;
qcom,bt-vdd-aon-config = <876000 1000000 0 1>;
qcom,bt-vdd-dig-config = <876000 1000000 0 1>;
qcom,bt-vdd-rfa0p75-config = <876000 1000000 0 1>;
qcom,bt-vdd-rfa1p8-config = <1860000 2000000 0 1>;
qcom,bt-vdd-rfa1p25-config = <1312000 1340000 0 1>;
qcom,bt-vdd18-aon-config = <1800000 1800000 0 1 0>;
qcom,bt-vdd12-io-config = <1200000 1200000 0 1 0>;
qcom,bt-ant-ldo-config = <1800000 1860000 0 1 0>;
qcom,bt-vdd-aon-config = <876000 1000000 0 1 0>;
qcom,bt-vdd-dig-config = <876000 1000000 0 1 0>;
qcom,bt-vdd-rfa0p75-config = <876000 1000000 0 1 0>;
qcom,bt-vdd-rfa1p8-config = <1860000 2000000 0 1 0>;
qcom,bt-vdd-rfa1p25-config = <1312000 1340000 0 1 0>;
qcom,pdc_init_table =
"{class: wlan_pdc, ss: rf, res: s4j.m, enable: 1}",

4
sun-wcn788x-v8.dts
View File

@@ -12,6 +12,8 @@
/ {
model = "Qualcomm Technologies, Inc. Sun SoCs";
compatible = "qcom,sun", "qcom,sunp";
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
<0x100026a 0x10000>, <0x100026a 0x20000>,
<0x100027f 0x10000>, <0x100027f 0x20000>;
qcom,board-id = <0x30008 0>, <0x40001 0>;
};

35
sun-wcn788x-v8.dtsi
View File

@@ -5,6 +5,7 @@
*/
#include <dt-bindings/interconnect/qcom,sun.h>
#include <dt-bindings/clock/qcom,rpmh.h>
&pm8550ve_f_gpios {
bt_en: bt_en {
@@ -15,6 +16,14 @@
bias-disable;
power-source = <1>;
};
bt_fmd_clk_en: bt_fmd_clk_en {
pins = "gpio6";
function = "normal";
input-enable;
output-disable;
bias-disable;
power-source = <1>;
};
};
&tlmm {
@@ -29,14 +38,20 @@
&soc {
bluetooth: wcn788x {
compatible = "qcom,wcn788x";
nvmem-cells = <&fmd_set>;
nvmem-cell-names = "fmd_set";
clocks = <&rpmhcc RPMH_RF_CLK1>;
clock-names = "bt_rf_clk1";
qcom,wcn788x;
pinctrl-names = "bt_en", "sw_ctrl";
pinctrl-names = "bt_en", "sw_ctrl", "bt_fmd_clk_en";
pinctrl-0 = <&bt_en>;
pinctrl-1 = <&cnss_bt_sw_ctrl>;
pinctrl-2 = <&bt_fmd_clk_en>;
/* List of GPIOs to be setup for interrupt wakeup capable*/
mpm_wake_set_gpios = <18>;
mpm_wake_set_gpios = <18 9>;
qcom,wl-reset-gpio = <&tlmm 16 0>; /* WL_EN */
qcom,bt-sw-ctrl-gpio = <&tlmm 18 0>; /* SW_CTRL */
qcom,bt-fmd-clk-gpio = <&pm8550ve_f_gpios 6 0>; /* FMD_CLK_CTRL */
qcom,bt-reset-gpio = <&pm8550ve_f_gpios 3 0>; /* BT_EN */
qcom,qmp = <&aoss_qmp>;
@@ -49,14 +64,14 @@
qcom,bt-vdd-rfa1p8-supply = <&S3G>; /* RFA_1P8 */
qcom,bt-vdd-rfa1p25-supply = <&S7I>; /* RFA_1P2 */
qcom,bt-vdd18-aon-config = <1800000 1800000 0 1>;
qcom,bt-vdd12-io-config = <1200000 1200000 0 1>;
qcom,bt-ant-ldo-config = <1800000 1860000 0 1>;
qcom,bt-vdd-aon-config = <876000 1000000 0 1>;
qcom,bt-vdd-dig-config = <876000 1000000 0 1>;
qcom,bt-vdd-rfa0p75-config = <876000 1000000 0 1>;
qcom,bt-vdd-rfa1p8-config = <1860000 2000000 0 1>;
qcom,bt-vdd-rfa1p25-config = <1312000 1340000 0 1>;
qcom,bt-vdd18-aon-config = <1800000 1800000 0 1 1>;
qcom,bt-vdd12-io-config = <1200000 1200000 0 1 1>;
qcom,bt-ant-ldo-config = <1800000 1860000 0 1 0>;
qcom,bt-vdd-aon-config = <876000 1000000 0 1 0>;
qcom,bt-vdd-dig-config = <876000 1000000 0 1 0>;
qcom,bt-vdd-rfa0p75-config = <876000 1000000 0 1 0>;
qcom,bt-vdd-rfa1p8-config = <1860000 2000000 0 1 0>;
qcom,bt-vdd-rfa1p25-config = <1312000 1340000 0 1 0>;
qcom,pdc_init_table =
"{class: wlan_pdc, ss: rf, res: s5f.m, enable: 1}",

17
sunp-hdk-peach-bt-v8.dts Normal file
View File

@@ -0,0 +1,17 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "sunp-hdk-peach-bt-v8.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Sun SoCs HDK";
compatible = "qcom,sunp-hdk", "qcom,sunp", "qcom,hdk";
qcom,msm-id = <639 0x10000>, <639 0x20000>, <618 0x10000>, <618 0x20000>;
qcom,board-id = <0x1001f 0>;
};

14
sunp-hdk-peach-bt-v8.dtsi Normal file
View File

@@ -0,0 +1,14 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "sun-peach-bt-v8.dtsi"
/delete-node/ &fm_rtc6226;
&bluetooth {
/delete-property/ qcom,bt-ant-ldo-supply;
/delete-property/ qcom,bt-ant-ldo-config;
};