samsung_sm8750/android_kernel_samsung_sm8750-devicetrees
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

ARM: dts: msm: move esync RCG to SDE DSI node

Browse Source 
Driver needs to set esync clock's parent under a gating condition,
which is not available at the point where the clocks under MDSS DSI
node are parsed. Moves the esync RCG clock to SDE DSI instead.

Change-Id: I01e0fedbc7620425d237024663da944e2f7ae9cf
Signed-off-by: Kirill Shpin <quic_kshpin@quicinc.com>
This commit is contained in:
Kirill Shpin
2024-07-22 14:35:35 -07:00
parent ca2fc6dff7
commit 22f51de923
2 changed files with 22 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
display/sun-sde-display.dtsi
View File

@@ -92,10 +92,17 @@
* MDP clock nodes, no actual vote shall be added and this * MDP clock nodes, no actual vote shall be added and this
* change is done just to satisfy sync state requirements. * change is done just to satisfy sync state requirements.
*/ */
<&dispcc DISP_CC_MDSS_MDP_CLK>; <&dispcc DISP_CC_MDSS_MDP_CLK>,
/*
* The esync clk RCG is only necessary here to set its parent
* to the pll dsi clk, which also needs to be available at the
* point that its known whether the clock will be used. After
* updating the parent, this clock handle is no longer needed.
*/
<&dispcc DISP_CC_ESYNC0_CLK_SRC>;
clock-names = "pll_byte_clk0", "pll_dsi_clk0", clock-names = "pll_byte_clk0", "pll_dsi_clk0",
"pll_byte_clk1", "pll_dsi_clk1", "pll_byte_clk1", "pll_dsi_clk1",
"mdp_core_clk"; "mdp_core_clk", "esync_clk_rcg";
vddio-supply = <&L12B>; vddio-supply = <&L12B>;
vci-supply = <&L13B>; vci-supply = <&L13B>;
vdd-supply = <&L11B>; vdd-supply = <&L11B>;
@@ -121,10 +128,17 @@
* MDP clock nodes, no actual vote shall be added and this * MDP clock nodes, no actual vote shall be added and this
* change is done just to satisfy sync state requirements. * change is done just to satisfy sync state requirements.
*/ */
<&dispcc DISP_CC_MDSS_MDP_CLK>; <&dispcc DISP_CC_MDSS_MDP_CLK>,
/*
* The esync clk RCG is only necessary here to set its parent
* to the pll dsi clk, which also needs to be available at the
* point that its known whether the clock will be used. After
* updating the parent, this clock handle is no longer needed.
*/
<&dispcc DISP_CC_ESYNC1_CLK_SRC>;
clock-names = "pll_byte_clk0", "pll_dsi_clk0", clock-names = "pll_byte_clk0", "pll_dsi_clk0",
"pll_byte_clk1", "pll_dsi_clk1", "pll_byte_clk1", "pll_dsi_clk1",
"mdp_core_clk"; "mdp_core_clk", "esync_clk_rcg";
vddio-supply = <&L12B>; vddio-supply = <&L12B>;
vci-supply = <&L13B>; vci-supply = <&L13B>;
vdd-supply = <&L11B>; vdd-supply = <&L11B>;

12
display/sun-sde.dtsi
View File

@@ -313,15 +313,13 @@
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK>, <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
<&mdss_dsi_phy0 1>,
<&dispcc DISP_CC_ESYNC0_CLK>, <&dispcc DISP_CC_ESYNC0_CLK>,
<&dispcc DISP_CC_ESYNC0_CLK_SRC>,
<&dispcc DISP_CC_OSC_CLK>, <&dispcc DISP_CC_OSC_CLK>,
<&dispcc DISP_CC_MDSS_ESC0_CLK>, <&dispcc DISP_CC_MDSS_ESC0_CLK>,
<&rpmhcc RPMH_CXO_CLK>; <&rpmhcc RPMH_CXO_CLK>;
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
"pixel_clk", "pixel_clk_rcg", "pll_dsi_clk", "pixel_clk", "pixel_clk_rcg", "esync_clk", "osc_clk",
"esync_clk", "esync_clk_rcg", "osc_clk", "esc_clk", "xo"; "esc_clk", "xo";
}; };
&mdss_dsi1 { &mdss_dsi1 {
@@ -332,15 +330,13 @@
<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
<&dispcc DISP_CC_MDSS_PCLK1_CLK>, <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>,
<&mdss_dsi_phy1 1>,
<&dispcc DISP_CC_ESYNC1_CLK>, <&dispcc DISP_CC_ESYNC1_CLK>,
<&dispcc DISP_CC_ESYNC1_CLK_SRC>,
<&dispcc DISP_CC_OSC_CLK>, <&dispcc DISP_CC_OSC_CLK>,
<&dispcc DISP_CC_MDSS_ESC1_CLK>, <&dispcc DISP_CC_MDSS_ESC1_CLK>,
<&rpmhcc RPMH_CXO_CLK>; <&rpmhcc RPMH_CXO_CLK>;
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
"pixel_clk", "pixel_clk_rcg", "pll_dsi_clk", "pixel_clk", "pixel_clk_rcg", "esync_clk", "osc_clk",
"esync_clk", "esync_clk_rcg", "osc_clk", "esc_clk", "xo"; "esc_clk", "xo";
}; };
&mdss_dsi_phy0 { &mdss_dsi_phy0 {