From 22f51de9232416f67ab322ed80c464c41d37663e Mon Sep 17 00:00:00 2001 From: Kirill Shpin Date: Mon, 22 Jul 2024 14:35:35 -0700 Subject: [PATCH] ARM: dts: msm: move esync RCG to SDE DSI node Driver needs to set esync clock's parent under a gating condition, which is not available at the point where the clocks under MDSS DSI node are parsed. Moves the esync RCG clock to SDE DSI instead. Change-Id: I01e0fedbc7620425d237024663da944e2f7ae9cf Signed-off-by: Kirill Shpin --- display/sun-sde-display.dtsi | 22 ++++++++++++++++++---- display/sun-sde.dtsi | 12 ++++-------- 2 files changed, 22 insertions(+), 12 deletions(-) diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index c779d0fd..03774135 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -92,10 +92,17 @@ * MDP clock nodes, no actual vote shall be added and this * change is done just to satisfy sync state requirements. */ - <&dispcc DISP_CC_MDSS_MDP_CLK>; + <&dispcc DISP_CC_MDSS_MDP_CLK>, + /* + * The esync clk RCG is only necessary here to set its parent + * to the pll dsi clk, which also needs to be available at the + * point that its known whether the clock will be used. After + * updating the parent, this clock handle is no longer needed. + */ + <&dispcc DISP_CC_ESYNC0_CLK_SRC>; clock-names = "pll_byte_clk0", "pll_dsi_clk0", "pll_byte_clk1", "pll_dsi_clk1", - "mdp_core_clk"; + "mdp_core_clk", "esync_clk_rcg"; vddio-supply = <&L12B>; vci-supply = <&L13B>; vdd-supply = <&L11B>; @@ -121,10 +128,17 @@ * MDP clock nodes, no actual vote shall be added and this * change is done just to satisfy sync state requirements. */ - <&dispcc DISP_CC_MDSS_MDP_CLK>; + <&dispcc DISP_CC_MDSS_MDP_CLK>, + /* + * The esync clk RCG is only necessary here to set its parent + * to the pll dsi clk, which also needs to be available at the + * point that its known whether the clock will be used. After + * updating the parent, this clock handle is no longer needed. + */ + <&dispcc DISP_CC_ESYNC1_CLK_SRC>; clock-names = "pll_byte_clk0", "pll_dsi_clk0", "pll_byte_clk1", "pll_dsi_clk1", - "mdp_core_clk"; + "mdp_core_clk", "esync_clk_rcg"; vddio-supply = <&L12B>; vci-supply = <&L13B>; vdd-supply = <&L11B>; diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index f0d8064c..3c3f1462 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -313,15 +313,13 @@ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, <&dispcc DISP_CC_MDSS_PCLK0_CLK>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, - <&mdss_dsi_phy0 1>, <&dispcc DISP_CC_ESYNC0_CLK>, - <&dispcc DISP_CC_ESYNC0_CLK_SRC>, <&dispcc DISP_CC_OSC_CLK>, <&dispcc DISP_CC_MDSS_ESC0_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "pll_dsi_clk", - "esync_clk", "esync_clk_rcg", "osc_clk", "esc_clk", "xo"; + "pixel_clk", "pixel_clk_rcg", "esync_clk", "osc_clk", + "esc_clk", "xo"; }; &mdss_dsi1 { @@ -332,15 +330,13 @@ <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, <&dispcc DISP_CC_MDSS_PCLK1_CLK>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, - <&mdss_dsi_phy1 1>, <&dispcc DISP_CC_ESYNC1_CLK>, - <&dispcc DISP_CC_ESYNC1_CLK_SRC>, <&dispcc DISP_CC_OSC_CLK>, <&dispcc DISP_CC_MDSS_ESC1_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "pll_dsi_clk", - "esync_clk", "esync_clk_rcg", "osc_clk", "esc_clk", "xo"; + "pixel_clk", "pixel_clk_rcg", "esync_clk", "osc_clk", + "esc_clk", "xo"; }; &mdss_dsi_phy0 {