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ARM: dts: msm: move esync RCG to SDE DSI node

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Driver needs to set esync clock's parent under a gating condition,
which is not available at the point where the clocks under MDSS DSI
node are parsed. Moves the esync RCG clock to SDE DSI instead.

Change-Id: I01e0fedbc7620425d237024663da944e2f7ae9cf
Signed-off-by: Kirill Shpin <quic_kshpin@quicinc.com>
This commit is contained in:
Kirill Shpin
2024-07-22 14:35:35 -07:00
parent ca2fc6dff7
commit 22f51de923
2 changed files with 22 additions and 12 deletions
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22
display/sun-sde-display.dtsi
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@@ -92,10 +92,17 @@
* MDP clock nodes, no actual vote shall be added and this
* change is done just to satisfy sync state requirements.
*/
<&dispcc DISP_CC_MDSS_MDP_CLK>;
<&dispcc DISP_CC_MDSS_MDP_CLK>,
/*
* The esync clk RCG is only necessary here to set its parent
* to the pll dsi clk, which also needs to be available at the
* point that its known whether the clock will be used. After
* updating the parent, this clock handle is no longer needed.
*/
<&dispcc DISP_CC_ESYNC0_CLK_SRC>;
clock-names = "pll_byte_clk0", "pll_dsi_clk0",
"pll_byte_clk1", "pll_dsi_clk1",
"mdp_core_clk";
"mdp_core_clk", "esync_clk_rcg";
vddio-supply = <&L12B>;
vci-supply = <&L13B>;
vdd-supply = <&L11B>;
@@ -121,10 +128,17 @@
* MDP clock nodes, no actual vote shall be added and this
* change is done just to satisfy sync state requirements.
*/
<&dispcc DISP_CC_MDSS_MDP_CLK>;
<&dispcc DISP_CC_MDSS_MDP_CLK>,
/*
* The esync clk RCG is only necessary here to set its parent
* to the pll dsi clk, which also needs to be available at the
* point that its known whether the clock will be used. After
* updating the parent, this clock handle is no longer needed.
*/
<&dispcc DISP_CC_ESYNC1_CLK_SRC>;
clock-names = "pll_byte_clk0", "pll_dsi_clk0",
"pll_byte_clk1", "pll_dsi_clk1",
"mdp_core_clk";
"mdp_core_clk", "esync_clk_rcg";
vddio-supply = <&L12B>;
vci-supply = <&L13B>;
vdd-supply = <&L11B>;