ARM: dts: msm: Use "iommu-addresses" property for parrot dwc3
Use upstream compatible DT property "iommu-addresses" instead of "qcom,iommu-dma-addr-pool" for dwc3 which describes the addresses that dwc3 cannot use. Extend the address and size cells to ensure that IOMMU returns a 32 bit address, in order to define a region that will block 0xf0000000--0xffffffffffffffff. Change-Id: Idb5640a5a63bfa50c7fac61e785012df733e82c6 Signed-off-by: Saranya R <quic_sarar@quicinc.com>
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@@ -12,8 +12,8 @@
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reg = <0xa600000 0x100000>;
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reg = <0xa600000 0x100000>;
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reg-names = "core_base";
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reg-names = "core_base";
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#address-cells = <1>;
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#address-cells = <2>;
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#size-cells = <1>;
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#size-cells = <2>;
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ranges;
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ranges;
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USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
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USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
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@@ -53,13 +53,13 @@
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<&aggre1_noc MASTER_USB3_0 &cnoc2 SLAVE_IPA_CFG>,
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<&aggre1_noc MASTER_USB3_0 &cnoc2 SLAVE_IPA_CFG>,
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<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_USB3_0>;
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<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_USB3_0>;
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dwc3@a600000 {
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dwc3_0: dwc3@a600000 {
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compatible = "snps,dwc3";
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compatible = "snps,dwc3";
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reg = <0xa600000 0xd800>;
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reg = <0x0 0xa600000 0x0 0xd800>;
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iommus = <&apps_smmu 0x80 0x0>;
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iommus = <&apps_smmu 0x80 0x0>;
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qcom,iommu-dma = "atomic";
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qcom,iommu-dma = "atomic";
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qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
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memory-region = <&dwc3_mem_region>;
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dma-coherent;
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dma-coherent;
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interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
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@@ -79,6 +79,12 @@
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};
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};
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dwc3_mem_region: dwc3_mem_region {
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iommu-addresses = <&dwc3_0 0x0 0x0 0x0 0x90000000>,
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<&dwc3_0 0x0 0xf0000000 0xffffffff 0x10000000>;
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};
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/* USB port related High Speed PHY */
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/* USB port related High Speed PHY */
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usb2_phy0: hsphy@88e3000 {
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usb2_phy0: hsphy@88e3000 {
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compatible = "qcom,usb-hsphy-snps-femto";
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compatible = "qcom,usb-hsphy-snps-femto";
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