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Merge "ARM: dts: qcom: Set correct parents for the PHY symbol mux clks"

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QCTECMDR Service
2025-03-26 04:38:08 -07:00
committed by Gerrit - the friendly Code Review server
parent 24dfd1761e 3db9245b08
commit 1ee1b80772
1 changed files with 4 additions and 4 deletions
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qcom/sun.dtsi
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@@ -2333,15 +2333,15 @@
"ref_aux_clk", "qref_clk", "ref_aux_clk", "qref_clk",
"rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk", "rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk",
"rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk"; "rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk";
clocks = <&rpmhcc RPMH_CXO_PAD_CLK>, clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
<&tcsrcc TCSR_UFS_CLKREF_EN>, <&tcsrcc TCSR_UFS_CLKREF_EN>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC>, <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, <&ufs_phy_rx_symbol_0_clk>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, <&ufs_phy_rx_symbol_1_clk>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>; <&ufs_phy_tx_symbol_0_clk>;
resets = <&ufshc_mem 0>; resets = <&ufshc_mem 0>;
status = "disabled"; status = "disabled";
}; };