From 3db9245b080c6c9bf2555d2cec3389c66763ef30 Mon Sep 17 00:00:00 2001 From: "Bao D. Nguyen" Date: Wed, 12 Mar 2025 02:12:08 -0700 Subject: [PATCH] ARM: dts: qcom: Set correct parents for the PHY symbol mux clks According to the Hardware Programming Guide, when going into hibern8, select XO clock (RPMH_CXO_CLK) clock as the parent of the phy symbol mux clocks (GCC_UFS_PHY_RX/TX_SYMBOL_0/1_CLK_SRC). When exiting the hibern8, select the phy symbol clocks (UFS_PHY_RX/TX_SYMBOL_0/1_CLK) as the parent of the phy symbol mux clocks. Change-Id: I624f98c39b7548dc2a9a5207d82600bb69ac41d5 Signed-off-by: Bao D. Nguyen --- qcom/sun.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index d99fb590..e37ae33b 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -2333,15 +2333,15 @@ "ref_aux_clk", "qref_clk", "rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk", "rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk"; - clocks = <&rpmhcc RPMH_CXO_PAD_CLK>, + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, <&tcsrcc TCSR_UFS_CLKREF_EN>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC>, <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, - <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>; + <&ufs_phy_rx_symbol_0_clk>, + <&ufs_phy_rx_symbol_1_clk>, + <&ufs_phy_tx_symbol_0_clk>; resets = <&ufshc_mem 0>; status = "disabled"; };