ARM: dts: msm: Add initial device tree for ravelin
Add initial device tree support for ravelin target.
This is a snapshot of dtsi files as of KP.1.0
'commit <370d8eab7cc6> ("Merge "ARM: dts: qcom:
Disable cnss-kiwi SOL on anorak platform"")'.
Modified as per compilation and bootup.
Change-Id: Icb9a6e67879c68dbf894d1713fa2837882b9f00c
Signed-off-by: Swetha Chikkaboraiah <quic_schikk@quicinc.com>
This commit is contained in:
Swetha Chikkaboraiah
528
qcom/ravelin-qupv3.dtsi
Normal file
528
qcom/ravelin-qupv3.dtsi
Normal file
@@ -0,0 +1,528 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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&soc {
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/* QUPv3 SE Instances
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* Qup0 0: SE 0
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* Qup0 1: SE 1
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* Qup0 2: SE 2
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* Qup0 3: SE 3
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* Qup0 4: SE 4
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* Qup1 0: SE 5
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* Qup1 1: SE 6
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* Qup1 2: SE 7
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* Qup1 3: SE 8
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* Qup1 4: SE 9
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*/
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/* GPI Instance */
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gpi_dma0: qcom,gpi-dma@900000 {
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compatible = "qcom,gpi-dma";
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#dma-cells = <5>;
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reg = <0x900000 0x60000>;
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reg-names = "gpi-top";
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iommus = <&apps_smmu 0x176 0x0>;
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qcom,max-num-gpii = <12>;
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interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
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qcom,static-gpii-mask = <0x1>;
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qcom,gpii-mask = <0x3e>;
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qcom,ev-factor = <2>;
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qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
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dma-coherent;
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qcom,gpi-ee-offset = <0x10000>;
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status = "ok";
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};
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/* QUPv3_0 wrapper instance */
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qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x9c0000 0x2000>;
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#address-cells = <1>;
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#size-cells = <1>;
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clock-names = "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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iommus = <&apps_smmu 0x163 0x0>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
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qcom,iommu-geometry = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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dma-coherent;
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status = "ok";
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/* HS UART Instance */
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qupv3_se2_4uart: qcom,qup_uart@988000 {
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compatible = "qcom,msm-geni-serial-hs";
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reg = <0x988000 0x4000>;
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reg-names = "se_phys";
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interrupts-extended = <&intc GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
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<&tlmm 17 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
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<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
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<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "active", "sleep", "shutdown";
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pinctrl-0 = <&qupv3_se2_default_cts>, <&qupv3_se2_default_rts>,
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<&qupv3_se2_default_tx>, <&qupv3_se2_default_rx>;
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pinctrl-1 = <&qupv3_se2_cts>, <&qupv3_se2_rts>,
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<&qupv3_se2_tx>, <&qupv3_se2_rx>;
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pinctrl-2 = <&qupv3_se2_cts>, <&qupv3_se2_rts>,
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<&qupv3_se2_tx>, <&qupv3_se2_default_rx>;
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pinctrl-3 = <&qupv3_se2_default_cts>, <&qupv3_se2_default_rts>,
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<&qupv3_se2_default_tx>, <&qupv3_se2_default_rx>;
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qcom,wakeup-byte = <0xFD>;
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status = "disabled";
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};
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/* HST Debug UART Instance */
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qupv3_se0_2uart: qcom,qup_uart@980000 {
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compatible = "qcom,geni-debug-uart";
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reg = <0x980000 0x4000>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
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interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
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interconnects =
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<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
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<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
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<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se0_2uart_tx_active>, <&qupv3_se0_2uart_rx_active>;
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pinctrl-1 = <&qupv3_se0_2uart_sleep>;
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status = "disabled";
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};
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qupv3_se0_i2c: i2c@980000 {
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compatible = "qcom,i2c-geni";
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reg = <0x980000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
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interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
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interconnects =
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<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
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<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
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<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>;
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pinctrl-1 = <&qupv3_se0_i2c_sleep>;
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dmas = <&gpi_dma0 0 0 3 64 0>,
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<&gpi_dma0 1 0 3 64 0>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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qupv3_se1_i2c: i2c@984000 {
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compatible = "qcom,i2c-geni";
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reg = <0x984000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
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interconnects =
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<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
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<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
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<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
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interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se1_i2c_sda_active>, <&qupv3_se1_i2c_scl_active>;
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pinctrl-1 = <&qupv3_se1_i2c_sleep>;
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dmas = <&gpi_dma0 0 1 3 64 2>,
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<&gpi_dma0 1 1 3 64 2>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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qupv3_se1_spi: spi@984000 {
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compatible = "qcom,spi-geni";
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reg = <0x984000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
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interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
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interconnects =
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<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
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<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
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<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se1_spi_mosi_active>, <&qupv3_se1_spi_miso_active>,
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<&qupv3_se1_spi_clk_active>, <&qupv3_se1_spi_cs_active>;
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pinctrl-1 = <&qupv3_se1_spi_sleep>;
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dmas = <&gpi_dma0 0 1 1 64 2>,
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<&gpi_dma0 1 1 1 64 2>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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status = "disabled";
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};
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qupv3_se3_i2c: i2c@98c000 {
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compatible = "qcom,i2c-geni";
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reg = <0x98c000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
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interconnects =
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<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
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<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
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<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
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interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se3_i2c_sda_active>, <&qupv3_se3_i2c_scl_active>;
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pinctrl-1 = <&qupv3_se3_i2c_sleep>;
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dmas = <&gpi_dma0 0 3 3 64 0>,
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<&gpi_dma0 1 3 3 64 0>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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qupv3_se3_spi: spi@98c000 {
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compatible = "qcom,spi-geni";
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reg = <0x98c000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
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interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
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interconnects =
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<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
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<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
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<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se3_spi_mosi_active>, <&qupv3_se3_spi_miso_active>,
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<&qupv3_se3_spi_clk_active>, <&qupv3_se3_spi_cs_active>;
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pinctrl-1 = <&qupv3_se3_spi_sleep>;
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dmas = <&gpi_dma0 0 3 1 64 0>,
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<&gpi_dma0 1 3 1 64 0>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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status = "disabled";
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};
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qupv3_se4_i2c: i2c@990000 {
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compatible = "qcom,i2c-geni";
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reg = <0x990000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
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interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
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interconnects =
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<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
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<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
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<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se4_i2c_sda_active>, <&qupv3_se4_i2c_scl_active>;
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pinctrl-1 = <&qupv3_se4_i2c_sleep>;
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dmas = <&gpi_dma0 0 4 3 64 0>,
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<&gpi_dma0 1 4 3 64 0>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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qupv3_se4_spi: spi@990000 {
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compatible = "qcom,spi-geni";
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reg = <0x990000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
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interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
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interconnects =
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<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
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<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
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<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se4_spi_mosi_active>, <&qupv3_se4_spi_miso_active>,
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<&qupv3_se4_spi_clk_active>, <&qupv3_se4_spi_cs_active>;
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pinctrl-1 = <&qupv3_se4_spi_sleep>;
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dmas = <&gpi_dma0 0 4 1 64 0>,
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<&gpi_dma0 1 4 1 64 0>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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status = "disabled";
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};
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};
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/* GPI Instance */
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gpi_dma1: qcom,gpi-dma@a00000 {
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compatible = "qcom,gpi-dma";
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#dma-cells = <5>;
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reg = <0xa00000 0x60000>;
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reg-names = "gpi-top";
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iommus = <&apps_smmu 0x416 0x0>;
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qcom,max-num-gpii = <12>;
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interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
|
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<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
|
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<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
|
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<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
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qcom,gpii-mask = <0x3f>;
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qcom,ev-factor = <2>;
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qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
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dma-coherent;
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qcom,gpi-ee-offset = <0x10000>;
|
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status = "ok";
|
||||
};
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/* QUPv3_1 wrapper instance */
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qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0xac0000 0x2000>;
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#address-cells = <1>;
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#size-cells = <1>;
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clock-names = "m-ahb", "s-ahb";
|
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clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
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iommus = <&apps_smmu 0x403 0x0>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
|
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qcom,iommu-geometry = <0x40000000 0x10000000>;
|
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qcom,iommu-dma = "fastmap";
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dma-coherent;
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ranges;
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status = "ok";
|
||||
|
||||
/* PORed Debug UART Instance */
|
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qupv3_se7_2uart: qcom,qup_uart@a88000 {
|
||||
compatible = "qcom,geni-debug-uart";
|
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reg = <0xa88000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
|
||||
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se7_2uart_tx_active>, <&qupv3_se7_2uart_rx_active>;
|
||||
pinctrl-1 = <&qupv3_se7_2uart_sleep>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
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qupv3_se5_i2c: i2c@a80000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xa80000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
|
||||
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se5_i2c_sda_active>, <&qupv3_se5_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se5_i2c_sleep>;
|
||||
dmas = <&gpi_dma1 0 0 3 64 0>,
|
||||
<&gpi_dma1 1 0 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se5_spi: spi@a80000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0xa80000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
|
||||
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se5_spi_mosi_active>, <&qupv3_se5_spi_miso_active>,
|
||||
<&qupv3_se5_spi_clk_active>, <&qupv3_se5_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se5_spi_sleep>;
|
||||
dmas = <&gpi_dma1 0 0 1 64 0>,
|
||||
<&gpi_dma1 1 0 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se6_i2c: i2c@a84000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xa84000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
|
||||
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se6_i2c_sda_active>, <&qupv3_se6_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se6_i2c_sleep>;
|
||||
dmas = <&gpi_dma1 0 1 3 64 0>,
|
||||
<&gpi_dma1 1 1 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se6_spi: spi@a84000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0xa84000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
|
||||
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se6_spi_mosi_active>, <&qupv3_se6_spi_miso_active>,
|
||||
<&qupv3_se6_spi_clk_active>, <&qupv3_se6_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se6_spi_sleep>;
|
||||
dmas = <&gpi_dma1 0 1 1 64 0>,
|
||||
<&gpi_dma1 1 1 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se8_i2c: i2c@a8c000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xa8c000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
|
||||
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se8_i2c_sda_active>, <&qupv3_se8_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se8_i2c_sleep>;
|
||||
dmas = <&gpi_dma1 0 3 3 64 0>,
|
||||
<&gpi_dma1 1 3 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
qcom,shared;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se8_spi: spi@a8c000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0xa8c000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
|
||||
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se8_spi_mosi_active>, <&qupv3_se8_spi_miso_active>,
|
||||
<&qupv3_se8_spi_clk_active>, <&qupv3_se8_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se8_spi_sleep>;
|
||||
dmas = <&gpi_dma1 0 3 1 64 0>,
|
||||
<&gpi_dma1 1 3 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se9_i2c: i2c@a90000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xa90000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
|
||||
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se9_i2c_sda_active>, <&qupv3_se9_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se9_i2c_sleep>;
|
||||
dmas = <&gpi_dma1 0 4 3 64 0>,
|
||||
<&gpi_dma1 1 4 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se9_spi: spi@a90000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0xa90000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
|
||||
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se9_spi_mosi_active>, <&qupv3_se9_spi_miso_active>,
|
||||
<&qupv3_se9_spi_clk_active>, <&qupv3_se9_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se9_spi_sleep>;
|
||||
dmas = <&gpi_dma1 0 4 1 64 0>,
|
||||
<&gpi_dma1 1 4 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
Reference in New Issue
Block a user