From 1b78f8027a4fee53f515191b1177871019e9c19c Mon Sep 17 00:00:00 2001 From: Swetha Chikkaboraiah Date: Mon, 4 Mar 2024 13:52:23 +0530 Subject: [PATCH] ARM: dts: msm: Add initial device tree for ravelin Add initial device tree support for ravelin target. This is a snapshot of dtsi files as of KP.1.0 'commit <370d8eab7cc6> ("Merge "ARM: dts: qcom: Disable cnss-kiwi SOL on anorak platform"")'. Modified as per compilation and bootup. Change-Id: Icb9a6e67879c68dbf894d1713fa2837882b9f00c Signed-off-by: Swetha Chikkaboraiah --- qcom/Makefile | 20 + qcom/ipcc-test-ravelin.dtsi | 10 + qcom/msm-arm-smmu-ravelin.dtsi | 379 ++ qcom/platform_map.bzl | 11 + qcom/pmi632.dtsi | 532 +++ qcom/ravelin-4gb.dts | 14 + qcom/ravelin-4gb.dtsi | 16 + qcom/ravelin-atp-overlay.dts | 16 + qcom/ravelin-atp.dts | 15 + qcom/ravelin-atp.dtsi | 144 + qcom/ravelin-coresight.dtsi | 3727 +++++++++++++++++ qcom/ravelin-debug.dtsi | 1584 +++++++ qcom/ravelin-dma-heaps.dtsi | 43 + qcom/ravelin-idp-overlay.dts | 16 + ...ravelin-idp-wcn3950-amoled-rcm-overlay.dts | 16 + qcom/ravelin-idp-wcn3950-amoled-rcm.dts | 15 + qcom/ravelin-idp-wcn3950-amoled-rcm.dtsi | 47 + qcom/ravelin-idp-wcn3988-4gb-overlay.dts | 16 + qcom/ravelin-idp-wcn3988-4gb.dts | 15 + qcom/ravelin-idp-wcn3988-4gb.dtsi | 6 + qcom/ravelin-idp.dts | 15 + qcom/ravelin-idp.dtsi | 193 + qcom/ravelin-low-memory.dtsi | 42 + qcom/ravelin-msm-rdbg.dtsi | 19 + qcom/ravelin-pcie.dtsi | 277 ++ qcom/ravelin-pinctrl.dtsi | 1403 +++++++ qcom/ravelin-pm7250b.dtsi | 355 ++ qcom/ravelin-pmi632.dtsi | 326 ++ qcom/ravelin-pmic-overlay.dtsi | 663 +++ qcom/ravelin-qcx6438.dtsi | 62 + qcom/ravelin-qrd-4gb-overlay.dts | 16 + qcom/ravelin-qrd-4gb.dts | 15 + qcom/ravelin-qrd-4gb.dtsi | 6 + qcom/ravelin-qrd-overlay.dts | 17 + qcom/ravelin-qrd.dts | 16 + qcom/ravelin-qrd.dtsi | 164 + qcom/ravelin-qupv3.dtsi | 528 +++ qcom/ravelin-regulators.dtsi | 814 ++++ qcom/ravelin-reserved-memory.dtsi | 174 + qcom/ravelin-rumi-overlay.dts | 17 + qcom/ravelin-rumi.dts | 17 + qcom/ravelin-rumi.dtsi | 243 ++ qcom/ravelin-stub-regulator.dtsi | 429 ++ qcom/ravelin-thermal-modem.dtsi | 404 ++ qcom/ravelin-thermal-overlay.dtsi | 62 + qcom/ravelin-thermal.dtsi | 951 +++++ qcom/ravelin-usb.dtsi | 325 ++ qcom/ravelin-wcn6750.dtsi | 117 + qcom/ravelin.dts | 15 + qcom/ravelin.dtsi | 2569 ++++++++++++ qcom/ravelinp-4gb.dts | 14 + qcom/ravelinp-4gb.dtsi | 12 + qcom/ravelinp-atp.dts | 15 + qcom/ravelinp-atp.dtsi | 6 + qcom/ravelinp-idp-wcn3950-amoled-rcm.dts | 15 + qcom/ravelinp-idp-wcn3950-amoled-rcm.dtsi | 6 + qcom/ravelinp-idp-wcn3988-4gb.dts | 15 + qcom/ravelinp-idp-wcn3988-4gb.dtsi | 7 + qcom/ravelinp-idp.dts | 15 + qcom/ravelinp-idp.dtsi | 6 + qcom/ravelinp-qrd-4gb.dts | 15 + qcom/ravelinp-qrd-4gb.dtsi | 6 + qcom/ravelinp-qrd.dts | 16 + qcom/ravelinp-qrd.dtsi | 6 + qcom/ravelinp.dts | 15 + qcom/ravelinp.dtsi | 11 + 66 files changed, 17076 insertions(+) create mode 100644 qcom/ipcc-test-ravelin.dtsi create mode 100644 qcom/msm-arm-smmu-ravelin.dtsi create mode 100644 qcom/pmi632.dtsi create mode 100644 qcom/ravelin-4gb.dts create mode 100644 qcom/ravelin-4gb.dtsi create mode 100644 qcom/ravelin-atp-overlay.dts create mode 100644 qcom/ravelin-atp.dts create mode 100644 qcom/ravelin-atp.dtsi create mode 100644 qcom/ravelin-coresight.dtsi create mode 100644 qcom/ravelin-debug.dtsi create mode 100644 qcom/ravelin-dma-heaps.dtsi create mode 100644 qcom/ravelin-idp-overlay.dts create mode 100644 qcom/ravelin-idp-wcn3950-amoled-rcm-overlay.dts create mode 100644 qcom/ravelin-idp-wcn3950-amoled-rcm.dts create mode 100644 qcom/ravelin-idp-wcn3950-amoled-rcm.dtsi create mode 100644 qcom/ravelin-idp-wcn3988-4gb-overlay.dts create mode 100644 qcom/ravelin-idp-wcn3988-4gb.dts create mode 100644 qcom/ravelin-idp-wcn3988-4gb.dtsi create mode 100644 qcom/ravelin-idp.dts create mode 100644 qcom/ravelin-idp.dtsi create mode 100644 qcom/ravelin-low-memory.dtsi create mode 100644 qcom/ravelin-msm-rdbg.dtsi create mode 100644 qcom/ravelin-pcie.dtsi create mode 100644 qcom/ravelin-pinctrl.dtsi create mode 100644 qcom/ravelin-pm7250b.dtsi create mode 100644 qcom/ravelin-pmi632.dtsi create mode 100644 qcom/ravelin-pmic-overlay.dtsi create mode 100644 qcom/ravelin-qcx6438.dtsi create mode 100644 qcom/ravelin-qrd-4gb-overlay.dts create mode 100644 qcom/ravelin-qrd-4gb.dts create mode 100644 qcom/ravelin-qrd-4gb.dtsi create mode 100644 qcom/ravelin-qrd-overlay.dts create mode 100644 qcom/ravelin-qrd.dts create mode 100644 qcom/ravelin-qrd.dtsi create mode 100644 qcom/ravelin-qupv3.dtsi create mode 100644 qcom/ravelin-regulators.dtsi create mode 100644 qcom/ravelin-reserved-memory.dtsi create mode 100644 qcom/ravelin-rumi-overlay.dts create mode 100644 qcom/ravelin-rumi.dts create mode 100644 qcom/ravelin-rumi.dtsi create mode 100644 qcom/ravelin-stub-regulator.dtsi create mode 100644 qcom/ravelin-thermal-modem.dtsi create mode 100644 qcom/ravelin-thermal-overlay.dtsi create mode 100644 qcom/ravelin-thermal.dtsi create mode 100644 qcom/ravelin-usb.dtsi create mode 100644 qcom/ravelin-wcn6750.dtsi create mode 100644 qcom/ravelin.dts create mode 100644 qcom/ravelin.dtsi create mode 100644 qcom/ravelinp-4gb.dts create mode 100644 qcom/ravelinp-4gb.dtsi create mode 100644 qcom/ravelinp-atp.dts create mode 100644 qcom/ravelinp-atp.dtsi create mode 100644 qcom/ravelinp-idp-wcn3950-amoled-rcm.dts create mode 100644 qcom/ravelinp-idp-wcn3950-amoled-rcm.dtsi create mode 100644 qcom/ravelinp-idp-wcn3988-4gb.dts create mode 100644 qcom/ravelinp-idp-wcn3988-4gb.dtsi create mode 100644 qcom/ravelinp-idp.dts create mode 100644 qcom/ravelinp-idp.dtsi create mode 100644 qcom/ravelinp-qrd-4gb.dts create mode 100644 qcom/ravelinp-qrd-4gb.dtsi create mode 100644 qcom/ravelinp-qrd.dts create mode 100644 qcom/ravelinp-qrd.dtsi create mode 100644 qcom/ravelinp.dts create mode 100644 qcom/ravelinp.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 242401a7..ebe62f22 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -125,6 +125,26 @@ parrot-dtb-$(CONFIG_ARCH_PARROT) += \ parrot-overlays-dtb-$(CONFIG_ARCH_PARROT) += $(PARROT_BOARDS) $(PARROT_BASE_DTB) $(PARROT_4GB_BOARDS) $(PARROT_4GB_BASE_DTB) dtb-y += $(parrot-dtb-y) +RAVELIN_BASE_DTB += ravelin.dtb ravelinp.dtb +RAVELIN_4GB_BASE_DTB += ravelin-4gb.dtb ravelinp-4gb.dtb + +RAVELIN_BOARDS += \ + ravelin-rumi-overlay.dtbo \ + ravelin-atp-overlay.dtbo \ + ravelin-idp-overlay.dtbo \ + ravelin-idp-wcn3950-amoled-rcm-overlay.dtbo \ + ravelin-qrd-overlay.dtbo \ + +RAVELIN_4GB_BOARDS += \ + ravelin-idp-wcn3988-4gb-overlay.dtbo \ + ravelin-qrd-4gb-overlay.dtbo \ + +parrot-dtb-$(CONFIG_ARCH_RAVELIN) += \ + $(call add-overlays, $(RAVELIN_BOARDS),$(RAVELIN_BASE_DTB)) \ + $(call add-overlays, $(RAVELIN_4GB_BOARDS),$(RAVELIN_4GB_BASE_DTB)) +parrot-overlays-dtb-$(CONFIG_ARCH_RAVELIN) += $(RAVELIN_BOARDS) $(RAVELIN_BASE_DTB) $(RAVELIN_4GB_BOARDS) $(RAVELIN_4GB_BASE_DTB) +dtb-y += $(parrot-dtb-y) + endif ifeq ($(CONFIG_ARCH_PINEAPPLE), y) diff --git a/qcom/ipcc-test-ravelin.dtsi b/qcom/ipcc-test-ravelin.dtsi new file mode 100644 index 00000000..bf439c38 --- /dev/null +++ b/qcom/ipcc-test-ravelin.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ipcc-test.dtsi" + +&soc { + /delete-node/ ipcc-self-ping-slpi; +}; diff --git a/qcom/msm-arm-smmu-ravelin.dtsi b/qcom/msm-arm-smmu-ravelin.dtsi new file mode 100644 index 00000000..6ebf4e64 --- /dev/null +++ b/qcom/msm-arm-smmu-ravelin.dtsi @@ -0,0 +1,379 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + kgsl_smmu: kgsl-smmu@3da0000 { + compatible = "qcom,qsmmu-v500", "qcom,adreno-smmu"; + reg = <0x3da0000 0x10000>, + <0x3dc2000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,use-3-lvl-tables; + qcom,num-context-banks-override = <0x5>; + qcom,num-smr-override = <0x7>; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + dma-coherent; + + qcom,regulator-names = "vdd"; + vdd-supply = <&gpu_cc_cx_gdsc>; + + qcom,actlr = + /* All CBs of GFX: +15 deep PF */ + <0x0 0x1FFF 0x32B>; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = + "gpu_cc_cx_gmu", + "gpu_cc_hub_cx_int", + "gpu_cc_hlos1_vote_gpu_smmu", + "gcc_gpu_memnoc_gfx", + "gcc_gpu_snoc_dvm_gfx", + "gpu_cc_ahb"; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + ; + + gfx_0_tbu: gfx_0_tbu@3dc5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x3dc5000 0x1000>, + <0x3dc2200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + }; + + gfx_1_tbu: gfx_1_tbu@3dc9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x3dc9000 0x1000>, + <0x3dc2208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + }; + }; + + apps_smmu: apps-smmu@15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x100000>, + <0x151e2000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,use-3-lvl-tables; + qcom,num-context-banks-override = <0x52>; + qcom,num-smr-override = <0x85>; + qcom,handoff-smrs = <0x800 0x402>; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + dma-coherent; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + qcom,actlr = + /* For video clients, +3 PF */ + <0x1980 0x3F 0x103>, + /* Display and camera clients, +0 PF */ + <0x1900 0x3F 0x1>, + <0x1800 0xFF 0x1>, + <0x800 0x7FF 0x1>; + + clocks = <&gcc GCC_HLOS1_VOTE_MMU_TCU_CLK>; + clock-names = + "gcc_hlos1_vote_mmu_tcu_clk"; + interconnects = <&gem_noc MASTER_APPSS_PROC + &cnoc3 SLAVE_TCU>; + qcom,active-only; + + anoc_1_tbu: anoc_1_tbu@151e5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151e5000 0x1000>, + <0x151e2200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + qcom,iova-width = <36>; + qcom,micro-idle; + clocks = <&gcc GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK>; + clock-names = + "gcc_hlos1_vote_aggre_noc_mmu_tbu1_clk"; + interconnects = <&gem_noc MASTER_APPSS_PROC + &cnoc3 SLAVE_IMEM>; + qcom,active-only; + }; + + anoc_2_tbu: anoc_2_tbu@151e9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151e9000 0x1000>, + <0x151e2208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + qcom,iova-width = <36>; + qcom,micro-idle; + clocks = <&gcc GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK>; + clock-names = + "gcc_hlos1_vote_aggre_noc_mmu_tbu2_clk"; + interconnects = <&gem_noc MASTER_APPSS_PROC + &cnoc3 SLAVE_IMEM>; + qcom,active-only; + }; + + mnoc_hf_0_tbu: mnoc_hf_0_tbu@151ed000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151ed000 0x1000>, + <0x151e2210 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x800 0x400>; + qcom,iova-width = <32>; + qcom,micro-idle; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>; + clocks = <&gcc GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_CLK>; + clock-names = + "gcc_hlos1_vote_mmnoc_mmu_tbu_hf0_clk"; + interconnects = <&mmss_noc MASTER_CAMNOC_HF + &mc_virt SLAVE_EBI1>; + qcom,active-only; + }; + + mnoc_hf_1_tbu: mnoc_hf_1_tbu@151f1000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151f1000 0x1000>, + <0x151e2218 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0xc00 0x400>; + qcom,iova-width = <32>; + qcom,micro-idle; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc>; + clocks = <&gcc GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_CLK>; + clock-names = + "gcc_hlos1_vote_mmnoc_mmu_tbu_hf1_clk"; + interconnects = <&mmss_noc MASTER_CAMNOC_HF + &mc_virt SLAVE_EBI1>; + qcom,active-only; + }; + + lpass_tbu: lpass_tbu@151f5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151f5000 0x1000>, + <0x151e2220 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1000 0x400>; + qcom,iova-width = <32>; + qcom,micro-idle; + clocks = <&gcc GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK>; + clock-names = + "gcc_hlos1_vote_aggre_noc_mmu_audio_tbu_clk"; + interconnects = <&lpass_ag_noc MASTER_LPASS_PROC + &mc_virt SLAVE_EBI1>; + qcom,active-only; + }; + + pcie_tbu: pcie_tbu@151f9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151f9000 0x1000>, + <0x151e2228 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1400 0x400>; + qcom,iova-width = <36>; + qcom,micro-idle; + clocks = <&gcc GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK>; + clock-names = + "gcc_hlos1_vote_aggre_noc_mmu_pcie_tbu_clk"; + interconnects = <&pcie_anoc MASTER_PCIE_0 + &mc_virt SLAVE_EBI1>; + qcom,active-only; + }; + + sf_0_tbu: sf_0_tbu@151fd000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151fd000 0x1000>, + <0x151e2230 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1800 0x400>; + qcom,iova-width = <32>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc>; + qcom,micro-idle; + clocks = <&gcc GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_CLK>; + clock-names = + "gcc_hlos1_vote_mmnoc_mmu_tbu_sf0_clk"; + interconnects = <&mmss_noc MASTER_CAMNOC_SF + &mc_virt SLAVE_EBI1>; + qcom,active-only; + }; + }; + + dma_dev@0x0 { + compatible = "qcom,iommu-dma"; + memory-region = <&system_cma>; + }; + + iommu_test_device { + compatible = "qcom,iommu-debug-test"; + + usecase0_apps { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x7e0 0>; + }; + + usecase1_apps_fastmap { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x7e0 0>; + qcom,iommu-dma = "fastmap"; + }; + + usecase2_apps_atomic { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x7e0 0>; + qcom,iommu-dma = "atomic"; + }; + + usecase3_apps_dma { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x7e0 0>; + qcom,iommu-dma = "atomic"; + }; + + usecase4_apps_coherent { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x7e1 0>; + dma-coherent; + }; + + usecase5_kgsl_dma { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&kgsl_smmu 0x7 0x400>; + }; + + usecase6_kgsl_coherent { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&kgsl_smmu 0x407 0x400>; + dma-coherent; + }; + + usecase7_apps_secure { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x7e0 0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ + }; + }; +}; diff --git a/qcom/platform_map.bzl b/qcom/platform_map.bzl index 77dfc563..f70d7b36 100644 --- a/qcom/platform_map.bzl +++ b/qcom/platform_map.bzl @@ -191,6 +191,10 @@ _platform_map = { {"name": "parrot-sg.dtb"}, {"name": "parrotp-sg.dtb"}, {"name": "parrot-4gb.dtb"}, + {"name": "ravelin.dtb"}, + {"name": "ravelinp.dtb"}, + {"name": "ravelin-4gb.dtb"}, + {"name": "ravelinp-4gb.dtb"}, ], "dtbo_list": [ # keep sorted @@ -214,6 +218,13 @@ _platform_map = { {"name": "parrot-idp-wcn6750-amoled-4gb-overlay.dtbo"}, {"name": "parrot-qrd-4gb-overlay.dtbo"}, {"name": "parrot-qrd-wcn6750-4gb-overlay.dtbo"}, + {"name": "ravelin-rumi-overlay.dtbo"}, + {"name": "ravelin-atp-overlay.dtbo"}, + {"name": "ravelin-idp-overlay.dtbo"}, + {"name": "ravelin-idp-wcn3950-amoled-rcm-overlay.dtbo"}, + {"name": "ravelin-qrd-overlay.dtbo"}, + {"name": "ravelin-idp-wcn3988-4gb-overlay.dtbo"}, + {"name": "ravelin-qrd-4gb-overlay.dtbo"}, ], }, } diff --git a/qcom/pmi632.dtsi b/qcom/pmi632.dtsi new file mode 100644 index 00000000..625aedac --- /dev/null +++ b/qcom/pmi632.dtsi @@ -0,0 +1,532 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + pmi632_2: qcom,pmi632@2 { + compatible = "qcom,spmi-pmic"; + reg = <2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmi632_pon: qcom,power-on@800 { + reg = <0x800>; + }; + + pmi632_vadc: vadc@3100 { + compatible = "qcom,spmi-adc5-lite"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + #io-channel-cells = <1>; + io-channel-ranges; + + /* Channel nodes */ + ref_gnd { + reg = ; + label = "ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + vref_1p25 { + reg = ; + label = "vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + die_temp { + reg = ; + label = "die_temp"; + qcom,pre-scaling = <1 1>; + }; + + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + vbat_sns { + reg = ; + label = "vbat_sns"; + qcom,pre-scaling = <1 3>; + }; + + usb_in_i_uv { + reg = ; + label = "usb_in_i_uv"; + qcom,pre-scaling = <1 1>; + }; + + chg_temp { + reg = ; + label = "chg_temp"; + qcom,pre-scaling = <1 1>; + }; + + bat_therm { + reg = ; + label = "bat_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + bat_therm_30k { + reg = ; + label = "bat_therm_30k"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + bat_therm_400k { + reg = ; + label = "bat_therm_400k"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + bat_id { + reg = ; + label = "bat_id"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + i_parallel { + reg = ; + label = "i_parallel"; + qcom,pre-scaling = <1 1>; + }; + }; + + pmi632_adc_tm: adc_tm@3500 { + reg = <0x3500>; + interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "threshold"; + #address-cells = <1>; + #size-cells = <0>; + #thermal-sensor-cells = <1>; + }; + + pmi632_tz: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x2 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pmi632_vadc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + qcom,schgm-flash@a600 { + reg = <0xa600>; + interrupts = <0x2 0xa6 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0xa6 0x6 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "flash-state-change", + "ilim2-s2"; + qcom,flash-disable-soc = <10>; + }; + + pmi632_gpios: pinctrl@c000 { + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pmi632_pbs_client3: qcom,pbs@7400 { + compatible = "qcom,qpnp-pbs"; + reg = <0x7400>; + }; + + pmi632_sdam7: qcom,sdam@b600 { + compatible = "qcom,spmi-sdam"; + reg = <0xb600>; + }; + + pmi632_bcl: bcl@3d00 { + compatible = "qcom,bcl-v5"; + reg = <0x3d00>; + interrupts = <0x2 0x3d 0x0 IRQ_TYPE_NONE>, + <0x2 0x3d 0x1 IRQ_TYPE_NONE>, + <0x2 0x3d 0x2 IRQ_TYPE_NONE>; + interrupt-names = "bcl-lvl0", + "bcl-lvl1", + "bcl-lvl2"; + qcom,ibat-use-qg-adc-5a; + #thermal-sensor-cells = <1>; + }; + + bcl_soc: bcl-soc { + compatible = "qcom,msm-bcl-soc"; + #thermal-sensor-cells = <0>; + }; + }; + + pmi632_3: qcom,pmi632@3 { + compatible ="qcom,spmi-pmic"; + reg = <3 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmi632_vib: qcom,vibrator@5700 { + reg = <0x5700>; + qcom,vib-ldo-volt-uv = <3000000>; + qcom,disable-overdrive; + }; + + pmi632_pwm: qcom,pwms@b300 { + reg = <0xb300>; + reg-names = "lpg-base"; + #pwm-cells = <2>; + qcom,num-lpg-channels = <5>; + nvmem-names = "ppg_sdam"; + nvmem = <&pmi632_sdam7>; + qcom,pbs-client = <&pmi632_pbs_client3>; + qcom,lut-sdam-base = <0x80>; + qcom,lut-patterns = <0 0 0 14 28 42 56 70 84 100 + 100 84 70 56 42 28 14 0 0 0>; + lpg@1 { + qcom,lpg-chan-id = <1>; + qcom,ramp-step-ms = <200>; + qcom,ramp-low-index = <0>; + qcom,ramp-high-index = <19>; + qcom,ramp-pattern-repeat; + qcom,lpg-sdam-base = <0x48>; + }; + + lpg@2 { + qcom,lpg-chan-id = <2>; + qcom,ramp-step-ms = <200>; + qcom,ramp-low-index = <0>; + qcom,ramp-high-index = <19>; + qcom,ramp-pattern-repeat; + qcom,lpg-sdam-base = <0x56>; + }; + + lpg@3 { + qcom,lpg-chan-id = <3>; + qcom,ramp-step-ms = <200>; + qcom,ramp-low-index = <0>; + qcom,ramp-high-index = <19>; + qcom,ramp-pattern-repeat; + qcom,lpg-sdam-base = <0x64>; + }; + }; + + pmi632_rgb: qcom,leds@d000 { + reg = <0xd000>; + red { + label = "red"; + pwms = <&pmi632_pwm 0 1000000>; + led-sources = <0>; + linux,default-trigger = "timer"; + }; + + green { + label = "green"; + pwms = <&pmi632_pwm 1 1000000>; + led-sources = <1>; + linux,default-trigger = "timer"; + }; + + blue { + label = "blue"; + pwms = <&pmi632_pwm 2 1000000>; + led-sources = <2>; + linux,default-trigger = "timer"; + }; + }; + + pmi632_lcdb: qpnp-lcdb@ec00 { + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xec00>; + interrupts = <0x3 0xec 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "sc-irq"; + + qcom,voltage-step-ramp; + + lcdb_ldo_vreg: ldo { + label = "ldo"; + regulator-name = "lcdb_ldo"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <6000000>; + }; + + lcdb_ncp_vreg: ncp { + label = "ncp"; + regulator-name = "lcdb_ncp"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <6000000>; + }; + + lcdb_bst_vreg: bst { + label = "bst"; + regulator-name = "lcdb_bst"; + regulator-min-microvolt = <4700000>; + regulator-max-microvolt = <6275000>; + }; + }; + + flash_led: qcom,leds@d300 { + reg = <0xd300>; + label = "flash"; + interrupts = <0x3 0xd3 0x0 IRQ_TYPE_EDGE_RISING>, + <0x3 0xd3 0x3 IRQ_TYPE_EDGE_RISING>, + <0x3 0xd3 0x4 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "led-fault-irq", + "all-ramp-down-done-irq", + "all-ramp-up-done-irq"; + qcom,short-circuit-det; + qcom,open-circuit-det; + qcom,vph-droop-det; + qcom,thermal-derate-en; + qcom,thermal-derate-current = <200 500 1000>; + qcom,isc-delay = <192>; + + pmi632_flash0: qcom,flash_0 { + label = "flash"; + qcom,led-name = "led:flash_0"; + qcom,max-current = <1500>; + qcom,default-led-trigger = "flash0_trigger"; + qcom,id = <0>; + qcom,current-ma = <1000>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <400>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pmi632_flash1: qcom,flash_1 { + label = "flash"; + qcom,led-name = "led:flash_1"; + qcom,max-current = <1500>; + qcom,default-led-trigger = "flash1_trigger"; + qcom,id = <1>; + qcom,current-ma = <1000>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <400>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pmi632_torch0: qcom,torch_0 { + label = "torch"; + qcom,led-name = "led:torch_0"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch0_trigger"; + qcom,id = <0>; + qcom,current-ma = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <400>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pmi632_torch1: qcom,torch_1 { + label = "torch"; + qcom,led-name = "led:torch_1"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch1_trigger"; + qcom,id = <1>; + qcom,current-ma = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <400>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pmi632_switch0: qcom,led_switch_0 { + label = "switch"; + qcom,led-name = "led:switch_0"; + qcom,led-mask = <3>; + qcom,default-led-trigger = "switch0_trigger"; + }; + + pmi632_switch1: qcom,led_switch_1 { + label = "switch"; + qcom,led-name = "led:switch_1"; + qcom,led-mask = <2>; + qcom,default-led-trigger = "switch1_trigger"; + }; + + }; + + }; +}; + +&thermal_zones { + pmi632-tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmi632_tz>; + + trips { + pmi632_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pmi632_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; + + pmi632-ibat-lvl0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmi632_bcl 0>; + + trips { + ibat_lvl0: ibat-lvl0 { + temperature = <4000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pmi632-ibat-lvl1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmi632_bcl 1>; + + trips { + ibat_lvl1: ibat-lvl1 { + temperature = <5000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pmi632-bcl-lvl0 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmi632_bcl 5>; + + trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + thermal-hal-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + b_bcl_lvl0: b-bcl-lvl0 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + pmi632-bcl-lvl1 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmi632_bcl 6>; + + trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + thermal-hal-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + b_bcl_lvl1: b-bcl-lvl1 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + pmi632-bcl-lvl2 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmi632_bcl 7>; + + trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + thermal-hal-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + b_bcl_lvl2: b-bcl-lvl2 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + socd { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&bcl_soc>; + + trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + thermal-hal-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + socd_trip:socd-trip { + temperature = <90>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; +}; diff --git a/qcom/ravelin-4gb.dts b/qcom/ravelin-4gb.dts new file mode 100644 index 00000000..73105488 --- /dev/null +++ b/qcom/ravelin-4gb.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin-4gb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin 4Gb SoC"; + compatible = "qcom,ravelin"; + qcom,board-id = <0 0x600>; +}; diff --git a/qcom/ravelin-4gb.dtsi b/qcom/ravelin-4gb.dtsi new file mode 100644 index 00000000..778de904 --- /dev/null +++ b/qcom/ravelin-4gb.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin.dtsi" +#include "ravelin-low-memory.dtsi" +/ { +}; + +&mem_client_3_size { + qcom,peripheral-size = <0x200000>; +}; + +&soc { +}; diff --git a/qcom/ravelin-atp-overlay.dts b/qcom/ravelin-atp-overlay.dts new file mode 100644 index 00000000..7ea7d64b --- /dev/null +++ b/qcom/ravelin-atp-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "ravelin-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin ATP"; + compatible = "qcom,ravelin-atp", "qcom,ravelin", "qcom,atp"; + qcom,msm-id = <568 0x10000>, <602 0x10000>; + qcom,board-id = <33 0>; +}; diff --git a/qcom/ravelin-atp.dts b/qcom/ravelin-atp.dts new file mode 100644 index 00000000..78d603ee --- /dev/null +++ b/qcom/ravelin-atp.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin.dtsi" +#include "ravelin-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin ATP"; + compatible = "qcom,ravelin-atp", "qcom,ravelin", "qcom,atp"; + qcom,board-id = <33 0>; +}; diff --git a/qcom/ravelin-atp.dtsi b/qcom/ravelin-atp.dtsi new file mode 100644 index 00000000..f1aa4a4f --- /dev/null +++ b/qcom/ravelin-atp.dtsi @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-pmic-overlay.dtsi" +#include "ravelin-pm7250b.dtsi" +#include "ravelin-thermal-overlay.dtsi" + +&soc { +}; + +&qupv3_se1_spi { + status = "ok"; + + #address-cells = <1>; + #size-cells = <0>; + qcom,spi-touch-active = "focaltech,fts_ts"; + + focaltech@0 { + reg = <0x0>; + spi-max-frequency = <6000000>; + interrupt-parent = <&tlmm>; + interrupts = <91 0x2008>; + focaltech,reset-gpio = <&tlmm 90 0x00>; + focaltech,irq-gpio = <&tlmm 91 0x2008>; + focaltech,display-coords = <0 0 1080 2340>; + focaltech,max-touch-number = <5>; + focaltech,ic-type = <0x3658D488>; + focaltech,touch-type = "primary"; + + vdd-supply = <&L4E>; + + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", "pmx_ts_release"; + pinctrl-0 = <&ts_spi_active>; + pinctrl-1 = <&ts_spi_int_suspend &ts_spi_reset_suspend>; + pinctrl-2 = <&ts_spi_release>; + }; +}; + +&sdhc_1 { + status = "ok"; + vdd-supply = <&L5E>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L19B>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-current-level = <0 325000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; +}; + +&sdhc_2 { + status = "ok"; + vdd-supply = <&L24B>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + /* + * min/max voltages are voted on L24B/L28B and L24B/L28B_PBS + * regulators will only be voted for enabling/disabling conditions + * to support FR84471 for chipsets where PMIC doesn't support + * PBS ram sequence to turn OFF regulators automatically on + * multicard tray removal and these new regulator resources are + * exposed by PMIC team as part of this FR. + */ + vdd-en-dis-supply = <&L24B_PBS>; + + vdd-io-supply = <&L28B>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + vdd-io-en-dis-supply = <&L28B_PBS>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>; +}; + +&ufsphy_mem { + /* + * Here parrot phy is used for ravelin as it + * do not have its own list for module load and + * hence compatible is using parrot. + * We have plan to improve this by making phy binary + * target independent. + */ + compatible = "qcom,ufs-phy-qmp-v4-waipio"; + + vdda-phy-supply = <&L5B>; + vdda-pll-supply = <&L16B>; + vdda-phy-max-microamp = <88530>; + vdda-pll-max-microamp = <18310>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + + vcc-supply = <&L5E>; + vcc-max-microamp = <1056000>; + + vccq-supply = <&L13B>; + vccq-max-microamp = <750000>; + + vccq2-supply = <&L19B>; + vccq2-max-microamp = <750000>; + + qcom,vddp-ref-clk-supply = <&L13B>; + qcom,vddp-ref-clk-max-microamp = <100>; + + /* + * ufs-dev-types and nvmem entries are for ufs device + * identification using nvmem interface. Use number of + * ufs devices supported for ufs-dev-types, and nvmem handle + * added by pmic for sdam register. + * + * Default value taken by driver is bit[0] = 0 for 3.x and + * bit[0] = 1 for 2.x driver code takes this as default case. + * + * But Bit value to identify ufs device is not consistent + * across the targets it could be bit[0] = 0/1 for UFS2.x/3x + * and vice versa. If the bit[0] value is not same as default + * value used in driver and if its reverted then use flag + * qcom,ufs-dev-revert to identify ufs device. + */ + ufs-dev-types = <2>; + qcom,ufs-dev-revert; + nvmem-cells = <&ufs_dev>, <&boot_config>; + nvmem-cell-names = "ufs_dev", "boot_conf"; + + status = "ok"; +}; + +&battery_charger { + qcom,thermal-mitigation-step = <500000>; + qcom,wireless-charging-not-supported; +}; diff --git a/qcom/ravelin-coresight.dtsi b/qcom/ravelin-coresight.dtsi new file mode 100644 index 00000000..586fac35 --- /dev/null +++ b/qcom/ravelin-coresight.dtsi @@ -0,0 +1,3727 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + audio_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-audio-etm0"; + qcom,inst-id = <5>; + atid = <40>; + + out-ports { + port { + audio_etm0_out_funnel_lpass_lpi: endpoint { + remote-endpoint = + <&funnel_lpass_lpi_in_audio_etm0>; + }; + }; + }; + }; + + tpdm_lpass_lpi: tpdm_lpass_lpi { + compatible = "arm,coresight-dummy-source"; + coresight-name = "coresight-tpdm-lpass-lpi"; + qcom,dummy-source; + + atid = <26>; + + out-ports { + port { + tpdm_lpass_lpi_out_funnel_lpass_lpi: endpoint { + remote-endpoint = + <&funnel_lpass_lpi_in_tpdm_lpass_lpi>; + }; + }; + }; + }; + + tpdm_lpass: tpdm@10844000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10844000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-lpass"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <74>; + out-ports { + port { + tpdm_lpass_out_funnel_lpass: endpoint { + remote-endpoint = + <&funnel_lpass_in_tpdm_lpass>; + }; + }; + }; + }; + + tpdm_dl_lpass: tpdm@10c38000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c38000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dl-lpass"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <74>; + out-ports { + port { + tpdm_dl_lpass_out_tpda_dl_lpass_10: endpoint { + remote-endpoint = + <&tpda_dl_lpass_10_in_tpdm_dl_lpass>; + }; + }; + }; + }; + + lpass_stm: lpass_stm { + compatible = "arm,coresight-dummy-source"; + coresight-name = "coresight-lpass-stm"; + qcom,dummy-source; + + atid = <25>; + + out-ports { + port { + lpass_stm_out_funnel_lpass_lpi: endpoint { + remote-endpoint = + <&funnel_lpass_lpi_in_lpass_stm>; + }; + }; + }; + }; + + tpdm_swao_prio_0: tpdm@10b09000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10b09000 0x1000>; + reg-names = "tpdm-base"; + + atid = <71>; + coresight-name = "coresight-tpdm-swao-prio-0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_swao_prio_0_out_tpda_aoss_0: endpoint { + remote-endpoint = + <&tpda_aoss_0_in_tpdm_swao_prio_0>; + }; + }; + }; + }; + + tpdm_swao_prio_1: tpdm@10b0a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10b0a000 0x1000>; + reg-names = "tpdm-base"; + + atid = <71>; + coresight-name = "coresight-tpdm-swao-prio-1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_swao_prio_1_out_tpda_aoss_1: endpoint { + remote-endpoint = + <&tpda_aoss_1_in_tpdm_swao_prio_1>; + }; + }; + }; + }; + + tpdm_swao_prio_2: tpdm@10b0b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10b0b000 0x1000>; + reg-names = "tpdm-base"; + + atid = <71>; + coresight-name = "coresight-tpdm-swao-prio-2"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_swao_prio_2_out_tpda_aoss_2: endpoint { + remote-endpoint = + <&tpda_aoss_2_in_tpdm_swao_prio_2>; + }; + }; + }; + }; + + tpdm_swao_prio_3: tpdm@10b0c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10b0c000 0x1000>; + reg-names = "tpdm-base"; + + atid = <71>; + coresight-name = "coresight-tpdm-swao-prio-3"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_swao_prio_3_out_tpda_aoss_3: endpoint { + remote-endpoint = + <&tpda_aoss_3_in_tpdm_swao_prio_3>; + }; + }; + }; + }; + + tpdm_swao_1: tpdm@10b0d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10b0d000 0x1000>; + reg-names = "tpdm-base"; + + atid = <71>; + coresight-name = "coresight-tpdm-swao-1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_swao_out_tpda_aoss_4: endpoint { + remote-endpoint = + <&tpda_aoss_4_in_tpdm_swao>; + }; + }; + }; + }; + + tpdm_ddr_ch01: tpdm@10d20000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10d20000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-ddr-ch01"; + + atid = <78>; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_ddr_ch01_out_funnel_ddr_ch01: endpoint { + remote-endpoint = + <&funnel_ddr_ch01_in_tpdm_ddr_ch01>; + }; + }; + }; + }; + + tpdm_ddr: tpdm@10d00000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10d00000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-ddr"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_ddr_dl0_out_funnel_ddr_dl0: endpoint { + remote-endpoint = + <&funnel_ddr_dl0_in_tpdm_ddr_dl0>; + }; + }; + }; + }; + + tpdm_shrm: tpdm@10d01000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10d01000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-shrm"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,cmb-msr-skip; + out-ports { + port { + tpdm_shrm_out_funnel_ddr_dl0: endpoint { + remote-endpoint = + <&funnel_ddr_dl0_in_tpdm_shrm>; + }; + }; + }; + }; + + tpdm_gpu: tpdm@10900000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10900000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-gpu"; + + atid = <79>; + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_gpu_out_funnel_gfx_dl: endpoint { + remote-endpoint = + <&funnel_gfx_dl_in_tpdm_gpu>; + }; + }; + }; + }; + + tpdm_prng: tpdm@10841000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10841000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-prng"; + + atid = <78>; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_prng_out_tpda_dl_center_19: endpoint { + remote-endpoint = + <&tpda_dl_center_19_in_tpdm_prng>; + }; + }; + }; + }; + + tpdm_qm: tpdm@109d0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x109d0000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-qm"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_qm_out_tpda_dl_center_20: endpoint { + remote-endpoint = + <&tpda_dl_center_20_in_tpdm_qm>; + }; + }; + }; + }; + + tpdm_gcc: tpdm@1082c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x1082c000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-gcc"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_gcc_out_tpda_dl_center_21: endpoint { + remote-endpoint = + <&tpda_dl_center_21_in_tpdm_gcc>; + }; + }; + }; + }; + + tpdm_vsense: tpdm@10840000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10840000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-vsense"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_vsense_out_tpda_dl_center_22: endpoint { + remote-endpoint = + <&tpda_dl_center_22_in_tpdm_vsense>; + }; + }; + }; + }; + + tpdm_emmc: tpdm@10c23000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c23000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-emmc"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_sdcc_out_tpda_dl_lpass_0: endpoint { + remote-endpoint = + <&tpda_dl_lpass_0_in_tpdm_sdcc>; + }; + }; + }; + }; + + tpdm_sdcc: tpdm@10c20000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c20000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-sdcc"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,cmb-msr-skip; + + out-ports { + port { + tpdm_sdcc2_out_tpda_dl_west: endpoint { + remote-endpoint = + <&tpda_dl_west_in_tpdm_sdcc2>; + }; + }; + }; + }; + + tpdm_ipa: tpdm@10c22000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c22000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-ipa"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,cmb-msr-skip; + + out-ports { + port { + tpdm_ipa_out_tpda_dl_center_24: endpoint { + remote-endpoint = + <&tpda_dl_center_24_in_tpdm_ipa>; + }; + }; + }; + }; + + tpdm_pimem: tpdm@10850000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10850000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-pimem"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_pimem_out_tpda_dl_center_25: endpoint { + remote-endpoint = + <&tpda_dl_center_25_in_tpdm_pimem>; + }; + }; + }; + }; + + tpdm_dlct: tpdm@10c28000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c28000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-dlct"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_dlct_out_tpda_dl_center_26: endpoint { + remote-endpoint = + <&tpda_dl_center_26_in_tpdm_dlct>; + }; + }; + }; + }; + + tpdm_ipcc: tpdm@10c29000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c29000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-ipcc"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_ipcc_out_tpda_dl_center_27: endpoint { + remote-endpoint = + <&tpda_dl_center_27_in_tpdm_ipcc>; + }; + }; + }; + }; + + tpdm_dl_west: tpdm@10C48000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10C48000 0x1000>; + reg-names = "tpdm-base"; + + atid = <101>; + coresight-name = "coresight-tpdm-dl-west"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_dl_west_out_tpda_dl_west: endpoint { + remote-endpoint = + <&tpda_dl_west_in_tpdm_dl_west>; + }; + }; + }; + }; + + snoc: snoc { + compatible = "arm,coresight-dummy-source"; + coresight-name = "coresight-snoc"; + qcom,dummy-source; + + atid = <125>; + out-ports { + port { + snoc_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_snoc>; + }; + }; + }; + }; + + tpdm_spdm: tpdm@1000f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x1000f000 0x1000>; + reg-names = "tpdm-base"; + + atid = <65>; + coresight-name = "coresight-tpdm-spdm"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_spdm_out_tpda_qdss_1: endpoint { + remote-endpoint = + <&tpda_qdss_1_in_tpdm_spdm>; + }; + }; + }; + }; + + stm: stm@10002000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb962>; + reg = <0x10002000 0x1000>, + <0x16280000 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + atid = <16>; + coresight-name = "coresight-stm"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + stm_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_stm>; + }; + }; + }; + }; + + tpdm_dcc: tpdm@10003000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10003000 0x1000>; + reg-names = "tpdm-base"; + + atid = <65>; + coresight-name = "coresight-tpdm-dcc"; + + qcom,hw-enable-check; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_dcc_out_tpda_qdss_0: endpoint { + remote-endpoint = + <&tpda_qdss_0_in_tpdm_dcc>; + }; + }; + }; + }; + + tpdm_dl_center2_dsb: tpdm@10ac0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10ac0000 0x1000>; + reg-names = "tpdm-base"; + + atid = <79>; + coresight-name = "coresight-tpdm-dlct2-dsb"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_dlct0_out_tpda_dl_center2_26: endpoint { + remote-endpoint = + <&tpda_dl_center2_26_in_tpdm_dlct0>; + }; + }; + }; + }; + + tpdm_dl_center2_cmb: tpdm@10ac1000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10ac1000 0x1000>; + reg-names = "tpdm-base"; + + atid = <79>; + coresight-name = "coresight-tpdm-dlct2-cmb"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,cmb-msr-skip; + status = "disabled"; + out-ports { + port { + tpdm_dlct1_out_tpda_dl_center2_27: endpoint { + remote-endpoint = + <&tpda_dl_center2_27_in_tpdm_dlct1>; + }; + }; + }; + }; + + tpdm_dl_south0: tpdm@109c0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x109c0000 0x1000>; + reg-names = "tpdm-base"; + + atid = <79>; + coresight-name = "coresight-tpdm-dl-south-dsb"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,cmb-msr-skip; + + out-ports { + port { + tpdm_dl_south0_out_funnel_dl_south: endpoint { + remote-endpoint = + <&funnel_dl_south_in_tpdm_dl_south0>; + }; + }; + }; + }; + + tpdm_dl_south1: tpdm@109c1000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x109c1000 0x1000>; + reg-names = "tpdm-base"; + + atid = <79>; + coresight-name = "coresight-tpdm-dl-south-cmb"; + + clocks = <&aoss_qmp>; + status = "disabled"; + clock-names = "apb_pclk"; + qcom,cmb-msr-skip; + + out-ports { + port { + tpdm_dl_south1_out_funnel_dl_south: endpoint { + remote-endpoint = + <&funnel_dl_south_in_tpdm_dl_south1>; + }; + }; + }; + }; + + tpdm_rdpm: tpdm@10c00000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c00000 0x1000>; + reg-names = "tpdm-base"; + + atid = <79>; + coresight-name = "coresight-tpdm-rdpm"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,cmb-msr-skip; + status = "disabled"; + + out-ports { + port { + tpdm_rdpm_out_funnel_dl_center_1: endpoint { + remote-endpoint = + <&funnel_dl_center_1_in_tpdm_rdpm>; + }; + }; + }; + }; + + tpdm_rdpm_mx: tpdm@10c01000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c01000 0x1000>; + reg-names = "tpdm-base"; + + atid = <79>; + coresight-name = "coresight-tpdm-rdpm-mx"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,cmb-msr-skip; + status = "disabled"; + + out-ports { + port { + tpdm_rdpm_mx_out_funnel_dl_center_1: endpoint { + remote-endpoint = + <&funnel_dl_center_1_in_tpdm_rdpm_mx>; + }; + }; + }; + }; + + tpdm_llm_silver: tpdm@128a0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x128a0000 0x1000>; + reg-names = "tpdm-base"; + + atid = <66>; + coresight-name = "coresight-tpdm-llm-silver"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_llm_silver_out_tpda_apss_0: endpoint { + remote-endpoint = + <&tpda_apss_0_in_tpdm_llm_silver>; + }; + }; + }; + }; + + tpdm_actpm: tpdm@12860000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x12860000 0x1000>; + reg-names = "tpdm-base"; + + atid = <66>; + coresight-name = "coresight-tpdm-actpm"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_apss0_out_tpda_apss_3: endpoint { + remote-endpoint = + <&tpda_apss_3_in_tpdm_apss0>; + }; + }; + }; + }; + + tpdm_apss: tpdm@12861000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x12861000 0x1000>; + reg-names = "tpdm-base"; + + atid = <66>; + coresight-name = "coresight-tpdm-apss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_apps1_out_tpda_apss_4: endpoint { + remote-endpoint = + <&tpda_apss_4_in_tpdm_apps1>; + }; + }; + }; + }; + + tpdm_modem_0: tpdm@10800000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10800000 0x1000>; + reg-names = "tpdm-base"; + + atid = <67>; + coresight-name = "coresight-tpdm-modem-0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_modem_0_out_tpda_modem_0: endpoint { + remote-endpoint = + <&tpda_modem_0_in_tpdm_modem_0>; + }; + }; + }; + }; + + tpdm_modem_1: tpdm@10801000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10801000 0x1000>; + reg-names = "tpdm-base"; + + atid = <67>; + coresight-name = "coresight-tpdm-modem-1"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,cmb-msr-skip; + + out-ports { + port { + tpdm_modem_1_out_tpda_modem_1: endpoint { + remote-endpoint = + <&tpda_modem_1_in_tpdm_modem_1>; + }; + }; + }; + }; + + modem_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-modem-etm0"; + qcom,inst-id = <2>; + + atid = <36 37>; + out-ports { + port { + modem_etm0_out_funnel_modem_q6_dup: endpoint { + remote-endpoint = + <&funnel_modem_q6_dup_in_modem_etm0>; + }; + }; + }; + }; + + modem2_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-modem2-etm0"; + qcom,inst-id = <11>; + + atid = <39>; + out-ports { + port { + modem2_etm0_out_funnel_modem: endpoint { + remote-endpoint = + <&funnel_modem_in_modem2_etm0>; + }; + }; + }; + }; + + modem_diag: modem_diag { + compatible = "arm,coresight-dummy-source"; + coresight-name = "coresight-modem-diag"; + qcom,dummy-source; + + atid = <50>; + out-ports { + port { + modem_diag_out_funnel_modem_q6: endpoint { + remote-endpoint = + <&funnel_modem_q6_in_modem_diag>; + }; + }; + }; + }; + + tpdm_wcss: tpdm@109A4000 { + compatible = "arm,coresight-dummy-source"; + qcom,dummy-source; + + atid = <24>; + coresight-name = "coresight-tpdm-wcss"; + + out-ports { + port { + tpdm_wcss_out_funnel_dl_south: endpoint { + remote-endpoint = + <&funnel_dl_south_in_tpdm_wcss>; + }; + }; + }; + }; + + tpdm_tmess_prng: tpdm@10cc9000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10cc9000 0x1000>; + reg-names = "tpdm-base"; + + atid = <85>; + coresight-name = "coresight-tpdm-tmess-prng"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_tmess_prng_out_tpda_tmess_0: endpoint { + remote-endpoint = + <&tpda_tmess_0_in_tpdm_tmess_prng>; + }; + }; + }; + }; + + tpdm_tmess_0: tpdm@10cc0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10cc0000 0x1000>; + reg-names = "tpdm-base"; + + atid = <85>; + coresight-name = "coresight-tpdm-tmess-0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_tmess_0_out_tpda_tmess_1: endpoint { + remote-endpoint = + <&tpda_tmess_1_in_tpdm_tmess_0>; + }; + }; + }; + }; + + tpdm_tmess_1: tpdm@10cc1000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10cc1000 0x1000>; + reg-names = "tpdm-base"; + + atid = <85>; + coresight-name = "coresight-tpdm-tmess-1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_tmess_1_out_tpda_tmess_2: endpoint { + remote-endpoint = + <&tpda_tmess_2_in_tpdm_tmess_1>; + }; + }; + }; + }; + + tpdm_wpss: tpdm@10c70000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c70000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-wpss-dsb"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_wpss_out_funnel_wpss: endpoint { + remote-endpoint = + <&funnel_wpss_in_tpdm_wpss>; + }; + }; + }; + }; + + tpdm_wpss1: tpdm@10c71000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c71000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-wpss-cmb"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_wpss_1_out_funnel_wpss: endpoint { + remote-endpoint = + <&funnel_wpss_in_tpdm_wpss_1>; + }; + }; + }; + }; + + wpss_etm: wpss_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-wpss-etm0"; + qcom,inst-id = <3>; + atid = <44>; + + out-ports { + port { + wpss_etm0_out_funnel_wpss: endpoint { + remote-endpoint = + <&funnel_wpss_in_wpss_etm0>; + }; + }; + }; + }; + + funnel_wpss: funnel@10c73000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10c73000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-wpss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_wpss_in_tpdm_wpss: endpoint { + remote-endpoint = + <&tpdm_wpss_out_funnel_wpss>; + }; + }; + + port@1 { + reg = <1>; + funnel_wpss_in_tpdm_wpss_1: endpoint { + remote-endpoint = + <&tpdm_wpss_1_out_funnel_wpss>; + }; + }; + + port@2 { + reg = <2>; + funnel_wpss_in_wpss_etm0: endpoint { + remote-endpoint = + <&wpss_etm0_out_funnel_wpss>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_wpss_out_tpda_dl_center_5: endpoint { + remote-endpoint = + <&tpda_dl_center_5_in_funnel_wpss>; + source = <&tpdm_wpss>; + }; + }; + + port@1 { + reg = <1>; + funnel_wpss_out_tpda_dl_center_6: endpoint { + remote-endpoint = + <&tpda_dl_center_6_in_funnel_wpss>; + source = <&tpdm_wpss1>; + }; + }; + + port@2 { + reg = <2>; + funnel_wpss_out_funnel_dl_center: endpoint { + remote-endpoint = + <&funnel_dl_center_in_funnel_wpss>; + source = <&wpss_etm>; + }; + }; + + }; + }; + + funnel_lpass_lpi: funnel@10b44000 { + compatible = "arm,coresight-static-funnel"; + coresight-name = "coresight-funnel-lpass_lpi"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_lpass_lpi_in_audio_etm0: endpoint { + remote-endpoint = + <&audio_etm0_out_funnel_lpass_lpi>; + }; + }; + + port@1 { + reg = <1>; + funnel_lpass_lpi_in_lpass_stm: endpoint { + remote-endpoint = + <&lpass_stm_out_funnel_lpass_lpi>; + }; + }; + + port@5 { + reg = <5>; + funnel_lpass_lpi_in_tpdm_lpass_lpi: endpoint { + remote-endpoint = + <&tpdm_lpass_lpi_out_funnel_lpass_lpi>; + }; + }; + + }; + + out-ports { + port { + funnel_lpass_lpi_out_funnel_aoss: endpoint { + remote-endpoint = + <&funnel_aoss_in_funnel_lpass_lpi>; + }; + }; + + }; + }; + + funnel_gfx_dl: funnel@10902000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10902000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-gfx_dl"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + funnel_gfx_dl_in_tpdm_gpu: endpoint { + remote-endpoint = + <&tpdm_gpu_out_funnel_gfx_dl>; + }; + }; + + }; + + out-ports { + port { + funnel_gfx_out_tpda_dl_center2_17: endpoint { + remote-endpoint = + <&tpda_dl_center2_17_in_funnel_gfx>; + }; + }; + + }; + }; + + + funnel_lpass: funnel@10846000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10846000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-lpass"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + funnel_lpass_in_tpdm_lpass: endpoint { + remote-endpoint = + <&tpdm_lpass_out_funnel_lpass>; + }; + }; + + }; + + out-ports { + port { + funnel_lpass_out_tpda_dl_lpass_2: endpoint { + remote-endpoint = + <&tpda_dl_lpass_2_in_funnel_lpass>; + }; + }; + + }; + }; + + funnel_ddr_ch01: funnel@10d22000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10d22000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-ddr_ch01"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + funnel_ddr_ch01_in_tpdm_ddr_ch01: endpoint { + remote-endpoint = + <&tpdm_ddr_ch01_out_funnel_ddr_ch01>; + }; + }; + + }; + + out-ports { + port { + funnel_ddr_ch01_out_funnel_ddr_dl0: endpoint { + remote-endpoint = + <&funnel_ddr_dl0_in_funnel_ddr_ch01>; + }; + }; + + }; + }; + + funnel_ddr_dl0: funnel@10d03000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10d03000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-ddr_dl0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_ddr_dl0_in_funnel_ddr_ch01: endpoint { + remote-endpoint = + <&funnel_ddr_ch01_out_funnel_ddr_dl0>; + }; + }; + + port@2 { + reg = <2>; + funnel_ddr_dl0_in_tpdm_ddr_dl0: endpoint { + remote-endpoint = + <&tpdm_ddr_dl0_out_funnel_ddr_dl0>; + }; + }; + + port@3 { + reg = <3>; + funnel_ddr_dl0_in_tpdm_shrm: endpoint { + remote-endpoint = + <&tpdm_shrm_out_funnel_ddr_dl0>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_ddr_out_tpda_dl_center_9: endpoint { + remote-endpoint = + <&tpda_dl_center_9_in_funnel_ddr>; + source = <&tpdm_ddr_ch01>; + }; + }; + + port@1 { + reg = <1>; + funnel_ddr_out_tpda_dl_center_11: endpoint { + remote-endpoint = + <&tpda_dl_center_11_in_funnel_ddr>; + source = <&tpdm_ddr>; + }; + }; + + port@2 { + reg = <2>; + funnel_ddr_out_tpda_dl_center_12: endpoint { + remote-endpoint = + <&tpda_dl_center_12_in_funnel_ddr>; + source = <&tpdm_shrm>; + }; + }; + + }; + }; + + funnel_dlct_1: funnel@10c02000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10c02000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dlct1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + funnel_dl_center_1_in_tpdm_rdpm: endpoint { + remote-endpoint = + <&tpdm_rdpm_out_funnel_dl_center_1>; + }; + }; + + port@2 { + reg = <2>; + funnel_dl_center_1_in_tpdm_rdpm_mx: endpoint { + remote-endpoint = + <&tpdm_rdpm_mx_out_funnel_dl_center_1>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_dl_center_1_out_tpda_dl_center_10: endpoint { + remote-endpoint = + <&tpda_dl_center_10_in_funnel_dl_center_1>; + source = <&tpdm_rdpm>; + }; + }; + + port@1 { + reg = <1>; + funnel_dl_center_1_out_tpda_dl_center_11: endpoint { + remote-endpoint = + <&tpda_dl_center_11_in_funnel_dl_center_1>; + source = <&tpdm_rdpm_mx>; + }; + }; + }; + }; + + tpda_tmess: tpda@10cc4000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x10cc4000 0x1000>; + reg-names = "tpda-base"; + + qcom,cmb-elem-size = <0 64>, + <1 64>, + <2 32>; + qcom,dsb-elem-size = <1 32>; + + qcom,tpda-atid = <85>; + coresight-name = "coresight-tpda-tmess"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_tmess_0_in_tpdm_tmess_prng: endpoint { + remote-endpoint = + <&tpdm_tmess_prng_out_tpda_tmess_0>; + }; + }; + + port@1 { + reg = <1>; + tpda_tmess_1_in_tpdm_tmess_0: endpoint { + remote-endpoint = + <&tpdm_tmess_0_out_tpda_tmess_1>; + }; + }; + + port@2 { + reg = <2>; + tpda_tmess_2_in_tpdm_tmess_1: endpoint { + remote-endpoint = + <&tpdm_tmess_1_out_tpda_tmess_2>; + }; + }; + + }; + + out-ports { + + port { + tpda_tmess_out_funnel_tmess: endpoint { + remote-endpoint = + <&funnel_tmess_in_tpda_tmess>; + }; + }; + + }; + }; + + funnel_tmess: funnel@10cc5000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10cc5000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-tmess"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + funnel_tmess_in_tpda_tmess: endpoint { + remote-endpoint = + <&tpda_tmess_out_funnel_tmess>; + }; + }; + + }; + + out-ports { + port { + funnel_tmess_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_funnel_tmess>; + }; + }; + + }; + }; + + tpda_modem: tpda@10803000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x10803000 0x1000>; + reg-names = "tpda-base"; + + qcom,tpda-atid = <67>; + qcom,dsb-elem-size = <0 32>; + qcom,cmb-elem-size = <0 64>; + + coresight-name = "coresight-tpda-modem"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_modem_0_in_tpdm_modem_0: endpoint { + remote-endpoint = + <&tpdm_modem_0_out_tpda_modem_0>; + }; + }; + + port@1 { + reg = <1>; + tpda_modem_1_in_tpdm_modem_1: endpoint { + remote-endpoint = + <&tpdm_modem_1_out_tpda_modem_1>; + }; + }; + + }; + + out-ports { + + port { + tpda_modem_out_funnel_modem: endpoint { + remote-endpoint = + <&funnel_modem_in_tpda_modem>; + }; + }; + + }; + }; + + funnel_modem_q6_dup: funnel@1080d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x1080d000 0x1000>, + <0x1080c000 0x1000>; + reg-names = "funnel-base-dummy", "funnel-base-real"; + + coresight-name = "coresight-funnel-modem_q6_dup"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,duplicate-funnel; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_modem_q6_dup_in_modem_etm0: endpoint { + remote-endpoint = + <&modem_etm0_out_funnel_modem_q6_dup>; + }; + }; + + }; + + out-ports { + port { + funnel_modem_q6_dup_out_funnel_modem_q6: endpoint { + remote-endpoint = + <&funnel_modem_q6_in_funnel_modem_q6_dup>; + }; + }; + + }; + }; + + funnel_modem_q6: funnel@1080c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x1080c000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-modem_q6"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + funnel_modem_q6_in_funnel_modem_q6_dup: endpoint { + remote-endpoint = + <&funnel_modem_q6_dup_out_funnel_modem_q6>; + }; + }; + + port@2 { + reg = <2>; + funnel_modem_q6_in_modem_diag: endpoint { + remote-endpoint = + <&modem_diag_out_funnel_modem_q6>; + }; + }; + + }; + + out-ports { + port { + funnel_modem_q6_out_funnel_modem: endpoint { + remote-endpoint = + <&funnel_modem_in_funnel_modem_q6>; + }; + }; + + }; + }; + + funnel_modem: funnel@10804000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10804000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-modem"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + funnel_modem_in_modem2_etm0: endpoint { + remote-endpoint = + <&modem2_etm0_out_funnel_modem>; + }; + }; + + port@0 { + reg = <0>; + funnel_modem_in_tpda_modem: endpoint { + remote-endpoint = + <&tpda_modem_out_funnel_modem>; + }; + }; + + port@3 { + reg = <3>; + funnel_modem_in_funnel_modem_q6: endpoint { + remote-endpoint = + <&funnel_modem_q6_out_funnel_modem>; + }; + }; + + }; + + out-ports { + port { + funnel_modem_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_modem>; + }; + }; + + }; + }; + + tpda_apss: tpda@12863000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x12863000 0x1000>; + reg-names = "tpda-base"; + + qcom,tpda-atid = <66>; + qcom,dsb-elem-size = <4 32>; + qcom,cmb-elem-size = <0 32>, + <3 64>; + + coresight-name = "coresight-tpda-apss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_apss_0_in_tpdm_llm_silver: endpoint { + remote-endpoint = + <&tpdm_llm_silver_out_tpda_apss_0>; + }; + }; + + port@3 { + reg = <3>; + tpda_apss_3_in_tpdm_apss0: endpoint { + remote-endpoint = + <&tpdm_apss0_out_tpda_apss_3>; + }; + }; + + port@4 { + reg = <4>; + tpda_apss_4_in_tpdm_apps1: endpoint { + remote-endpoint = + <&tpdm_apps1_out_tpda_apss_4>; + }; + }; + + }; + + out-ports { + port { + tpda_apss_out_funnel_apss: endpoint { + remote-endpoint = + <&funnel_apss_in_tpda_apss>; + }; + }; + + }; + }; + + funnel_apss: funnel@12810000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x12810000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-apss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_apss_in_funnel_ete: endpoint { + remote-endpoint = + <&funnel_ete_out_funnel_apss>; + }; + }; + + port@3 { + reg = <3>; + funnel_apss_in_tpda_apss: endpoint { + remote-endpoint = + <&tpda_apss_out_funnel_apss>; + }; + }; + + }; + + out-ports { + port { + funnel_apss_out_funnel_dl_center: endpoint { + remote-endpoint = + <&funnel_dl_center_in_funnel_apss>; + }; + }; + + }; + }; + + tpda_dl_center: tpda@10c2b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x10c2b000 0x1000>; + reg-names = "tpda-base"; + + qcom,tpda-atid = <78>; + + qcom,dsb-elem-size = <5 32>, + <9 32>, + <11 32>, + <20 32>, + <21 32>, + <25 32>, + <26 32>; + + qcom,cmb-elem-size = <6 32>, + <11 32>, + <12 64>, + <19 64>, + <22 32>, + <24 64>, + <25 64>, + <27 64>; + + coresight-name = "coresight-tpda-dlct0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@5 { + reg = <5>; + tpda_dl_center_5_in_funnel_wpss: endpoint { + remote-endpoint = + <&funnel_wpss_out_tpda_dl_center_5>; + }; + }; + + port@6 { + reg = <6>; + tpda_dl_center_6_in_funnel_wpss: endpoint { + remote-endpoint = + <&funnel_wpss_out_tpda_dl_center_6>; + }; + }; + + port@9 { + reg = <9>; + tpda_dl_center_9_in_funnel_ddr: endpoint { + remote-endpoint = + <&funnel_ddr_out_tpda_dl_center_9>; + }; + }; + + port@c { + reg = <11>; + tpda_dl_center_11_in_funnel_ddr: endpoint { + remote-endpoint = + <&funnel_ddr_out_tpda_dl_center_11>; + }; + }; + + port@d { + reg = <12>; + tpda_dl_center_12_in_funnel_ddr: endpoint { + remote-endpoint = + <&funnel_ddr_out_tpda_dl_center_12>; + }; + }; + + port@13 { + reg = <19>; + tpda_dl_center_19_in_tpdm_prng: endpoint { + remote-endpoint = + <&tpdm_prng_out_tpda_dl_center_19>; + }; + }; + + port@14 { + reg = <20>; + tpda_dl_center_20_in_tpdm_qm: endpoint { + remote-endpoint = + <&tpdm_qm_out_tpda_dl_center_20>; + }; + }; + + port@15 { + reg = <21>; + tpda_dl_center_21_in_tpdm_gcc: endpoint { + remote-endpoint = + <&tpdm_gcc_out_tpda_dl_center_21>; + }; + }; + + port@16 { + reg = <22>; + tpda_dl_center_22_in_tpdm_vsense: endpoint { + remote-endpoint = + <&tpdm_vsense_out_tpda_dl_center_22>; + }; + }; + + port@18 { + reg = <24>; + tpda_dl_center_24_in_tpdm_ipa: endpoint { + remote-endpoint = + <&tpdm_ipa_out_tpda_dl_center_24>; + }; + }; + + port@19 { + reg = <25>; + tpda_dl_center_25_in_tpdm_pimem: endpoint { + remote-endpoint = + <&tpdm_pimem_out_tpda_dl_center_25>; + }; + }; + + port@1a { + reg = <26>; + tpda_dl_center_26_in_tpdm_dlct: endpoint { + remote-endpoint = + <&tpdm_dlct_out_tpda_dl_center_26>; + }; + }; + + port@1b { + reg = <27>; + tpda_dl_center_27_in_tpdm_ipcc: endpoint { + remote-endpoint = + <&tpdm_ipcc_out_tpda_dl_center_27>; + }; + }; + + }; + + out-ports { + + port { + tpda_dl_center_out_funnel_dl_center: endpoint { + remote-endpoint = + <&funnel_dl_center_in_tpda_dl_center>; + }; + }; + + }; + }; + + funnel_dlct0: funnel@10c2c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10c2c000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dlct0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_dl_center_in_tpda_dl_center: endpoint { + remote-endpoint = + <&tpda_dl_center_out_funnel_dl_center>; + }; + }; + + port@4 { + reg = <4>; + funnel_dl_center_in_funnel_wpss: endpoint { + remote-endpoint = + <&funnel_wpss_out_funnel_dl_center>; + }; + }; + + port@7 { + reg = <7>; + funnel_dl_center_in_funnel_apss: endpoint { + remote-endpoint = + <&funnel_apss_out_funnel_dl_center>; + }; + }; + }; + + out-ports { + port { + funnel_dl_center_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_dl_center>; + }; + }; + + }; + }; + + funnel_dl_south: funnel@109c3000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x109c3000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dl_south"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + funnel_dl_south_in_tpdm_dl_south0: endpoint { + remote-endpoint = + <&tpdm_dl_south0_out_funnel_dl_south>; + }; + }; + + port@3 { + reg = <3>; + funnel_dl_south_in_tpdm_dl_south1: endpoint { + remote-endpoint = + <&tpdm_dl_south1_out_funnel_dl_south>; + }; + }; + + port@4 { + reg = <4>; + funnel_dl_south_in_tpdm_wcss: endpoint { + remote-endpoint = + <&tpdm_wcss_out_funnel_dl_south>; + }; + }; + + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_dl_south_out_tpda_dl_center2_7: endpoint { + remote-endpoint = + <&tpda_dl_center2_7_in_funnel_dl_south>; + source = <&tpdm_dl_south0>; + }; + }; + + port@1 { + reg = <1>; + funnel_dl_south_out_tpda_dl_center2_8: endpoint { + remote-endpoint = + <&tpda_dl_center2_8_in_funnel_dl_south>; + source = <&tpdm_dl_south1>; + }; + }; + + port@2 { + reg = <2>; + funnel_dl_south_out_funnel_dl_center2: endpoint { + remote-endpoint = + <&funnel_dl_center2_in_funnel_dl_south>; + }; + }; + }; + }; + + tpda_dl_center2: tpda@10ac3000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x10ac3000 0x1000>; + reg-names = "tpda-base"; + + qcom,tpda-atid = <79>; + + qcom,dsb-elem-size = <7 32>, + <17 32>, + <26 32>; + + qcom,cmb-elem-size = <8 64>, + <13 64>, + <14 64>, + <27 64>; + + coresight-name = "coresight-tpda-dlct2"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@7 { + reg = <7>; + tpda_dl_center2_7_in_funnel_dl_south: endpoint { + remote-endpoint = + <&funnel_dl_south_out_tpda_dl_center2_7>; + }; + }; + + port@8 { + reg = <8>; + tpda_dl_center2_8_in_funnel_dl_south: endpoint { + remote-endpoint = + <&funnel_dl_south_out_tpda_dl_center2_8>; + }; + }; + + + port@d { + reg = <13>; + tpda_dl_center_10_in_funnel_dl_center_1: endpoint { + remote-endpoint = + <&funnel_dl_center_1_out_tpda_dl_center_10>; + }; + }; + + port@e { + reg = <14>; + tpda_dl_center_11_in_funnel_dl_center_1: endpoint { + remote-endpoint = + <&funnel_dl_center_1_out_tpda_dl_center_11>; + }; + }; + + port@11 { + reg = <17>; + tpda_dl_center2_17_in_funnel_gfx: endpoint { + remote-endpoint = + <&funnel_gfx_out_tpda_dl_center2_17>; + }; + }; + + port@1a { + reg = <26>; + tpda_dl_center2_26_in_tpdm_dlct0: endpoint { + remote-endpoint = + <&tpdm_dlct0_out_tpda_dl_center2_26>; + }; + }; + + port@1b { + reg = <27>; + tpda_dl_center2_27_in_tpdm_dlct1: endpoint { + remote-endpoint = + <&tpdm_dlct1_out_tpda_dl_center2_27>; + }; + }; + + }; + + out-ports { + + port { + tpda_dl_center2_out_funnel_dl_center2: endpoint { + remote-endpoint = + <&funnel_dl_center2_in_tpda_dl_center2>; + }; + }; + + }; + }; + + + funnel_dl_center2: funnel@10ac4000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10ac4000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dlct2"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_dl_center2_in_tpda_dl_center2: endpoint { + remote-endpoint = + <&tpda_dl_center2_out_funnel_dl_center2>; + }; + }; + + port@4 { + reg = <4>; + funnel_dl_center2_in_funnel_dl_south: endpoint { + remote-endpoint = + <&funnel_dl_south_out_funnel_dl_center2>; + }; + }; + + port@6 { + reg = <6>; + funnel_dl_center2_in_funnel_dl_lpass: endpoint { + remote-endpoint = + <&funnel_dl_lpass_out_funnel_dl_center2>; + }; + }; + + }; + + out-ports { + port { + funnel_dl_center2_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_dl_center2>; + }; + }; + + }; + }; + + tpda_dl_west: tpda@10c4a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x10c4a000 0x1000>; + reg-names = "tpda-base"; + + qcom,tpda-atid = <101>; + coresight-name = "coresight-tpda-dl-west"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,cmb-elem-size = <0 32>, + <10 32>; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_dl_west_in_tpdm_sdcc2: endpoint { + remote-endpoint = + <&tpdm_sdcc2_out_tpda_dl_west>; + }; + }; + + port@10 { + reg = <10>; + tpda_dl_west_in_tpdm_dl_west: endpoint { + remote-endpoint = + <&tpdm_dl_west_out_tpda_dl_west>; + }; + }; + + }; + + out-ports { + + port { + tpda_dl_west_out_funnel_dl_west: endpoint { + remote-endpoint = + <&funnel_dl_west_in_tpda_dl_west>; + }; + }; + + }; + }; + + funnel_dl_west: funnel@10c4b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10c4b000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dl-west"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + + port { + funnel_dl_west_in_tpda_dl_west: endpoint { + remote-endpoint = + <&tpda_dl_west_out_funnel_dl_west>; + }; + }; + + }; + + out-ports { + port { + funnel_dl_west_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_dl_west>; + }; + }; + + }; + }; + + + + tpda_dl_lpass: tpda@10c3a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x10c3a000 0x1000>; + reg-names = "tpda-base"; + + qcom,tpda-atid = <74>; + coresight-name = "coresight-tpda-dl-lpass"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,cmb-elem-size = <0 32>; + qcom,dsb-elem-size = <2 32>, + <10 32>; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_dl_lpass_0_in_tpdm_sdcc: endpoint { + remote-endpoint = + <&tpdm_sdcc_out_tpda_dl_lpass_0>; + }; + }; + + port@2 { + reg = <2>; + tpda_dl_lpass_2_in_funnel_lpass: endpoint { + remote-endpoint = + <&funnel_lpass_out_tpda_dl_lpass_2>; + }; + }; + + port@10 { + reg = <10>; + tpda_dl_lpass_10_in_tpdm_dl_lpass: endpoint { + remote-endpoint = + <&tpdm_dl_lpass_out_tpda_dl_lpass_10>; + }; + }; + + }; + + out-ports { + + port { + tpda_dl_lpass_out_funnel_dl_lpass: endpoint { + remote-endpoint = + <&funnel_dl_lpass_in_tpda_dl_lpass>; + }; + }; + + }; + }; + + funnel_dl_lpass: funnel@10c3b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10c3b000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dl-lpass"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + + port { + funnel_dl_lpass_in_tpda_dl_lpass: endpoint { + remote-endpoint = + <&tpda_dl_lpass_out_funnel_dl_lpass>; + }; + }; + + }; + + out-ports { + port { + funnel_dl_lpass_out_funnel_dl_center2: endpoint { + remote-endpoint = + <&funnel_dl_center2_in_funnel_dl_lpass>; + }; + }; + + }; + }; + + tpda_qdss: tpda@10004000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x10004000 0x1000>; + reg-names = "tpda-base"; + + qcom,tpda-atid = <65>; + coresight-name = "coresight-tpda-qdss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-elem-size = <0 32>, + <1 32>; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_qdss_0_in_tpdm_dcc: endpoint { + remote-endpoint = + <&tpdm_dcc_out_tpda_qdss_0>; + }; + }; + + port@1 { + reg = <1>; + tpda_qdss_1_in_tpdm_spdm: endpoint { + remote-endpoint = + <&tpdm_spdm_out_tpda_qdss_1>; + }; + }; + + + }; + + out-ports { + + port { + tpda_qdss_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_tpda_qdss>; + }; + }; + + }; + }; + + funnel_in0: funnel@10041000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10041000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in0_in_snoc: endpoint { + remote-endpoint = + <&snoc_out_funnel_in0>; + }; + }; + + port@1 { + reg = <1>; + funnel_in0_in_funnel_tmess: endpoint { + remote-endpoint = + <&funnel_tmess_out_funnel_in0>; + }; + }; + + port@6 { + reg = <6>; + funnel_in0_in_tpda_qdss: endpoint { + remote-endpoint = + <&tpda_qdss_out_funnel_in0>; + }; + }; + + port@7 { + reg = <7>; + funnel_in0_in_stm: endpoint { + remote-endpoint = + <&stm_out_funnel_in0>; + }; + }; + }; + + out-ports { + port { + funnel_in0_out_funnel_qdss: endpoint { + remote-endpoint = + <&funnel_qdss_in_funnel_in0>; + }; + }; + + }; + }; + + funnel_in1: funnel@10042000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10042000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + funnel_in1_in_funnel_modem: endpoint { + remote-endpoint = + <&funnel_modem_out_funnel_in1>; + }; + }; + + port@5 { + reg = <5>; + funnel_in1_in_funnel_dl_west: endpoint { + remote-endpoint = + <&funnel_dl_west_out_funnel_in1>; + }; + }; + + + port@6 { + reg = <6>; + funnel_in1_in_funnel_dl_center: endpoint { + remote-endpoint = + <&funnel_dl_center_out_funnel_in1>; + }; + }; + + port@7 { + reg = <7>; + funnel_in1_in_funnel_dl_center2: endpoint { + remote-endpoint = + <&funnel_dl_center2_out_funnel_in1>; + }; + }; + + }; + + out-ports { + port { + funnel_in1_out_funnel_qdss: endpoint { + remote-endpoint = + <&funnel_qdss_in_funnel_in1>; + }; + }; + + }; + }; + + funnel_merg: funnel@10045000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10045000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-merg"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + funnel_qdss_in_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_out_funnel_qdss>; + }; + }; + + port@0 { + reg = <0>; + funnel_qdss_in_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_out_funnel_qdss>; + }; + }; + + }; + + out-ports { + port { + funnel_qdss_out_funnel_aoss: endpoint { + remote-endpoint = + <&funnel_aoss_in_funnel_qdss>; + }; + }; + + }; + }; + + tpda_aoss: tpda@10b08000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x10b08000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-aoss"; + + qcom,tpda-atid = <71>; + qcom,cmb-elem-size = <0 64>, + <1 64>, + <2 64>, + <3 64>; + + qcom,dsb-elem-size = <4 32>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_aoss_0_in_tpdm_swao_prio_0: endpoint { + remote-endpoint = + <&tpdm_swao_prio_0_out_tpda_aoss_0>; + }; + }; + + port@1 { + reg = <1>; + tpda_aoss_1_in_tpdm_swao_prio_1: endpoint { + remote-endpoint = + <&tpdm_swao_prio_1_out_tpda_aoss_1>; + }; + }; + + port@2 { + reg = <2>; + tpda_aoss_2_in_tpdm_swao_prio_2: endpoint { + remote-endpoint = + <&tpdm_swao_prio_2_out_tpda_aoss_2>; + }; + }; + + port@3 { + reg = <3>; + tpda_aoss_3_in_tpdm_swao_prio_3: endpoint { + remote-endpoint = + <&tpdm_swao_prio_3_out_tpda_aoss_3>; + }; + }; + + port@4 { + reg = <4>; + tpda_aoss_4_in_tpdm_swao: endpoint { + remote-endpoint = + <&tpdm_swao_out_tpda_aoss_4>; + }; + }; + + }; + + out-ports { + + port { + tpda_aoss_out_funnel_aoss: endpoint { + remote-endpoint = + <&funnel_aoss_in_tpda_aoss>; + }; + }; + + }; + }; + + funnel_aoss: funnel@10b04000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10b04000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-aoss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@5 { + reg = <5>; + funnel_aoss_in_funnel_lpass_lpi: endpoint { + remote-endpoint = + <&funnel_lpass_lpi_out_funnel_aoss>; + }; + }; + + port@6 { + reg = <6>; + funnel_aoss_in_tpda_aoss: endpoint { + remote-endpoint = + <&tpda_aoss_out_funnel_aoss>; + }; + }; + + port@7 { + reg = <7>; + funnel_aoss_in_funnel_qdss: endpoint { + remote-endpoint = + <&funnel_qdss_out_funnel_aoss>; + }; + }; + }; + + out-ports { + port { + funnel_aoss_out_tmc_etf: endpoint { + remote-endpoint = + <&tmc_etf_in_funnel_aoss>; + }; + }; + + }; + }; + + dummy_eud: dummy_sink { + compatible = "arm,coresight-dummy-sink"; + + coresight-name = "coresight-eud"; + + qcom,dummy-sink; + in-ports { + port { + eud_in_replicator_swao: endpoint { + remote-endpoint = + <&replicator_swao_out_eud>; + }; + }; + }; + }; + + tmc_etf: tmc@10b05000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb961>; + reg = <0x10b05000 0x1000>; + reg-names = "tmc-base"; + + coresight-name = "coresight-tmc-etf"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + tmc_etf_in_funnel_aoss: endpoint { + remote-endpoint = + <&funnel_aoss_out_tmc_etf>; + }; + }; + }; + + out-ports { + port { + tmc_etf_out_replicator_swao: endpoint { + remote-endpoint = + <&replicator_swao_in_tmc_etf>; + }; + }; + }; + }; + + replicator_swao: replicator@10b06000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + + reg = <0x10b06000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator_swao"; + + qcom,replicator-loses-context; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + in-ports { + port { + replicator_swao_in_tmc_etf: endpoint { + remote-endpoint = + <&tmc_etf_out_replicator_swao>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + replicator_swao_out_replicator_qdss: endpoint { + remote-endpoint = + <&replicator_qdss_in_replicator_swao>; + }; + }; + + port@1 { + reg = <1>; + replicator_swao_out_eud: endpoint { + remote-endpoint = + <&eud_in_replicator_swao>; + }; + }; + }; + }; + + replicator_qdss: replicator@10046000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + + reg = <0x10046000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator_qdss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + in-ports { + port { + replicator_qdss_in_replicator_swao: endpoint { + remote-endpoint = + <&replicator_swao_out_replicator_qdss>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + replicator_qdss_out_replicator_etr: endpoint { + remote-endpoint = + <&replicator_etr_in_replicator_qdss>; + }; + }; + }; + }; + + replicator_etr: replicator@1004e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + + reg = <0x1004e000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator_etr"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + replicator_etr_in_replicator_qdss: endpoint { + remote-endpoint = + <&replicator_qdss_out_replicator_etr>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_etr_out_tmc_etr: endpoint { + remote-endpoint = + <&tmc_etr_in_replicator_etr>; + }; + }; + + port@1 { + reg = <1>; + replicator_etr_out_tmc_etr1: endpoint { + remote-endpoint = + <&tmc_etr1_in_replicator_etr>; + }; + }; + }; + }; + + tmc_etr: tmc@10048000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb961>; + + reg = <0x10048000 0x1000>, + <0x10064000 0x16000>; + reg-names = "tmc-base", "bam-base"; + + qcom,iommu-dma = "bypass"; + iommus = <&apps_smmu 0x04e0 0>, + <&apps_smmu 0x0520 0>; + + qcom,iommu-dma-addr-pool = <0x0 0xffc00000>; + + qcom,sw-usb; + dma-coherent; + coresight-name = "coresight-tmc-etr"; + + coresight-csr = <&csr>; + csr-atid-offset = <0xf8>; + csr-irqctrl-offset = <0x6c>; + byte-cntr-name = "byte-cntr"; + byte-cntr-class-name = "coresight-tmc-etr-stream"; + + interrupts = ; + interrupt-names = "byte-cntr-irq"; + + arm,scatter-gather; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + tmc_etr_in_replicator_etr: endpoint { + remote-endpoint = + <&replicator_etr_out_tmc_etr>; + }; + }; + }; + }; + + tmc_etr1: tmc@1004f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb961>; + + reg = <0x1004f000 0x1000>; + reg-names = "tmc-base"; + + coresight-name = "coresight-tmc-etr1"; + + iommus = <&apps_smmu 0x0500 0>; + qcom,iommu-dma-addr-pool = <0x0 0xffc00000>; + dma-coherent; + + coresight-csr = <&csr>; + csr-atid-offset = <0x108>; + csr-irqctrl-offset = <0x70>; + byte-cntr-name = "byte-cntr1"; + byte-cntr-class-name = "coresight-tmc-etr1-stream"; + + interrupts = ; + interrupt-names = "byte-cntr-irq"; + + arm,scatter-gather; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + tmc_etr1_in_replicator_etr: endpoint { + remote-endpoint = + <&replicator_etr_out_tmc_etr1>; + }; + }; + }; + }; + + csr: csr@10001000 { + compatible = "qcom,coresight-csr"; + + reg = <0x10001000 0x1000>; + reg-names = "csr-base"; + + coresight-name = "coresight-csr"; + qcom,usb-bam-support; + qcom,perflsheot-set-support; + qcom,hwctrl-set-support; + qcom,set-byte-cntr-support; + qcom,blk-size = <1>; + }; + + swao_csr: csr@10b11000 { + compatible = "qcom,coresight-csr"; + + reg = <0x10b11000 0x1000>, + <0x10b110f8 0x50>; + reg-names = "csr-base", "msr-base"; + + coresight-name = "coresight-swao-csr"; + qcom,timestamp-support; + qcom,msr-support; + qcom,blk-size = <1>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + qc_cti: cti@10010000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10010000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-qc_cti"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cti-gpio-trigout = <16>; + pinctrl-names = "cti-trigout-pctrl"; + pinctrl-0 = <&trigout_a>; + }; + + cti0: cti@10c2a000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10c2a000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-cti0"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + south_cti: cti@109C2000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x109C2000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-dl_south_cti0"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + ddr_dl_0_cti_0: cti@10d02000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10d02000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-ddr_dl_0_cti_0"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + ddr_dl_1_cti_0: cti@10d0c000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10d0c000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-ddr_dl_1_cti_0"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + ddr_ch01_dl_cti_0: cti@10d21000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10d21000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-ddr_ch01_dl_cti_0"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + lpass_dl_cti: cti@10845000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10845000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-lpass_dl_cti"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + gpu_isdb_cti: cti@10961000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10961000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-gpu_isdb_cti"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + gpu_cortex_m3: cti@10962000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10962000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-gpu_cortex_m3"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + turing_dl_cti_0: cti@10982000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10982000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-turing_dl_cti_0"; + + status = "disabled"; + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + turing_q6_cti: cti@1098b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x1098b000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-turing_q6_cti"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + wlan_q6_cti: cti@10C7B000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10C7B000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-wlan_q6_cti"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + swao_cti: cti@10b00000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10b00000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-swao_cti"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,extended_cti; + }; + + cortex_m3: cti@10b13000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10b13000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-cortex_m3"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + lpass_lpi_cti: cti@10b41000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10b41000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-lpass_lpi_cti"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + lpass_q6_cti: cti@10b4b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10b4b000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-lpass_q6_cti"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + apss_cti0: cti@128e0000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x128e0000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-apss_cti0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + apss_cti1: cti@128f0000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x128f0000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-apss_cti1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + apss_cti2: cti@12900000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x12900000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-apss_cti2"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + riscv_cti: cti@1282b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x1282b000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-riscv_cti"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + mss_q6_cti: cti@1080b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x1080b000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-mss_q6_cti"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + mss_vq6_cti: cti@10813000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10813000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-mss_vq6_cti"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tmess_cti_0: cti@10cc2000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10cc2000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-tmess_cti_0"; + + qcom,extended_cti; + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tmess_cti_1: cti@10cc3000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10cc3000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-tmess_cti_1"; + + qcom,extended_cti; + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tmess_cpu: cti@10cd1000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10cd1000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-tmess_cpu"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + apss_atb_cti: cti@12862000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x12862000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-apss_atb_cti"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + ddrss_shrm2: cti@10d11000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10d11000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-ddrss_shrm2"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + Sierra_A6: cti@10C13000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10C13000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-sierra_a6"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + wcss0: cti@109AC000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x109AC000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-sierra_a6"; + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + wcss1: cti@109ad000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x109ad000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-wcss1"; + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + wcss2: cti@109Ae000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x109Ae000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-wcss2"; + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + ipcb_tgu: tgu@10b0e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb999>; + + reg = <0x10b0e000 0x1000>; + reg-names = "tgu-base"; + + tgu-steps = <3>; + tgu-conditions = <4>; + tgu-regs = <4>; + tgu-timer-counters = <8>; + + coresight-name = "coresight-tgu-ipcb"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + spmi_tgu0: tgu@10b0f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb999>; + + reg = <0x10b0f000 0x1000>; + reg-names = "tgu-base"; + + tgu-steps = <3>; + tgu-conditions = <4>; + tgu-regs = <9>; + tgu-timer-counters = <8>; + + coresight-name = "coresight-tgu-spmi0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + spmi_tgu1: tgu@10b10000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb999>; + + reg = <0x10b10000 0x1000>; + reg-names = "tgu-base"; + + tgu-steps = <3>; + tgu-conditions = <4>; + tgu-regs = <9>; + tgu-timer-counters = <8>; + + coresight-name = "coresight-tgu-spmi1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + etm0 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x12040000 0x1000>; + cpu = <&CPU0>; + + coresight-name = "coresight-etm0"; + qcom,skip-power-up; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + atid = <1>; + out-ports { + port { + ete0_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete0>; + }; + }; + }; + }; + + etm1 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x12140000 0x1000>; + cpu = <&CPU1>; + + coresight-name = "coresight-etm1"; + qcom,skip-power-up; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + atid = <2>; + out-ports { + port { + ete1_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete1>; + }; + }; + }; + }; + + etm2 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x12240000 0x1000>; + cpu = <&CPU2>; + + coresight-name = "coresight-etm2"; + qcom,skip-power-up; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + atid = <3>; + out-ports { + port { + ete2_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete2>; + }; + }; + }; + }; + + etm3 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x12340000 0x1000>; + cpu = <&CPU3>; + + coresight-name = "coresight-etm3"; + qcom,skip-power-up; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + atid = <4>; + out-ports { + port { + ete3_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete3>; + }; + }; + }; + }; + + etm4 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x12440000 0x1000>; + cpu = <&CPU4>; + + coresight-name = "coresight-etm4"; + qcom,skip-power-up; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + atid = <5>; + out-ports { + port { + ete4_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete4>; + }; + }; + }; + }; + + etm5 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x12540000 0x1000>; + cpu = <&CPU5>; + + coresight-name = "coresight-etm5"; + qcom,skip-power-up; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + atid = <6>; + out-ports { + port { + ete5_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete5>; + }; + }; + }; + }; + + etm6 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x12640000 0x1000>; + cpu = <&CPU6>; + + coresight-name = "coresight-etm6"; + qcom,skip-power-up; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + atid = <7>; + out-ports { + port { + ete6_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete6>; + }; + }; + }; + }; + + etm7 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x12740000 0x1000>; + cpu = <&CPU7>; + + coresight-name = "coresight-etm7"; + qcom,skip-power-up; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + atid = <8>; + out-ports { + port { + ete7_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete7>; + }; + }; + }; + }; + + funnel_etm: funnel@12800000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x12800000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-etm"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_ete_out_funnel_apss: endpoint { + remote-endpoint = + <&funnel_apss_in_funnel_ete>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_ete_in_ete0: endpoint { + remote-endpoint = + <&ete0_out_funnel_ete>; + }; + }; + + port@1 { + reg = <1>; + funnel_ete_in_ete1: endpoint { + remote-endpoint = + <&ete1_out_funnel_ete>; + }; + }; + + port@2 { + reg = <2>; + funnel_ete_in_ete2: endpoint { + remote-endpoint = + <&ete2_out_funnel_ete>; + }; + }; + + port@3 { + reg = <3>; + funnel_ete_in_ete3: endpoint { + remote-endpoint = + <&ete3_out_funnel_ete>; + }; + }; + + port@4 { + reg = <4>; + funnel_ete_in_ete4: endpoint { + remote-endpoint = + <&ete4_out_funnel_ete>; + }; + }; + + port@5 { + reg = <5>; + funnel_ete_in_ete5: endpoint { + remote-endpoint = + <&ete5_out_funnel_ete>; + }; + }; + + port@6 { + reg = <6>; + funnel_ete_in_ete6: endpoint { + remote-endpoint = + <&ete6_out_funnel_ete>; + }; + }; + + port@7 { + reg = <7>; + funnel_ete_in_ete7: endpoint { + remote-endpoint = + <&ete7_out_funnel_ete>; + }; + }; + }; + }; +}; diff --git a/qcom/ravelin-debug.dtsi b/qcom/ravelin-debug.dtsi new file mode 100644 index 00000000..c0b1e3eb --- /dev/null +++ b/qcom/ravelin-debug.dtsi @@ -0,0 +1,1584 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0xc00000>; + }; +}; + +&soc { + dcc: dcc_v2@100ff000 { + compatible = "qcom,dcc-v2"; + reg = <0x100ff000 0x1000>, + <0x10080000 0x18000>; + + qcom,transaction_timeout = <0>; + reg-names = "dcc-base", "dcc-ram-base"; + dcc-ram-offset = <0>; + + link_list_0 { + qcom,curr-link-list = <6>; + qcom,data-sink = "sram"; + qcom,link-list = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + link_list_1 { + qcom,curr-link-list = <4>; + qcom,data-sink = "sram"; + qcom,link-list = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + }; + + mem_dump { + compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; + + c0_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x0>; + }; + + c100_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x1>; + }; + + c200_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x2>; + }; + + c300_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x3>; + }; + + c400_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x4>; + }; + + c500_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x5>; + }; + + c600_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x6>; + }; + + c700_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x7>; + }; + + cpuss_reg { + qcom,dump-size = <0x30000>; + qcom,dump-id = <0xef>; + }; + + l1_icache0 { + qcom,dump-size = <0x10900>; + qcom,dump-id = <0x60>; + }; + + l1_icache100 { + qcom,dump-size = <0x10900>; + qcom,dump-id = <0x61>; + }; + + l1_icache200 { + qcom,dump-size = <0x10900>; + qcom,dump-id = <0x62>; + }; + + l1_icache300 { + qcom,dump-size = <0x10900>; + qcom,dump-id = <0x63>; + }; + + l1_icache400 { + qcom,dump-size = <0x10900>; + qcom,dump-id = <0x64>; + }; + + l1_icache500 { + qcom,dump-size = <0x10900>; + qcom,dump-id = <0x65>; + }; + + l1_icache600 { + qcom,dump-size = <0x15100>; + qcom,dump-id = <0x66>; + }; + + l1_icache700 { + qcom,dump-size = <0x15100>; + qcom,dump-id = <0x67>; + }; + + l1_dcache0 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x80>; + }; + + l1_dcache100 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x81>; + }; + + l1_dcache200 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x82>; + }; + + l1_dcache300 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x83>; + }; + + l1_dcache400 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x84>; + }; + + l1_dcache500 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x85>; + }; + + l1_dcache600 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x86>; + }; + + l1_dcache700 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x87>; + }; + + l1_itlb600 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x26>; + }; + + l1_itlb700 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x27>; + }; + + l1_dtlb600 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x46>; + }; + + l1_dtlb700 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x47>; + }; + + l2_cache600 { + qcom,dump-size = <0x48100>; + qcom,dump-id = <0xc6>; + }; + + l2_cache700 { + qcom,dump-size = <0x48100>; + qcom,dump-id = <0xc7>; + }; + + l2_tlb0 { + qcom,dump-size = <0x5b00>; + qcom,dump-id = <0x120>; + }; + + l2_tlb100 { + qcom,dump-size = <0x5b00>; + qcom,dump-id = <0x121>; + }; + + l2_tlb200 { + qcom,dump-size = <0x5b00>; + qcom,dump-id = <0x122>; + }; + + l2_tlb300 { + qcom,dump-size = <0x5b00>; + qcom,dump-id = <0x123>; + }; + + l2_tlb400 { + qcom,dump-size = <0x5b00>; + qcom,dump-id = <0x124>; + }; + + l2_tlb500 { + qcom,dump-size = <0x5b00>; + qcom,dump-id = <0x125>; + }; + + l2_tlb600 { + qcom,dump-size = <0x6100>; + qcom,dump-id = <0x126>; + }; + + l2_tlb700 { + qcom,dump-size = <0x6100>; + qcom,dump-id = <0x127>; + }; + + rpmh { + qcom,dump-size = <0x400000>; + qcom,dump-id = <0xec>; + }; + + rpm_sw { + qcom,dump-size = <0x28000>; + qcom,dump-id = <0xea>; + }; + + pmic { + qcom,dump-size = <0x200000>; + qcom,dump-id = <0xe4>; + }; + + fcm { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xee>; + }; + + etf_swao { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xf1>; + }; + + etr_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + etfswao_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x102>; + }; + + etr1_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x105>; + }; + + misc_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + + etf_lpass { + qcom,dump-size = <0x4000>; + qcom,dump-id = <0xf4>; + }; + + etflpass_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x104>; + }; + + osm_reg { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x163>; + }; + + pcu_reg { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x164>; + }; + + fsm_data { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x165>; + }; + }; +}; diff --git a/qcom/ravelin-dma-heaps.dtsi b/qcom/ravelin-dma-heaps.dtsi new file mode 100644 index 00000000..004a2ef0 --- /dev/null +++ b/qcom/ravelin-dma-heaps.dtsi @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + qcom,dma-heaps { + compatible = "qcom,dma-heaps"; + qcom,user_contig { + qcom,dma-heap-name = "qcom,user-contig"; + qcom,dma-heap-type = ; + memory-region = <&user_contig_mem>; + }; + + qcom,qseecom { + qcom,dma-heap-name = "qcom,qseecom"; + qcom,dma-heap-type = ; + memory-region = <&qseecom_mem>; + }; + + qcom,qseecom_ta { + qcom,dma-heap-name = "qcom,qseecom-ta"; + qcom,dma-heap-type = ; + memory-region = <&qseecom_ta_mem>; + }; + + qcom,audio_ml { + qcom,dma-heap-name = "qcom,audio-ml"; + qcom,dma-heap-type = ; + memory-region = <&audio_cma_mem>; + }; + + non_secure_display_dma_buf: qcom,display { + qcom,dma-heap-name = "qcom,display"; + qcom,dma-heap-type = ; + qcom,max-align = <9>; + memory-region = <&non_secure_display_memory>; + }; + }; +}; + diff --git a/qcom/ravelin-idp-overlay.dts b/qcom/ravelin-idp-overlay.dts new file mode 100644 index 00000000..e46b8a1e --- /dev/null +++ b/qcom/ravelin-idp-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "ravelin-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin IDP"; + compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp"; + qcom,msm-id = <568 0x10000>, <602 0x10000>; + qcom,board-id = <34 0>; +}; diff --git a/qcom/ravelin-idp-wcn3950-amoled-rcm-overlay.dts b/qcom/ravelin-idp-wcn3950-amoled-rcm-overlay.dts new file mode 100644 index 00000000..8f917453 --- /dev/null +++ b/qcom/ravelin-idp-wcn3950-amoled-rcm-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "ravelin-idp-wcn3950-amoled-rcm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin WCN3950 IDP + AMOLED + RCM"; + compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp"; + qcom,msm-id = <568 0x10000>, <602 0x10000>; + qcom,board-id = <34 2>; +}; diff --git a/qcom/ravelin-idp-wcn3950-amoled-rcm.dts b/qcom/ravelin-idp-wcn3950-amoled-rcm.dts new file mode 100644 index 00000000..49f04598 --- /dev/null +++ b/qcom/ravelin-idp-wcn3950-amoled-rcm.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin.dtsi" +#include "ravelin-idp-wcn3950-amoled-rcm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin WCN3950 IDP + AMOLED + RCM"; + compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp"; + qcom,board-id = <34 2>; +}; diff --git a/qcom/ravelin-idp-wcn3950-amoled-rcm.dtsi b/qcom/ravelin-idp-wcn3950-amoled-rcm.dtsi new file mode 100644 index 00000000..fec6cbb4 --- /dev/null +++ b/qcom/ravelin-idp-wcn3950-amoled-rcm.dtsi @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-idp.dtsi" + +&soc { +}; + +&qupv3_se1_i2c { + status = "disabled"; +}; + +&qupv3_se1_spi { + #address-cells = <1>; + #size-cells = <0>; + status = "ok"; + qcom,touch-active = "goodix,gt9916S"; + + goodix-berlin@0 { + reg = <0>; + spi-max-frequency = <1000000>; + + goodix,avdd-name = "avdd"; + avdd-supply = <&L4E>; + + interrupt-parent = <&tlmm>; + interrupts = <91 0x2008>; + goodix,reset-gpio = <&tlmm 90 0x00>; + goodix,irq-gpio = <&tlmm 91 0x2008>; + goodix,irq-flags = <2>; + goodix,panel-max-x = <1080>; + goodix,panel-max-y = <2400>; + goodix,panel-max-w = <255>; + goodix,panel-max-p = <4096>; + goodix,firmware-name = "goodix_firmware_spi.bin"; + goodix,config-name = "goodix_cfg_group_spi.bin"; + + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", "pmx_ts_release"; + pinctrl-0 = <&ts_spi_active>; + pinctrl-1 = <&ts_spi_int_suspend &ts_spi_reset_suspend>; + pinctrl-2 = <&ts_spi_release>; + + qcom,touch-environment = "pvm"; + }; +}; diff --git a/qcom/ravelin-idp-wcn3988-4gb-overlay.dts b/qcom/ravelin-idp-wcn3988-4gb-overlay.dts new file mode 100644 index 00000000..cc8bf2e9 --- /dev/null +++ b/qcom/ravelin-idp-wcn3988-4gb-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "ravelin-idp-wcn3988-4gb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin IDP 4GB DDR + WCN3988"; + compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp"; + qcom,msm-id = <568 0x10000>, <602 0x10000>; + qcom,board-id = <34 0x601>; +}; diff --git a/qcom/ravelin-idp-wcn3988-4gb.dts b/qcom/ravelin-idp-wcn3988-4gb.dts new file mode 100644 index 00000000..c186a13d --- /dev/null +++ b/qcom/ravelin-idp-wcn3988-4gb.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin-4gb.dtsi" +#include "ravelin-idp-wcn3988-4gb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin IDP 4GB DDR + WCN3988"; + compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp"; + qcom,board-id = <34 0x601>; +}; diff --git a/qcom/ravelin-idp-wcn3988-4gb.dtsi b/qcom/ravelin-idp-wcn3988-4gb.dtsi new file mode 100644 index 00000000..122b06c7 --- /dev/null +++ b/qcom/ravelin-idp-wcn3988-4gb.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-idp.dtsi" diff --git a/qcom/ravelin-idp.dts b/qcom/ravelin-idp.dts new file mode 100644 index 00000000..451a3e72 --- /dev/null +++ b/qcom/ravelin-idp.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin.dtsi" +#include "ravelin-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin IDP"; + compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp"; + qcom,board-id = <34 0>; +}; diff --git a/qcom/ravelin-idp.dtsi b/qcom/ravelin-idp.dtsi new file mode 100644 index 00000000..5de7dd7b --- /dev/null +++ b/qcom/ravelin-idp.dtsi @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-pmic-overlay.dtsi" +#include "ravelin-pm7250b.dtsi" +#include "ravelin-thermal-overlay.dtsi" + +&soc { +}; + +&qupv3_se8_i2c { + awinic@64 { + reg = <0x64>; + + awinic,red { + awinic,name = "red"; + awinic,id = <0>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + + awinic,green { + awinic,name = "green"; + awinic,id = <1>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + + awinic,blue { + awinic,name = "blue"; + awinic,id = <2>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + }; +}; + +&qupv3_se1_i2c { + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + qcom,i2c-touch-active = "focaltech,fts_ts"; + + focaltech@38 { + reg = <0x38>; + + interrupt-parent = <&tlmm>; + interrupts = <13 0x2008>; + focaltech,reset-gpio = <&tlmm 12 0x00>; + focaltech,irq-gpio = <&tlmm 13 0x2008>; + focaltech,display-coords = <0 0 1080 2408>; + focaltech,max-touch-number = <10>; + focaltech,ic-type = <0x8726081C>; + focaltech,touch-type = "primary"; + + pinctrl-names = "pmx_ts_active","pmx_ts_suspend","pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + + focaltech,trusted-touch-mode = "vm_mode"; + focaltech,touch-environment = "pvm"; + focaltech,trusted-touch-type = "primary"; + focaltech,trusted-touch-spi-irq = <566>; + focaltech,trusted-touch-io-bases = <0x984000 0x910000>; + focaltech,trusted-touch-io-sizes = <0x1000 0x4000>; + focaltech,trusted-touch-vm-gpio-list = <&tlmm 10 0 &tlmm 11 0 + &tlmm 12 0 &tlmm 13 0x2008>; + }; +}; + +&sdhc_1 { + status = "ok"; + vdd-supply = <&L5E>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L19B>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-current-level = <0 325000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; +}; + +&sdhc_2 { + status = "ok"; + vdd-supply = <&L24B>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + /* + * min/max voltages are voted on L24B/L28B and L24B/L28B_PBS + * regulators will only be voted for enabling/disabling conditions + * to support FR84471 for chipsets where PMIC doesn't support + * PBS ram sequence to turn OFF regulators automatically on + * multicard tray removal and these new regulator resources are + * exposed by PMIC team as part of this FR. + */ + vdd-en-dis-supply = <&L24B_PBS>; + + vdd-io-supply = <&L28B>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + vdd-io-en-dis-supply = <&L28B_PBS>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>; +}; + +&ufsphy_mem { + /* + * Here parrot phy is used for ravelin as it + * do not have its own list for module load and + * hence compatible is using parrot. + * We have plan to improve this by making phy binary + * target independent. + */ + compatible = "qcom,ufs-phy-qmp-v4-waipio"; + + vdda-phy-supply = <&L5B>; + vdda-pll-supply = <&L16B>; + vdda-phy-max-microamp = <88530>; + vdda-pll-max-microamp = <18310>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + + vcc-supply = <&L5E>; + vcc-max-microamp = <1056000>; + + vccq-supply = <&L13B>; + vccq-max-microamp = <750000>; + + vccq2-supply = <&L19B>; + vccq2-max-microamp = <750000>; + + qcom,vddp-ref-clk-supply = <&L13B>; + qcom,vddp-ref-clk-max-microamp = <100>; + + /* + * ufs-dev-types and nvmem entries are for ufs device + * identification using nvmem interface. Use number of + * ufs devices supported for ufs-dev-types, and nvmem handle + * added by pmic for sdam register. + * + * Default value taken by driver is bit[0] = 0 for 3.x and + * bit[0] = 1 for 2.x driver code takes this as default case. + * + * But Bit value to identify ufs device is not consistent + * across the targets it could be bit[0] = 0/1 for UFS2.x/3x + * and vice versa. If the bit[0] value is not same as default + * value used in driver and if its reverted then use flag + * qcom,ufs-dev-revert to identify ufs device. + */ + ufs-dev-types = <2>; + qcom,ufs-dev-revert; + nvmem-cells = <&ufs_dev>, <&boot_config>; + nvmem-cell-names = "ufs_dev", "boot_conf"; + + status = "ok"; +}; + +&battery_charger { + qcom,thermal-mitigation-step = <500000>; + qcom,wireless-charging-not-supported; +}; diff --git a/qcom/ravelin-low-memory.dtsi b/qcom/ravelin-low-memory.dtsi new file mode 100644 index 00000000..201d98f4 --- /dev/null +++ b/qcom/ravelin-low-memory.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&trust_ui_vm_mem { + status = "disabled"; +}; + +&trust_ui_vm_qrtr { + status = "disabled"; +}; + +&trust_ui_vm_vblk0_ring { + status = "disabled"; +}; + +&trust_ui_vm_swiotlb { + status = "disabled"; +}; + +&non_secure_display_dma_buf { + status = "disabled"; +}; + +&non_secure_display_memory { + status = "disabled"; +}; + +&soc { + qcom,guestvm_loader@e0b00000 { + status = "disabled"; + }; + + qrtr-gunyah { + status = "disabled"; + }; + + qcom,virtio_backend@0 { + status = "disabled"; + }; +}; diff --git a/qcom/ravelin-msm-rdbg.dtsi b/qcom/ravelin-msm-rdbg.dtsi new file mode 100644 index 00000000..e15e0053 --- /dev/null +++ b/qcom/ravelin-msm-rdbg.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + /* smp2p information */ + qcom,smp2p_interrupt_rdbg_2_out { + compatible = "qcom,smp2p-interrupt-rdbg-2-out"; + qcom,smem-states = <&smp2p_rdbg2_out 0>; + qcom,smem-state-names = "rdbg-smp2p-out"; + }; + + qcom,smp2p_interrupt_rdbg_2_in { + compatible = "qcom,smp2p-interrupt-rdbg-2-in"; + interrupts-extended = <&smp2p_rdbg2_in 0 0>; + interrupt-names = "rdbg-smp2p-in"; + }; +}; diff --git a/qcom/ravelin-pcie.dtsi b/qcom/ravelin-pcie.dtsi new file mode 100644 index 00000000..2b751c85 --- /dev/null +++ b/qcom/ravelin-pcie.dtsi @@ -0,0 +1,277 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&soc { + pcie0: qcom,pcie@1c00000 { + compatible = "qcom,pci-msm"; + + reg = <0x01c00000 0x3000>, + <0x01c06000 0x2000>, + <0x60000000 0xf1d>, + <0x60000f20 0xa8>, + <0x60001000 0x1000>, + <0x60100000 0x100000>; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf"; + + cell-index = <0>; + linux,pci-domain = <0>; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>; + + interrupt-parent = <&pcie0>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + + interrupt-map = <0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + + msi-parent = <&pcie0_msi>; + + perst-gpio = <&tlmm 32 GPIO_ACTIVE_HIGH>; + wake-gpio = <&tlmm 31 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pcie0_perst_default + &pcie0_clkreq_default + &pcie0_wake_default>; + pinctrl-1 = <&pcie0_perst_default + &pcie0_clkreq_sleep + &pcie0_wake_default>; + + gdsc-vdd-supply = <&gcc_pcie_0_gdsc>; + vreg-1p8-supply = <&L16B>; + vreg-0p9-supply = <&L5B>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + vreg-mx-supply = <&VDD_MX_LEVEL>; + qcom,vreg-1p8-voltage-level = <1200000 1200000 15070>; + qcom,vreg-0p9-voltage-level = <880000 880000 46890>; + qcom,vreg-cx-voltage-level = ; + qcom,vreg-mx-voltage-level = ; + qcom,bw-scale = /* Gen1 */ + ; + + interconnect-names = "icc_path"; + interconnects = <&pcie_anoc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, + <&gcc GCC_PCIE_0_PIPE_DIV2_CLK>, + <&gcc GCC_QMIP_PCIE_AHB_CLK>, + <&pcie_0_pipe_clk>; + clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", + "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", + "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", + "pcie_0_ldo", "pcie_0_slv_q2a_axi_clk", + "pcie_phy_refgen_clk", + "pcie_ddrss_sf_tbu_clk", + "pcie_aggre_noc_0_axi_clk", "pcie_cfg_noc_pcie_anoc_ahb_clk", + "pcie_pipe_clk_mux", "pcie_0_pipe_div2_clk", + "pcie_qmip_pcie_ahb_clk", "pcie_pipe_clk_ext_src"; + max-clock-frequency-hz = <0>, <0>, <0>, <19200000>, <0>, <0>, + <0>, <0>, <0>, <0>, <0>, <100000000>, + <0>, <0>, <0>, <0>; + + resets = <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "pcie_0_core_reset", + "pcie_0_phy_reset"; + + dma-coherent; + qcom,smmu-sid-base = <0x1400>; + iommu-map = <0x0 &apps_smmu 0x1400 0x1>, + <0x100 &apps_smmu 0x1401 0x1>; + + qcom,boot-option = <0x1>; + qcom,aux-clk-freq = <20>; /* 19.2 MHz */ + qcom,drv-supported; + qcom,drv-l1ss-timeout-us = <5000>; + qcom,l1-2-th-scale = <2>; + qcom,l1-2-th-value = <150>; + qcom,slv-addr-space-size = <0x4000000>; + qcom,ep-latency = <10>; + qcom,num-parf-testbus-sel = <0xb9>; + qcom,config-recovery; + + qcom,pcie-phy-ver = <107>; + qcom,phy-status-offset = <0x214>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0x240>; + qcom,phy-sequence = <0x0240 0x03 0x0 + 0x0094 0x08 0x0 + 0x0154 0x34 0x0 + 0x016c 0x08 0x0 + 0x0058 0x0f 0x0 + 0x00a4 0x42 0x0 + 0x0110 0x24 0x0 + 0x011c 0x03 0x0 + 0x0118 0xb4 0x0 + 0x010c 0x02 0x0 + 0x01bc 0x11 0x0 + 0x00bc 0x82 0x0 + 0x00d4 0x03 0x0 + 0x00d0 0x55 0x0 + 0x00cc 0x55 0x0 + 0x00b0 0x1a 0x0 + 0x00ac 0x0a 0x0 + 0x00c4 0x68 0x0 + 0x00e0 0x02 0x0 + 0x00dc 0xaa 0x0 + 0x00d8 0xab 0x0 + 0x00b8 0x34 0x0 + 0x00b4 0x14 0x0 + 0x0158 0x01 0x0 + 0x0074 0x06 0x0 + 0x007c 0x16 0x0 + 0x0084 0x36 0x0 + 0x0078 0x06 0x0 + 0x0080 0x16 0x0 + 0x0088 0x36 0x0 + 0x01b0 0x1e 0x0 + 0x01ac 0xca 0x0 + 0x01b8 0x18 0x0 + 0x01b4 0xa2 0x0 + 0x0050 0x07 0x0 + 0x0010 0x01 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x0ee4 0x20 0x0 + 0x0e84 0x75 0x0 + 0x0e90 0x3f 0x0 + 0x115c 0x7f 0x0 + 0x1160 0xff 0x0 + 0x1164 0xbf 0x0 + 0x1168 0x3f 0x0 + 0x116c 0xd8 0x0 + 0x1170 0xdc 0x0 + 0x1174 0xdc 0x0 + 0x1178 0x5c 0x0 + 0x117c 0x34 0x0 + 0x1180 0xa6 0x0 + 0x1190 0x34 0x0 + 0x1194 0x38 0x0 + 0x10d8 0x0f 0x0 + 0x0e3c 0x12 0x0 + 0x0e40 0x01 0x0 + 0x10dc 0x00 0x0 + 0x104c 0x08 0x0 + 0x1050 0x08 0x0 + 0x1044 0xf0 0x0 + 0x11a4 0x38 0x0 + 0x10cc 0xf0 0x0 + 0x10f4 0x07 0x0 + 0x1008 0x09 0x0 + 0x1014 0x05 0x0 + 0x0694 0x00 0x0 + 0x0654 0x00 0x0 + 0x06a8 0x0f 0x0 + 0x0048 0x90 0x0 + 0x0620 0xc1 0x0 + 0x0388 0x77 0x0 + 0x0398 0x0b 0x0 + 0x02dc 0x05 0x0 + 0x0200 0x00 0x0 + 0x0244 0x03 0x0>; + + qcom,parf-debug-reg = <0x01B0 0x0024 0x0028 0x0224 0x0500 + 0x04D0 0x04D4 0x03C0 0x0630 0x0230 + 0x0000>; + + qcom,dbi-debug-reg = <0x0104 0x0110 0x0080 0x0204 0x0730 + 0x0734 0x0738 0x073C>; + + qcom,phy-debug-reg = <0x0068 0x0140 0x0144 0x0148 0x014C + 0x0150 0x0160 0x0178 0x0ED0 0x0EDC + 0x0F34 0x0F38 0x0f3C 0x0F40 0x0F44 + 0x0F48 0x0F4C 0x0F50 0x0F54 0x0F58 + 0x11E8 0x0A00 0x0A04 0x0A08 0x0A0C + 0x0A10 0x0A14 0x0A18 0x0C20 0x0214 + 0x0218 0x021C 0x0220 0x0224 0x0228 + 0x022C 0x0230 0x0234 0x0238 0x023C + 0x0600 0x0604 0x1204 0x1210>; + + status = "disabled"; + pcie0_rp: pcie0_rp { + reg = <0 0 0 0 0>; + }; + }; + + pcie0_msi: qcom,pcie0_msi@0x17210040 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0x17210040 0x0>; + interrupt-parent = <&intc>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + status = "disabled"; + }; +}; diff --git a/qcom/ravelin-pinctrl.dtsi b/qcom/ravelin-pinctrl.dtsi new file mode 100644 index 00000000..fad561c0 --- /dev/null +++ b/qcom/ravelin-pinctrl.dtsi @@ -0,0 +1,1403 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + tlmm: pinctrl@f000000 { + compatible = "qcom,ravelin-tlmm"; + reg = <0xf000000 0x1000000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + wakeup-parent = <&pdc>; + qcom,gpios-reserved = <0 1 2 3>; + + qupv3_se7_2uart_pins: qupv3_se7_2uart_pins { + qupv3_se7_2uart_tx_active: qupv3_se7_2uart_tx_active { + mux { + pins = "gpio22"; + function = "qup1_se2_l2"; + }; + + config { + pins = "gpio22"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se7_2uart_rx_active: qupv3_se7_2uart_rx_active { + mux { + pins = "gpio23"; + function = "qup1_se2_l3"; + }; + + config { + pins = "gpio23"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se7_2uart_sleep: qupv3_se7_2uart_sleep { + mux { + pins = "gpio22", "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio22", "gpio23"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se2_4uart_pins: qupv3_se2_4uart_pins { + qupv3_se2_default_cts: qupv3_se2_default_cts { + mux { + pins = "gpio14"; + function = "gpio"; + }; + + config { + pins = "gpio14"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se2_default_rts: qupv3_se2_default_rts { + mux { + pins = "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio15"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se2_default_tx: qupv3_se2_default_tx { + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se2_default_rx: qupv3_se2_default_rx { + mux { + pins = "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio17"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se2_cts: qupv3_se2_cts { + mux { + pins = "gpio14"; + function = "qup0_se2_l0"; + }; + + config { + pins = "gpio14"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se2_rts: qupv3_se2_rts { + mux { + pins = "gpio15"; + function = "qup0_se2_l1"; + }; + + config { + pins = "gpio15"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se2_tx: qupv3_se2_tx { + mux { + pins = "gpio16"; + function = "qup0_se2_l2"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se2_rx: qupv3_se2_rx { + mux { + pins = "gpio17"; + function = "qup0_se2_l3"; + }; + + config { + pins = "gpio17"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se0_2uart_pins: qupv3_se0_2uart_pins { + qupv3_se0_2uart_tx_active: qupv3_se0_2uart_tx_active { + mux { + pins = "gpio34"; + function = "qup0_se0_l2"; + }; + + config { + pins = "gpio34"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se0_2uart_rx_active: qupv3_se0_2uart_rx_active { + mux { + pins = "gpio35"; + function = "qup0_se0_l3"; + }; + + config { + pins = "gpio35"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se0_2uart_sleep: qupv3_se0_2uart_sleep { + mux { + pins = "gpio34", "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio34", "gpio35"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { + qupv3_se0_i2c_sda_active: qupv3_se0_i2c_sda_active { + mux { + pins = "gpio4"; + function = "qup0_se0_l0"; + }; + + config { + pins = "gpio4"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se0_i2c_scl_active: qupv3_se0_i2c_scl_active { + mux { + pins = "gpio5"; + function = "qup0_se0_l1"; + }; + + config { + pins = "gpio5"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep { + mux { + pins = "gpio4", "gpio5"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se1_i2c_pins: qupv3_se1_i2c_pins { + qupv3_se1_i2c_sda_active: qupv3_se1_i2c_sda_active { + mux { + pins = "gpio10"; + function = "qup0_se1_l0"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se1_i2c_scl_active: qupv3_se1_i2c_scl_active { + mux { + pins = "gpio11"; + function = "qup0_se1_l1"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep { + mux { + pins = "gpio10", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se1_spi_pins: qupv3_se1_spi_pins { + qupv3_se1_spi_miso_active: qupv3_se1_spi_miso_active { + mux { + pins = "gpio10"; + function = "qup0_se1_l0"; + }; + + config { + pins = "gpio10"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se1_spi_mosi_active: qupv3_se1_spi_mosi_active { + mux { + pins = "gpio11"; + function = "qup0_se1_l1"; + }; + + config { + pins = "gpio11"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se1_spi_clk_active: qupv3_se1_spi_clk_active { + mux { + pins = "gpio12"; + function = "qup0_se1_l2"; + }; + + config { + pins = "gpio12"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se1_spi_cs_active: qupv3_se1_spi_cs_active { + mux { + pins = "gpio13"; + function = "qup0_se1_l3"; + }; + + config { + pins = "gpio13"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se1_spi_sleep: qupv3_se1_spi_sleep { + mux { + pins = "gpio10", "gpio11", + "gpio12", "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio10", "gpio11", + "gpio12", "gpio13"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se3_i2c_pins: qupv3_se3_i2c_pins { + qupv3_se3_i2c_sda_active: qupv3_se3_i2c_sda_active { + mux { + pins = "gpio18"; + function = "qup0_se3_l0"; + }; + + config { + pins = "gpio18"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se3_i2c_scl_active: qupv3_se3_i2c_scl_active { + mux { + pins = "gpio19"; + function = "qup0_se3_l1"; + }; + + config { + pins = "gpio19"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep { + mux { + pins = "gpio18", "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se3_spi_pins: qupv3_se3_spi_pins { + qupv3_se3_spi_miso_active: qupv3_se3_spi_miso_active { + mux { + pins = "gpio18"; + function = "qup0_se3_l0"; + }; + + config { + pins = "gpio18"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se3_spi_mosi_active: qupv3_se3_spi_mosi_active { + mux { + pins = "gpio19"; + function = "qup0_se3_l1"; + }; + + config { + pins = "gpio19"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se3_spi_clk_active: qupv3_se3_spi_clk_active { + mux { + pins = "gpio20"; + function = "qup0_se3_l2"; + }; + + config { + pins = "gpio20"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se3_spi_cs_active: qupv3_se3_spi_cs_active { + mux { + pins = "gpio21"; + function = "qup0_se3_l3"; + }; + + config { + pins = "gpio21"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se3_spi_sleep: qupv3_se3_spi_sleep { + mux { + pins = "gpio18", "gpio19", + "gpio20", "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio18", "gpio19", + "gpio20", "gpio21"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se4_i2c_pins: qupv3_se4_i2c_pins { + qupv3_se4_i2c_sda_active: qupv3_se4_i2c_sda_active { + mux { + pins = "gpio8"; + function = "qup0_se4_l0_mira"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se4_i2c_scl_active: qupv3_se4_i2c_scl_active { + mux { + pins = "gpio9"; + function = "qup0_se4_l1_mira"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep { + mux { + pins = "gpio8", "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se4_spi_pins: qupv3_se4_spi_pins { + qupv3_se4_spi_miso_active: qupv3_se4_spi_miso_active { + mux { + pins = "gpio8"; + function = "qup0_se4_l0_mira"; + }; + + config { + pins = "gpio8"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se4_spi_mosi_active: qupv3_se4_spi_mosi_active { + mux { + pins = "gpio9"; + function = "qup0_se4_l1_mira"; + }; + + config { + pins = "gpio9"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se4_spi_clk_active: qupv3_se4_spi_clk_active { + mux { + pins = "gpio6"; + function = "qup0_se4_l2"; + }; + + config { + pins = "gpio6"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se4_spi_cs_active: qupv3_se4_spi_cs_active { + mux { + pins = "gpio7"; + function = "qup0_se4_l3"; + }; + + config { + pins = "gpio7"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se4_spi_sleep: qupv3_se4_spi_sleep { + mux { + pins = "gpio8", "gpio9", + "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9", + "gpio6", "gpio7"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se5_i2c_pins: qupv3_se5_i2c_pins { + qupv3_se5_i2c_sda_active: qupv3_se5_i2c_sda_active { + mux { + pins = "gpio0"; + function = "qup1_se0_l0"; + }; + + config { + pins = "gpio0"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se5_i2c_scl_active: qupv3_se5_i2c_scl_active { + mux { + pins = "gpio1"; + function = "qup1_se0_l1"; + }; + + config { + pins = "gpio1"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se5_spi_pins: qupv3_se5_spi_pins { + qupv3_se5_spi_miso_active: qupv3_se5_spi_miso_active { + mux { + pins = "gpio0"; + function = "qup1_se0_l0"; + }; + + config { + pins = "gpio0"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se5_spi_mosi_active: qupv3_se5_spi_mosi_active { + mux { + pins = "gpio1"; + function = "qup1_se0_l1"; + }; + + config { + pins = "gpio1"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se5_spi_clk_active: qupv3_se5_spi_clk_active { + mux { + pins = "gpio2"; + function = "qup1_se0_l2"; + }; + + config { + pins = "gpio2"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se5_spi_cs_active: qupv3_se5_spi_cs_active { + mux { + pins = "gpio3"; + function = "qup1_se0_l3"; + }; + + config { + pins = "gpio3"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se5_spi_sleep: qupv3_se5_spi_sleep { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se6_i2c_pins: qupv3_se6_i2c_pins { + qupv3_se6_i2c_sda_active: qupv3_se6_i2c_sda_active { + mux { + pins = "gpio50"; + function = "qup1_se1_l0"; + }; + + config { + pins = "gpio50"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se6_i2c_scl_active: qupv3_se6_i2c_scl_active { + mux { + pins = "gpio51"; + function = "qup1_se1_l1"; + }; + + config { + pins = "gpio51"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep { + mux { + pins = "gpio50", "gpio51"; + function = "gpio"; + }; + + config { + pins = "gpio50", "gpio51"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se6_spi_pins: qupv3_se6_spi_pins { + qupv3_se6_spi_miso_active: qupv3_se6_spi_miso_active { + mux { + pins = "gpio50"; + function = "qup1_se1_l0"; + }; + + config { + pins = "gpio50"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se6_spi_mosi_active: qupv3_se6_spi_mosi_active { + mux { + pins = "gpio51"; + function = "qup1_se1_l1"; + }; + + config { + pins = "gpio51"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se6_spi_clk_active: qupv3_se6_spi_clk_active { + mux { + pins = "gpio26"; + function = "qup1_se1_l2"; + }; + + config { + pins = "gpio26"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se6_spi_cs_active: qupv3_se6_spi_cs_active { + mux { + pins = "gpio27"; + function = "qup1_se1_l3"; + }; + + config { + pins = "gpio27"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se6_spi_sleep: qupv3_se6_spi_sleep { + mux { + pins = "gpio50", "gpio51", + "gpio26", "gpio27"; + function = "gpio"; + }; + + config { + pins = "gpio50", "gpio51", + "gpio26", "gpio27"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se8_i2c_pins: qupv3_se8_i2c_pins { + qupv3_se8_i2c_sda_active: qupv3_se8_i2c_sda_active { + mux { + pins = "gpio24"; + function = "qup1_se3_l0"; + }; + + config { + pins = "gpio24"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se8_i2c_scl_active: qupv3_se8_i2c_scl_active { + mux { + pins = "gpio25"; + function = "qup1_se3_l1"; + }; + + config { + pins = "gpio25"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep { + mux { + pins = "gpio24", "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio24", "gpio25"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se8_spi_pins: qupv3_se8_spi_pins { + qupv3_se8_spi_miso_active: qupv3_se8_spi_miso_active { + mux { + pins = "gpio24"; + function = "qup1_se3_l0"; + }; + + config { + pins = "gpio24"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se8_spi_mosi_active: qupv3_se8_spi_mosi_active { + mux { + pins = "gpio25"; + function = "qup1_se3_l1"; + }; + + config { + pins = "gpio25"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se8_spi_clk_active: qupv3_se8_spi_clk_active { + mux { + pins = "gpio51"; + function = "qup1_se3_l2"; + }; + + config { + pins = "gpio51"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se8_spi_cs_active: qupv3_se8_spi_cs_active { + mux { + pins = "gpio50"; + function = "qup1_se3_l3"; + }; + + config { + pins = "gpio50"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se8_spi_sleep: qupv3_se8_spi_sleep { + mux { + pins = "gpio24", "gpio25", + "gpio51", "gpio50"; + function = "gpio"; + }; + + config { + pins = "gpio24", "gpio25", + "gpio51", "gpio50"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se9_i2c_pins: qupv3_se9_i2c_pins { + qupv3_se9_i2c_sda_active: qupv3_se9_i2c_sda_active { + mux { + pins = "gpio91"; + function = "qup1_se4_l0"; + }; + + config { + pins = "gpio91"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se9_i2c_scl_active: qupv3_se9_i2c_scl_active { + mux { + pins = "gpio90"; + function = "qup1_se4_l1"; + }; + + config { + pins = "gpio90"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep { + mux { + pins = "gpio91", "gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio91", "gpio90"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se9_spi_pins: qupv3_se9_spi_pins { + qupv3_se9_spi_miso_active: qupv3_se9_spi_miso_active { + mux { + pins = "gpio91"; + function = "qup1_se4_l0"; + }; + + config { + pins = "gpio91"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se9_spi_mosi_active: qupv3_se9_spi_mosi_active { + mux { + pins = "gpio90"; + function = "qup1_se4_l1"; + }; + + config { + pins = "gpio90"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se9_spi_clk_active: qupv3_se9_spi_clk_active { + mux { + pins = "gpio48"; + function = "qup1_se4_l2"; + }; + + config { + pins = "gpio48"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se9_spi_cs_active: qupv3_se9_spi_cs_active { + mux { + pins = "gpio43"; + function = "qup1_se4_l3"; + }; + + config { + pins = "gpio43"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se9_spi_sleep: qupv3_se9_spi_sleep { + mux { + pins = "gpio91", "gpio90", + "gpio48", "gpio43"; + function = "gpio"; + }; + + config { + pins = "gpio91", "gpio90", + "gpio48", "gpio43"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + /* WSA speaker reset pins */ + spkr_1_sd_n { + spkr_1_sd_n_sleep: spkr_1_sd_n_sleep { + mux { + pins = "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio99"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_1_sd_n_active: spkr_1_sd_n_active { + mux { + pins = "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio99"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + spkr_2_sd_n { + spkr_2_sd_n_sleep: spkr_2_sd_n_sleep { + mux { + pins = "gpio100"; + function = "gpio"; + }; + + config { + pins = "gpio100"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_2_sd_n_active: spkr_2_sd_n_active { + mux { + pins = "gpio100"; + function = "gpio"; + }; + + config { + pins = "gpio100"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + /* WCD reset pin */ + wcd_reset_active: wcd_reset_active { + mux { + pins = "gpio96"; + function = "gpio"; + }; + + config { + pins = "gpio96"; + drive-strength = <16>; + output-high; + }; + }; + + wcd_reset_sleep: wcd_reset_sleep { + mux { + pins = "gpio96"; + function = "gpio"; + }; + + config { + pins = "gpio96"; + drive-strength = <16>; + bias-disable; + output-low; + }; + }; + + sdc1_on: sdc1_on { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_off: sdc1_off { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_on: sdc2_on { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd { + pins = "gpio101"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_off: sdc2_off { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + + sd-cd { + pins = "gpio101"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + trigout_a: trigout_a { + mux { + pins = "gpio26"; + function = "qdss_cti"; + }; + + config { + pins = "gpio26"; + drive-strength = <2>; + bias-disable; + }; + }; + + /* touchscreen pins */ + pmx_ts_active { + ts_active: ts_active { + mux { + pins = "gpio12", "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio12", "gpio13"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + ts_spi_active: ts_spi_active { + mux { + pins = "gpio90", "gpio91"; + function = "gpio"; + }; + + config { + pins = "gpio90", "gpio91"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_reset_suspend { + ts_reset_suspend: ts_reset_suspend { + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + ts_spi_reset_suspend: ts_spi_reset_suspend { + mux { + pins = "gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio90"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_int_suspend { + ts_int_suspend: ts_int_suspend { + mux { + pins = "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio13"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + ts_spi_int_suspend: ts_spi_int_suspend { + mux { + pins = "gpio91"; + function = "gpio"; + }; + + config { + pins = "gpio91"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_release { + ts_release: ts_release { + mux { + pins = "gpio12", "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio12", "gpio13"; + drive-strength = <2>; + bias-disable; + }; + }; + + ts_spi_release: ts_spi_release { + mux { + pins = "gpio90", "gpio91"; + function = "gpio"; + }; + + config { + pins = "gpio90", "gpio91"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + pcie0 { + pcie0_perst_default: pcie0_perst_default { + mux { + pins = "gpio32"; + function = "gpio"; + }; + + config { + pins = "gpio32"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie0_clkreq_default: pcie0_clkreq_default { + mux { + pins = "gpio107"; + function = "pcie0_clk_req"; + }; + + config { + pins = "gpio107"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_wake_default: pcie0_wake_default { + mux { + pins = "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio31"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_clkreq_sleep: pcie0_clkreq_sleep { + mux { + pins = "gpio107"; + function = "gpio"; + }; + + config { + pins = "gpio107"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + usb_phy_ps: usb_phy_ps { + usb3phy_portselect_default: usb3phy_portselect_default { + mux { + pins = "gpio94"; + function = "usb0_phy_ps"; + }; + + config { + pins = "gpio94"; + bias-disable; + drive-strength = <2>; + }; + }; + }; + }; +}; diff --git a/qcom/ravelin-pm7250b.dtsi b/qcom/ravelin-pm7250b.dtsi new file mode 100644 index 00000000..750724d2 --- /dev/null +++ b/qcom/ravelin-pm7250b.dtsi @@ -0,0 +1,355 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include "pm7250b.dtsi" + +&soc { + qcom,pmic_glink { + status = "okay"; + }; + + qcom,pmic_glink_log { + compatible = "qcom,pmic-glink"; + qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS"; + + qcom,battery_debug { + compatible = "qcom,battery-debug"; + }; + + qcom,charger_ulog_glink { + compatible = "qcom,charger-ulog-glink"; + }; + + spmi_glink_debug: qcom,spmi_glink_debug { + compatible = "qcom,spmi-glink-debug"; + #address-cells = <1>; + #size-cells = <0>; + depends-on-supply = <&spmi0_bus>; + + /* Primary SPMI bus */ + spmi@0 { + reg = <0>; + #address-cells = <2>; + #size-cells = <0>; + + qcom,pm7250b-debug@8 { + compatible = "qcom,spmi-pmic"; + reg = <8 SPMI_USID>; + qcom,can-sleep; + }; + }; + }; + }; +}; + +&glink_edge { + qcom,pmic_glink_rpmsg { + qcom,glink-channels = "PMIC_RTR_ADSP_APPS"; + }; + + qcom,pmic_glink_log_rpmsg { + qcom,glink-channels = "PMIC_LOGS_ADSP_APPS"; + qcom,intents = <0x800 5 + 0xc00 3 + 0x2000 1>; + }; +}; + +&battery_charger { + status = "okay"; +}; + +&ucsi { + status = "okay"; +}; + +&altmode { + status = "okay"; +}; + +&spmi0_debug_bus { + qcom,pm7250b-debug@8 { + compatible = "qcom,spmi-pmic"; + reg = <8 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm7250b-debug@9 { + compatible = "qcom,spmi-pmic"; + reg = <9 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; +}; + +&pm7250b_2 { + /* Slave ID - 8 */ + reg = <8 SPMI_USID>; +}; + +&pm7250b_3 { + /* Slave ID - 9 */ + reg = <9 SPMI_USID>; +}; + +&pm7250b_clkdiv { + clocks = <&rpmhcc RPMH_CXO_CLK>; +}; + +&pm7250b_vadc { + interrupts = <0x8 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + + pm7250b_usb_conn_therm { + reg = ; + label = "pm7250b_usb_conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pm7250b_charger_skin_therm { + reg = ; + label = "pm7250b_charger_skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm7250b_adc_tm { + interrupts = <0x8 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, + <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>; + + pm7250b_usb_conn_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pm7250b_charger_skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + socd { + cooling-maps { + socd_cpu_6_7 { + trip = <&socd_trip>; + cooling-device = <&cpu_6_7_pause 1 1>; + }; + + socd_gpu0 { + trip = <&socd_trip>; + cooling-device = <&msm_gpu 2 2>; + }; + }; + }; + + pm7250b-ibat-lvl0 { + trips { + ibat-lvl0 { + temperature = <4000>; + }; + }; + }; + + pm7250b-ibat-lvl1 { + trips { + ibat-lvl1 { + temperature = <5000>; + }; + }; + }; + + pm7250b-bcl-lvl0 { + cooling-maps { + vbat_lte0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_lte_dsc 8 8>; + }; + + vbat_nr0_scg { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_nr_scg_dsc 3 3>; + }; + + vbat_nr0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_nr_dsc 6 6>; + }; + + vbat_cpu_4 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu4_pause 1 1>; + }; + + vbat_cpu_5 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu5_pause 1 1>; + }; + + vbat_cpu_6 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu6_pause 1 1>; + }; + + vbat_gpu0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + }; + }; + + pm7250b-bcl-lvl1 { + cooling-maps { + vbat_lte1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_lte_dsc 255 255>; + }; + + vbat_nr1_scg { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_nr_scg_dsc 255 255>; + }; + + vbat_nr1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_nr_dsc 255 255>; + }; + + vbat_cpu_7 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cpu7_pause 1 1>; + }; + + vbat_gpu1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&msm_gpu 4 4>; + }; + }; + }; + + pm7250b-bcl-lvl2 { + cooling-maps { + vbat_gpu2 { + trip = <&b_bcl_lvl2>; + cooling-device = <&msm_gpu 3 THERMAL_NO_LIMIT>; + }; + }; + }; + + sys-therm-9 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM3_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-therm-7 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM1_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + +&pm7250b_tz { + interrupts = <0x8 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; +}; + +&pm7250b_bcl { + interrupts = <0x8 0x1d 0x0 IRQ_TYPE_EDGE_RISING>, + <0x8 0x1d 0x1 IRQ_TYPE_EDGE_RISING>, + <0x8 0x1d 0x2 IRQ_TYPE_EDGE_RISING>; +}; + +&pm7250b_gpios { + display_panel_supply_ctrl { + display_panel_vddio_default: display_panel_vddio_default { + pins = "gpio11"; + function = "normal"; + input-disable; + output-enable; + bias-disable; + power-source = <0>; + qcom,drive-strength = <2>; + }; + + display_panel_extvdd_default: display_panel_extvdd_default { + pins = "gpio12"; + function = "normal"; + input-disable; + output-enable; + bias-disable; + power-source = <0>; + qcom,drive-strength = <2>; + }; + }; +}; + +&soc { + display_panel_vddio: display_gpio_regulator@1 { + compatible = "qti-regulator-fixed"; + regulator-name = "display_panel_vddio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <233>; + gpio = <&pm7250b_gpios 11 0>; + enable-active-high; + regulator-boot-on; + proxy-supply = <&display_panel_vddio>; + qcom,proxy-consumer-enable; + pinctrl-names = "default"; + pinctrl-0 = <&display_panel_vddio_default>; + }; + + display_panel_extvdd: display_gpio_regulator@2 { + compatible = "qti-regulator-fixed"; + regulator-name = "display_panel_extvdd"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <233>; + gpio = <&pm7250b_gpios 12 0>; + enable-active-high; + regulator-boot-on; + proxy-supply = <&display_panel_extvdd>; + qcom,proxy-consumer-enable; + pinctrl-names = "default"; + pinctrl-0 = <&display_panel_extvdd_default>; + }; +}; diff --git a/qcom/ravelin-pmi632.dtsi b/qcom/ravelin-pmi632.dtsi new file mode 100644 index 00000000..518976db --- /dev/null +++ b/qcom/ravelin-pmi632.dtsi @@ -0,0 +1,326 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include "pmi632.dtsi" + +&soc { + qcom,pmic_glink { + status = "okay"; + }; + + qcom,pmic_glink_log { + compatible = "qcom,pmic-glink"; + qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS"; + + qcom,battery_debug { + compatible = "qcom,battery-debug"; + }; + + qcom,charger_ulog_glink { + compatible = "qcom,charger-ulog-glink"; + }; + + spmi_glink_debug: qcom,spmi_glink_debug { + compatible = "qcom,spmi-glink-debug"; + #address-cells = <1>; + #size-cells = <0>; + depends-on-supply = <&spmi0_bus>; + + /* Primary SPMI bus */ + spmi@0 { + reg = <0>; + #address-cells = <2>; + #size-cells = <0>; + + qcom,pmi632-debug@2 { + compatible = "qcom,spmi-pmic"; + reg = <2 SPMI_USID>; + qcom,can-sleep; + }; + }; + }; + }; +}; + +&glink_edge { + qcom,pmic_glink_rpmsg { + qcom,glink-channels = "PMIC_RTR_ADSP_APPS"; + }; + + qcom,pmic_glink_log_rpmsg { + qcom,glink-channels = "PMIC_LOGS_ADSP_APPS"; + qcom,intents = <0x800 5 + 0xc00 3 + 0x2000 1>; + }; +}; + +&battery_charger { + status = "okay"; +}; + +&ucsi { + status = "okay"; +}; + +&altmode { + status = "disabled"; +}; + +&spmi0_debug_bus { + qcom,pmi632-debug@2 { + compatible = "qcom,spmi-pmic"; + reg = <2 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pmi632-debug@3 { + compatible = "qcom,spmi-pmic"; + reg = <3 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; +}; + +&pmi632_gpios { + usb_conn_therm { + usb_conn_therm_default: usb_conn_therm_default { + pins = "gpio1"; + bias-high-impedance; + }; + }; + + charger_skin_temp { + charger_skin_temp_default: charger_skin_temp_default { + pins = "gpio3"; + bias-high-impedance; + }; + }; + + smb_skin_therm { + smb_skin_therm_default: smb_skin_therm_default { + pins = "gpio4"; + bias-high-impedance; + }; + }; +}; + +&pmi632_vadc { + pinctrl-names = "default"; + pinctrl-0 = <&usb_conn_therm_default &charger_skin_temp_default + &smb_skin_therm_default>; + + pmi632_usb_conn_therm { + reg = ; + label = "pmi632_usb_conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pmi632_charger_skin_temp { + reg = ; + label = "pmi632_charger_skin_temp"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pmi632_smb_skin_therm { + reg = ; + label = "pmi632_smb_skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pmi632_adc_tm { + io-channels = <&pmi632_vadc ADC5_GPIO1_100K_PU>, + <&pmi632_vadc ADC5_GPIO2_100K_PU>, + <&pmi632_vadc ADC5_GPIO3_100K_PU>; + + pmi632_usb_conn_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pmi632_charger_skin_temp { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pmi632_smb_skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + +}; + +&thermal_zones { + socd { + cooling-maps { + socd_cpu_6_7 { + trip = <&socd_trip>; + cooling-device = <&cpu_6_7_pause 1 1>; + }; + + socd_gpu0 { + trip = <&socd_trip>; + cooling-device = <&msm_gpu 2 2>; + }; + }; + }; + + pmi632-bcl-lvl0 { + cooling-maps { + vbat_lte0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_lte_dsc 8 8>; + }; + + vbat_nr0_scg { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_nr_scg_dsc 3 3>; + }; + + vbat_nr0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_nr_dsc 6 6>; + }; + + vbat_cpu_4 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu4_pause 1 1>; + }; + + vbat_cpu_5 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu5_pause 1 1>; + }; + + vbat_cpu_6 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu6_pause 1 1>; + }; + + vbat_gpu0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + }; + }; + + pmi632-bcl-lvl1 { + cooling-maps { + vbat_lte1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_lte_dsc 255 255>; + }; + + vbat_nr1_scg { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_nr_scg_dsc 255 255>; + }; + + vbat_nr1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_nr_dsc 255 255>; + }; + + vbat_cpu_7 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cpu7_pause 1 1>; + }; + + vbat_gpu1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&msm_gpu 4 4>; + }; + }; + }; + + pmi632-bcl-lvl2 { + cooling-maps { + vbat_gpu2 { + trip = <&b_bcl_lvl2>; + cooling-device = <&msm_gpu 3 THERMAL_NO_LIMIT>; + }; + }; + }; + + sys-therm-9 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmi632_adc_tm ADC5_GPIO1_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-therm-7 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmi632_adc_tm ADC5_GPIO2_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-therm-8 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmi632_adc_tm ADC5_GPIO3_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + +&flash_led { + qcom,use-qti-battery-interface; +}; + +&pmi632_lcdb { + status = "ok"; +}; diff --git a/qcom/ravelin-pmic-overlay.dtsi b/qcom/ravelin-pmic-overlay.dtsi new file mode 100644 index 00000000..d6bc3028 --- /dev/null +++ b/qcom/ravelin-pmic-overlay.dtsi @@ -0,0 +1,663 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include + +#include "pmk8350.dtsi" +#include "pm6450.dtsi" + +&soc { + reboot_reason { + compatible = "qcom,reboot-reason"; + nvmem-cells = <&restart_reason>; + nvmem-cell-names = "restart_reason"; + }; + + pmic-pon-log { + compatible = "qcom,pmic-pon-log"; + nvmem = <&pmk8350_sdam_5>; + nvmem-names = "pon_log"; + }; +}; + +&pmk8350 { + /delete-node/ pon_pbs@800; + /delete-node/ pon_hlos@1300; + + pon_hlos@1300 { + compatible = "qcom,pm8998-pon"; + reg = <0x1300>, <0x800>; + reg-names = "pon_hlos", "pon_pbs"; + qcom,log-kpd-event; + + pwrkey { + compatible = "qcom,pmk8350-pwrkey"; + interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + }; + + resin { + compatible = "qcom,pmk8350-resin"; + interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + }; + }; +}; + +&pmk8350_vadc { + pinctrl-names = "default"; + pinctrl-0 = <&quiet_therm_default &wide_rfc_therm_default + &rear_cam_flash_therm_default &pa_therm2_default &pa_therm1_default>; + + /delete-node/ pm8350_ref_gnd; + /delete-node/ pm8350_vref_1p25; + /delete-node/ pm8350_die_temp; + /delete-node/ pm8350_vph_pwr; + + /delete-node/ pm8350b_ref_gnd; + /delete-node/ pm8350b_vref_1p25; + /delete-node/ pm8350b_die_temp; + /delete-node/ pm8350b_vph_pwr; + /delete-node/ pm8350b_vbat_sns; + + /delete-node/ pmr735b_ref_gnd; + /delete-node/ pmr735b_vref_1p25; + /delete-node/ pmr735b_die_temp; + + /delete-node/ pmr735a_ref_gnd; + /delete-node/ pmr735a_vref_1p25; + /delete-node/ pmr735a_die_temp; + + /* PM6450 Channel nodes */ + pm6450_ref_gnd { + reg = ; + label = "pm6450_ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + pm6450_vref_1p25 { + reg = ; + label = "pm6450_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + pm6450_die_temp { + reg = ; + label = "pm6450_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + pm6450_quiet_therm { + reg = ; + label = "pm6450_quiet_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pmk8350_wide_rfc_therm { + reg = ; + label = "pmk8350_wide_rfc_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pm6450_rear_cam_flash_therm { + reg = ; + label = "pm6450_rear_cam_flash_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pm6450_pa_therm2 { + reg = ; + label = "pm6450_pa_therm2"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pmk8350_pa_therm1 { + reg = ; + label = "pmk8350_pa_therm1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + pm8010_e: qcom,pm8010@4 { + compatible = "qcom,spmi-pmic"; + reg = <4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8010e_tz: pm8010-e-temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + }; +}; + +&pmk8350_adc_tm { + io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>, + <&pmk8350_vadc PM6450_ADC7_AMUX1_GPIO2_100K_PU>, + <&pmk8350_vadc PMK8350_ADC7_AMUX_THM2_100K_PU>, + <&pmk8350_vadc PM6450_ADC7_AMUX4_GPIO5_100K_PU>, + <&pmk8350_vadc PM6450_ADC7_AMUX3_GPIO4_100K_PU>, + <&pmk8350_vadc PMK8350_ADC7_AMUX_THM3_100K_PU>; + + pmk8350_xo_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pm6450_quiet_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pmk8350_wide_rfc_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pm6450_rear_cam_flash_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pm6450_pa2_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pmk8350_pa1_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pmk8350_gpios { + wide_rfc_therm { + wide_rfc_therm_default: wide_rfc_therm_default { + pins = "gpio1"; + bias-high-impedance; + }; + }; + + pa_therm1 { + pa_therm1_default: pa_therm1_default { + pins = "gpio2"; + bias-high-impedance; + }; + }; +}; + +&pmk8350_sdam_23 { + adc_scaling: scaling@bf { + reg = <0xbf 0x1>; + bits = <0 2>; + }; +}; + +&pmk8350_sdam_1 { + ufs_dev: ufs_dev@94 { + reg = <0x94 0x1>; + bits = <0 0>; + }; +}; + +&pm6450_gpios { + quiet_therm { + quiet_therm_default: quiet_therm_default { + pins = "gpio2"; + bias-high-impedance; + }; + }; + + rear_cam_flash_therm { + rear_cam_flash_therm_default: rear_cam_flash_therm_default { + pins = "gpio5"; + bias-high-impedance; + }; + }; + + pa_therm2 { + pa_therm2_default: pa_therm2_default { + pins = "gpio4"; + bias-high-impedance; + }; + }; + +}; + +&thermal_zones { + pm8010e_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8010e_tz>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + sys-therm-6 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM1_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-therm-4 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM2_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-therm-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm PM6450_ADC7_AMUX1_GPIO2_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-therm-3 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm PM6450_ADC7_AMUX4_GPIO5_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-therm-11 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm PM6450_ADC7_AMUX3_GPIO4_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-therm-5 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM3_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + +&tlmm { + key_vol_up_default: key_vol_up_default { + mux { + pins = "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + }; + + pm8010m_active: pm8010m-active { + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-pull-up; + output-high; + drive-strength = <2>; + }; + }; + + pm8010n_active: pm8010n-active { + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-pull-up; + output-high; + drive-strength = <2>; + }; + }; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; +}; + +/* + * Each QUP device that's a parent to PMIC must be listed as a critical device + * to GCC + */ +&gcc { + qcom,critical-devices = <&qupv3_se8_i2c>; +}; + +&qupv3_se8_i2c { + #address-cells = <1>; + #size-cells = <0>; + status = "ok"; + + pm8010m@8 { + compatible = "qcom,i2c-pmic"; + reg = <0x8>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pm8010m_active>; + + pm8010-chip@900 { + reg = <0x900>; + + PM8010M_EN: qcom,pm8008-chip-en { + regulator-name = "pm8010m-chip-en"; + }; + }; + + qcom,revid@100 { + reg = <0x100>; + }; + }; + + pm8010m@9 { + compatible = "qcom,i2c-pmic"; + reg = <0x9>; + #address-cells = <1>; + #size-cells = <0>; + + qcom,pm8010m-regulator { + #address-cells = <1>; + #size-cells = <0>; + + pm8008_en-supply = <&PM8010M_EN>; + vdd_l1_l2-supply = <&S8B>; + + L1M: pm8010m_l1: regulator@4000 { + reg = <0x4000>; + regulator-name = "pm8010m_l1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + qcom,min-dropout-voltage = <88000>; + qcom,hpm-min-load = <30000>; + }; + + L2M: pm8010m_l2: regulator@4100 { + reg = <0x4100>; + regulator-name = "pm8010m_l2"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; + qcom,min-dropout-voltage = <80000>; + qcom,hpm-min-load = <30000>; + }; + + L3M: pm8010m_l3: regulator@4200 { + reg = <0x4200>; + regulator-name = "pm8010m_l3"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + qcom,hpm-min-load = <0>; + }; + + L4M: pm8010m_l4: regulator@4300 { + reg = <0x4300>; + regulator-name = "pm8010m_l4"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + qcom,hpm-min-load = <0>; + }; + + L6M: pm8010m_l6: regulator@4500 { + reg = <0x4500>; + regulator-name = "pm8010m_l6"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3000000>; + qcom,hpm-min-load = <0>; + }; + + L7M: pm8010m_l7: regulator@4600 { + reg = <0x4600>; + regulator-name = "pm8010m_l7"; + regulator-min-microvolt = <2650000>; + regulator-max-microvolt = <2950000>; + qcom,hpm-min-load = <0>; + }; + }; + }; + + pm8010n@c { + compatible = "qcom,i2c-pmic"; + reg = <0xc>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pm8010n_active>; + + pm8010-chip@900 { + reg = <0x900>; + + PM8010N_EN: qcom,pm8008-chip-en { + regulator-name = "pm8010n-chip-en"; + }; + }; + + qcom,revid@100 { + reg = <0x100>; + }; + }; + + pm8010n@d { + compatible = "qcom,i2c-pmic"; + reg = <0xd>; + #address-cells = <1>; + #size-cells = <0>; + + qcom,pm8010n-regulator { + #address-cells = <1>; + #size-cells = <0>; + + pm8008_en-supply = <&PM8010N_EN>; + vdd_l1_l2-supply = <&S8B>; + vdd_l3_l4-supply = <&S9B>; + + L1N: pm8010n_l1: regulator@4000 { + reg = <0x4000>; + regulator-name = "pm8010n_l1"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; + qcom,min-dropout-voltage = <72000>; + qcom,hpm-min-load = <30000>; + }; + + L3N: pm8010n_l3: regulator@4200 { + reg = <0x4200>; + regulator-name = "pm8010n_l3"; + regulator-min-microvolt = <1736000>; + regulator-max-microvolt = <3312000>; + qcom,hpm-min-load = <0>; + qcom,min-dropout-voltage = <120000>; + }; + + L4N: pm8010n_l4: regulator@4300 { + reg = <0x4300>; + regulator-name = "pm8010N_l4"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1900000>; + qcom,hpm-min-load = <0>; + qcom,min-dropout-voltage = <152000>; + }; + + L6N: pm8010n_l6: regulator@4500 { + reg = <0x4500>; + regulator-name = "pm8010n_l6"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3000000>; + qcom,hpm-min-load = <0>; + }; + }; + }; +}; + +&pm6450_pwm_1 { + status = "ok"; +}; + +&pm6450_gpios { + lcd_backlight_ctrl { + lcd_backlight_pwm_default: lcd_backlight_pwm_default { + pins = "gpio7"; + function = "func1"; + input-disable; + output-enable; + bias-disable; + power-source = <1>; /* 1.8V */ + qcom,drive-strength = <2>; + }; + + lcd_backlight_en_default: lcd_backlight_en_default { + pins = "gpio6"; + function = "normal"; + input-disable; + output-enable; + bias-disable; + power-source = <0>; + qcom,drive-strength = <2>; + }; + }; +}; diff --git a/qcom/ravelin-qcx6438.dtsi b/qcom/ravelin-qcx6438.dtsi new file mode 100644 index 00000000..f51eb0ac --- /dev/null +++ b/qcom/ravelin-qcx6438.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + wil6210: qcom,wil6210 { + qcom,pcie-parent = <&pcie0>; + qcom,wigig-en = <&tlmm 91 0>; + pinctrl-names = "default"; + pinctrl-0 = <&wil6210_refclk_en_pin>; + qcom,11ad-bus-bw,name = "wil6210"; + qcom,11ad-bus-bw,num-cases = <3>; + qcom,11ad-bus-bw,num-paths = <1>; + qcom,11ad-bus-bw,vectors-KBps = <100 512 0 0>, + <100 512 600000 800000>, + <100 512 1300000 1300000>; + qcom,use-ext-supply; + vdd-s1c-supply = <&S9B>; + qcom,keep-radio-on-during-sleep; + qcom,use-ap-power-save; + status = "disabled"; + }; +}; + +&pcie0_rp { + #address-cells = <5>; + #size-cells = <0>; + + wil6210_pci: wil6210_pci { + reg = <0 0 0 0 0>; + qcom,iommu-group = <&wil6210_pci_iommu_group>; + + #address-cells = <1>; + #size-cells = <1>; + + wil6210_pci_iommu_group: wil6210_pci_iommu_group { + reg = <0 0>; + qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + qcom,iommu-pagetable = "coherent"; + }; + }; +}; + +&tlmm { + talyn_pins { + wil6210_refclk_en_pin: wil6210_refclk_en_pin { + mux { + pins = "gpio83"; + function = "gpio"; + }; + + config { + pins = "gpio83"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + }; +}; diff --git a/qcom/ravelin-qrd-4gb-overlay.dts b/qcom/ravelin-qrd-4gb-overlay.dts new file mode 100644 index 00000000..ea38d8c4 --- /dev/null +++ b/qcom/ravelin-qrd-4gb-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "ravelin-qrd-4gb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin QRD 4GB DDR"; + compatible = "qcom,ravelin-qrd", "qcom,ravelin", "qcom,qrd"; + qcom,msm-id = <568 0x10000>, <602 0x10000>; + qcom,board-id = <0x1000B 0x600>; +}; diff --git a/qcom/ravelin-qrd-4gb.dts b/qcom/ravelin-qrd-4gb.dts new file mode 100644 index 00000000..caadec8c --- /dev/null +++ b/qcom/ravelin-qrd-4gb.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin-4gb.dtsi" +#include "ravelin-qrd-4gb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin QRD 4GB DDR"; + compatible = "qcom,ravelin-qrd", "qcom,ravelin", "qcom,qrd"; + qcom,board-id = <0x1000B 0x600>; +}; diff --git a/qcom/ravelin-qrd-4gb.dtsi b/qcom/ravelin-qrd-4gb.dtsi new file mode 100644 index 00000000..c0e0c1bc --- /dev/null +++ b/qcom/ravelin-qrd-4gb.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-qrd.dtsi" diff --git a/qcom/ravelin-qrd-overlay.dts b/qcom/ravelin-qrd-overlay.dts new file mode 100644 index 00000000..5de8fb12 --- /dev/null +++ b/qcom/ravelin-qrd-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "ravelin-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin QRD"; + compatible = "qcom,ravelin-qrd", "qcom,ravelin", "qcom,qrd"; + qcom,msm-id = <568 0x10000>, <602 0x10000>, <581 0x10000>, <582 0x10000>; + qcom,board-id = <0x1000B 0>; +}; + diff --git a/qcom/ravelin-qrd.dts b/qcom/ravelin-qrd.dts new file mode 100644 index 00000000..111cf271 --- /dev/null +++ b/qcom/ravelin-qrd.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin.dtsi" +#include "ravelin-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin QRD"; + compatible = "qcom,ravelin-qrd", "qcom,ravelin", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; +}; + diff --git a/qcom/ravelin-qrd.dtsi b/qcom/ravelin-qrd.dtsi new file mode 100644 index 00000000..cf9f8ecd --- /dev/null +++ b/qcom/ravelin-qrd.dtsi @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-pmic-overlay.dtsi" +#include "ravelin-pmi632.dtsi" +#include "ravelin-thermal-overlay.dtsi" + +&soc { +}; + +&qupv3_se1_i2c { + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + qcom,i2c-touch-active = "focaltech,fts_ts"; + + focaltech@38 { + status = "ok"; + reg = <0x38>; + + interrupt-parent = <&tlmm>; + interrupts = <13 0x2008>; + focaltech,reset-gpio = <&tlmm 12 0x00>; + focaltech,irq-gpio = <&tlmm 13 0x2008>; + focaltech,display-coords = <0 0 1080 2408>; + focaltech,max-touch-number = <10>; + focaltech,ic-type = <0x8726081C>; + focaltech,touch-type = "primary"; + focaltech,touch-environment = "pvm"; + + pinctrl-names = "pmx_ts_active","pmx_ts_suspend","pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + }; +}; + +&sdhc_1 { + status = "ok"; + vdd-supply = <&L5E>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L19B>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-current-level = <0 325000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; +}; + +&sdhc_2 { + status = "ok"; + vdd-supply = <&L24B>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + /* + * min/max voltages are voted on L24B/L28B and L24B/L28B_PBS + * regulators will only be voted for enabling/disabling conditions + * to support FR84471 for chipsets where PMIC doesn't support + * PBS ram sequence to turn OFF regulators automatically on + * multicard tray removal and these new regulator resources are + * exposed by PMIC team as part of this FR. + */ + vdd-en-dis-supply = <&L24B_PBS>; + + vdd-io-supply = <&L28B>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + vdd-io-en-dis-supply = <&L28B_PBS>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>; +}; + +&ufsphy_mem { + /* + * Here parrot phy is used for ravelin as it + * do not have its own list for module load and + * hence compatible is using parrot. + * We have plan to improve this by making phy binary + * target independent. + */ + compatible = "qcom,ufs-phy-qmp-v4-waipio"; + + vdda-phy-supply = <&L5B>; + vdda-pll-supply = <&L16B>; + vdda-phy-max-microamp = <88530>; + vdda-pll-max-microamp = <18310>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + + vcc-supply = <&L5E>; + vcc-max-microamp = <1056000>; + + vccq-supply = <&L13B>; + vccq-max-microamp = <750000>; + + vccq2-supply = <&L19B>; + vccq2-max-microamp = <750000>; + + qcom,vddp-ref-clk-supply = <&L13B>; + qcom,vddp-ref-clk-max-microamp = <100>; + + /* + * ufs-dev-types and nvmem entries are for ufs device + * identification using nvmem interface. Use number of + * ufs devices supported for ufs-dev-types, and nvmem handle + * added by pmic for sdam register. + * + * Default value taken by driver is bit[0] = 0 for 3.x and + * bit[0] = 1 for 2.x driver code takes this as default case. + * + * But Bit value to identify ufs device is not consistent + * across the targets it could be bit[0] = 0/1 for UFS2.x/3x + * and vice versa. If the bit[0] value is not same as default + * value used in driver and if its reverted then use flag + * qcom,ufs-dev-revert to identify ufs device. + */ + ufs-dev-types = <2>; + qcom,ufs-dev-revert; + nvmem-cells = <&ufs_dev>, <&boot_config>; + nvmem-cell-names = "ufs_dev", "boot_conf"; + + status = "ok"; +}; + +&usb0 { + dwc3@a600000 { + usb-phy = <&usb2_phy0>, <&usb_nop_phy>; + maximum-speed = "high-speed"; + }; +}; + +&usb_qmp_dp_phy { + status = "disabled"; +}; + +&usb2_phy0 { + qcom,param-override-seq = + <0x86 0x6c>; +}; + +&battery_charger { + qcom,thermal-mitigation-step = <500000>; + qcom,wireless-charging-not-supported; + qcom,thermal-mitigation = <11500000 11000000 10500000 10000000 9500000 + 9000000 8500000 8000000 7500000 7000000 6500000 + 6000000 5500000 5000000 4500000 4000000 3500000 + 3000000 2500000 2000000 1500000 1000000 500000>; +}; diff --git a/qcom/ravelin-qupv3.dtsi b/qcom/ravelin-qupv3.dtsi new file mode 100644 index 00000000..aeceb616 --- /dev/null +++ b/qcom/ravelin-qupv3.dtsi @@ -0,0 +1,528 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + /* QUPv3 SE Instances + * Qup0 0: SE 0 + * Qup0 1: SE 1 + * Qup0 2: SE 2 + * Qup0 3: SE 3 + * Qup0 4: SE 4 + * Qup1 0: SE 5 + * Qup1 1: SE 6 + * Qup1 2: SE 7 + * Qup1 3: SE 8 + * Qup1 4: SE 9 + */ + + /* GPI Instance */ + gpi_dma0: qcom,gpi-dma@900000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0x900000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0x176 0x0>; + qcom,max-num-gpii = <12>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,static-gpii-mask = <0x1>; + qcom,gpii-mask = <0x3e>; + qcom,ev-factor = <2>; + qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + dma-coherent; + qcom,gpi-ee-offset = <0x10000>; + status = "ok"; + }; + + /* QUPv3_0 wrapper instance */ + qupv3_0: qcom,qupv3_0_geni_se@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x9c0000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + iommus = <&apps_smmu 0x163 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + dma-coherent; + status = "ok"; + + /* HS UART Instance */ + qupv3_se2_4uart: qcom,qup_uart@988000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x988000 0x4000>; + reg-names = "se_phys"; + interrupts-extended = <&intc GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 17 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "active", "sleep", "shutdown"; + pinctrl-0 = <&qupv3_se2_default_cts>, <&qupv3_se2_default_rts>, + <&qupv3_se2_default_tx>, <&qupv3_se2_default_rx>; + pinctrl-1 = <&qupv3_se2_cts>, <&qupv3_se2_rts>, + <&qupv3_se2_tx>, <&qupv3_se2_rx>; + pinctrl-2 = <&qupv3_se2_cts>, <&qupv3_se2_rts>, + <&qupv3_se2_tx>, <&qupv3_se2_default_rx>; + pinctrl-3 = <&qupv3_se2_default_cts>, <&qupv3_se2_default_rts>, + <&qupv3_se2_default_tx>, <&qupv3_se2_default_rx>; + qcom,wakeup-byte = <0xFD>; + status = "disabled"; + }; + + /* HST Debug UART Instance */ + qupv3_se0_2uart: qcom,qup_uart@980000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x980000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_2uart_tx_active>, <&qupv3_se0_2uart_rx_active>; + pinctrl-1 = <&qupv3_se0_2uart_sleep>; + status = "disabled"; + }; + + qupv3_se0_i2c: i2c@980000 { + compatible = "qcom,i2c-geni"; + reg = <0x980000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>; + pinctrl-1 = <&qupv3_se0_i2c_sleep>; + dmas = <&gpi_dma0 0 0 3 64 0>, + <&gpi_dma0 1 0 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se1_i2c: i2c@984000 { + compatible = "qcom,i2c-geni"; + reg = <0x984000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_i2c_sda_active>, <&qupv3_se1_i2c_scl_active>; + pinctrl-1 = <&qupv3_se1_i2c_sleep>; + dmas = <&gpi_dma0 0 1 3 64 2>, + <&gpi_dma0 1 1 3 64 2>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se1_spi: spi@984000 { + compatible = "qcom,spi-geni"; + reg = <0x984000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_spi_mosi_active>, <&qupv3_se1_spi_miso_active>, + <&qupv3_se1_spi_clk_active>, <&qupv3_se1_spi_cs_active>; + pinctrl-1 = <&qupv3_se1_spi_sleep>; + dmas = <&gpi_dma0 0 1 1 64 2>, + <&gpi_dma0 1 1 1 64 2>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se3_i2c: i2c@98c000 { + compatible = "qcom,i2c-geni"; + reg = <0x98c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_i2c_sda_active>, <&qupv3_se3_i2c_scl_active>; + pinctrl-1 = <&qupv3_se3_i2c_sleep>; + dmas = <&gpi_dma0 0 3 3 64 0>, + <&gpi_dma0 1 3 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se3_spi: spi@98c000 { + compatible = "qcom,spi-geni"; + reg = <0x98c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_spi_mosi_active>, <&qupv3_se3_spi_miso_active>, + <&qupv3_se3_spi_clk_active>, <&qupv3_se3_spi_cs_active>; + pinctrl-1 = <&qupv3_se3_spi_sleep>; + dmas = <&gpi_dma0 0 3 1 64 0>, + <&gpi_dma0 1 3 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se4_i2c: i2c@990000 { + compatible = "qcom,i2c-geni"; + reg = <0x990000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_i2c_sda_active>, <&qupv3_se4_i2c_scl_active>; + pinctrl-1 = <&qupv3_se4_i2c_sleep>; + dmas = <&gpi_dma0 0 4 3 64 0>, + <&gpi_dma0 1 4 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se4_spi: spi@990000 { + compatible = "qcom,spi-geni"; + reg = <0x990000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_spi_mosi_active>, <&qupv3_se4_spi_miso_active>, + <&qupv3_se4_spi_clk_active>, <&qupv3_se4_spi_cs_active>; + pinctrl-1 = <&qupv3_se4_spi_sleep>; + dmas = <&gpi_dma0 0 4 1 64 0>, + <&gpi_dma0 1 4 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + }; + + /* GPI Instance */ + gpi_dma1: qcom,gpi-dma@a00000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0xa00000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0x416 0x0>; + qcom,max-num-gpii = <12>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,gpii-mask = <0x3f>; + qcom,ev-factor = <2>; + qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + dma-coherent; + qcom,gpi-ee-offset = <0x10000>; + status = "ok"; + }; + + /* QUPv3_1 wrapper instance */ + qupv3_1: qcom,qupv3_1_geni_se@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0xac0000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0x403 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + dma-coherent; + ranges; + status = "ok"; + + /* PORed Debug UART Instance */ + qupv3_se7_2uart: qcom,qup_uart@a88000 { + compatible = "qcom,geni-debug-uart"; + reg = <0xa88000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_2uart_tx_active>, <&qupv3_se7_2uart_rx_active>; + pinctrl-1 = <&qupv3_se7_2uart_sleep>; + status = "disabled"; + }; + + qupv3_se5_i2c: i2c@a80000 { + compatible = "qcom,i2c-geni"; + reg = <0xa80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_i2c_sda_active>, <&qupv3_se5_i2c_scl_active>; + pinctrl-1 = <&qupv3_se5_i2c_sleep>; + dmas = <&gpi_dma1 0 0 3 64 0>, + <&gpi_dma1 1 0 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se5_spi: spi@a80000 { + compatible = "qcom,spi-geni"; + reg = <0xa80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_spi_mosi_active>, <&qupv3_se5_spi_miso_active>, + <&qupv3_se5_spi_clk_active>, <&qupv3_se5_spi_cs_active>; + pinctrl-1 = <&qupv3_se5_spi_sleep>; + dmas = <&gpi_dma1 0 0 1 64 0>, + <&gpi_dma1 1 0 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se6_i2c: i2c@a84000 { + compatible = "qcom,i2c-geni"; + reg = <0xa84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_i2c_sda_active>, <&qupv3_se6_i2c_scl_active>; + pinctrl-1 = <&qupv3_se6_i2c_sleep>; + dmas = <&gpi_dma1 0 1 3 64 0>, + <&gpi_dma1 1 1 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se6_spi: spi@a84000 { + compatible = "qcom,spi-geni"; + reg = <0xa84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_spi_mosi_active>, <&qupv3_se6_spi_miso_active>, + <&qupv3_se6_spi_clk_active>, <&qupv3_se6_spi_cs_active>; + pinctrl-1 = <&qupv3_se6_spi_sleep>; + dmas = <&gpi_dma1 0 1 1 64 0>, + <&gpi_dma1 1 1 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se8_i2c: i2c@a8c000 { + compatible = "qcom,i2c-geni"; + reg = <0xa8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_i2c_sda_active>, <&qupv3_se8_i2c_scl_active>; + pinctrl-1 = <&qupv3_se8_i2c_sleep>; + dmas = <&gpi_dma1 0 3 3 64 0>, + <&gpi_dma1 1 3 3 64 0>; + dma-names = "tx", "rx"; + qcom,shared; + status = "disabled"; + }; + + qupv3_se8_spi: spi@a8c000 { + compatible = "qcom,spi-geni"; + reg = <0xa8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_spi_mosi_active>, <&qupv3_se8_spi_miso_active>, + <&qupv3_se8_spi_clk_active>, <&qupv3_se8_spi_cs_active>; + pinctrl-1 = <&qupv3_se8_spi_sleep>; + dmas = <&gpi_dma1 0 3 1 64 0>, + <&gpi_dma1 1 3 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se9_i2c: i2c@a90000 { + compatible = "qcom,i2c-geni"; + reg = <0xa90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_i2c_sda_active>, <&qupv3_se9_i2c_scl_active>; + pinctrl-1 = <&qupv3_se9_i2c_sleep>; + dmas = <&gpi_dma1 0 4 3 64 0>, + <&gpi_dma1 1 4 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se9_spi: spi@a90000 { + compatible = "qcom,spi-geni"; + reg = <0xa90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_spi_mosi_active>, <&qupv3_se9_spi_miso_active>, + <&qupv3_se9_spi_clk_active>, <&qupv3_se9_spi_cs_active>; + pinctrl-1 = <&qupv3_se9_spi_sleep>; + dmas = <&gpi_dma1 0 4 1 64 0>, + <&gpi_dma1 1 4 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + }; +}; diff --git a/qcom/ravelin-regulators.dtsi b/qcom/ravelin-regulators.dtsi new file mode 100644 index 00000000..3f67cb6f --- /dev/null +++ b/qcom/ravelin-regulators.dtsi @@ -0,0 +1,814 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&apps_rsc_drv2 { + rpmh-regulator-msslvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mss.lvl"; + VDD_MODEM_LEVEL: + S1B_LEVEL: + pm6450_s1_level: regulator-pm6450-s1-level { + regulator-name = "pm6450_s1_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-cxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "cx.lvl"; + proxy-supply = <&VDD_CX_LEVEL>; + VDD_CX_LEVEL: + S5B_LEVEL: + pm6450_s5_level: regulator-pm6450-s5-level { + regulator-name = "pm6450_s5_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = + ; + }; + + VDD_CX_LEVEL_AO: + S5B_LEVEL_AO: + pm6450_s5_level_ao: regulator-pm6450-s5-level-ao { + regulator-name = "pm6450_s5_level_ao"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-ebilvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "ebi.lvl"; + VDD_EBI_LEVEL: + S6B_LEVEL: + pm6450_s6_level: regulator-pm6450-s6-level { + regulator-name = "pm6450_s6_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-smpb7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpb7"; + S7B: + pm6450_s7: regulator-pm6450-s7 { + regulator-name = "pm6450_s7"; + qcom,set = ; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + qcom,init-voltage = <1120000>; + }; + }; + + rpmh-regulator-smpb8 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpb8"; + S8B: + pm6450_s8: regulator-pm6450-s8 { + regulator-name = "pm6450_s8"; + qcom,set = ; + regulator-min-microvolt = <382000>; + regulator-max-microvolt = <1744000>; + qcom,init-voltage = <1352000>; + }; + }; + + rpmh-regulator-smpb9 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpb9"; + S9B: + pm6450_s9: regulator-pm6450-s9 { + regulator-name = "pm6450_s9"; + qcom,set = ; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2040000>; + qcom,init-voltage = <1872000>; + }; + }; + + rpmh-regulator-ldob1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = ; + L1B: + pm6450_l1: regulator-pm6450-l1 { + regulator-name = "pm6450_l1"; + qcom,set = ; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <650000>; + qcom,init-voltage = <504000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-lcxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "lcx.lvl"; + VDD_LPI_CX_LEVEL: + L2B_LEVEL: + pm6450_l2_level: regulator-pm6450-l2-level { + regulator-name = "pm6450_l2_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-ldob3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = ; + L3B: + pm6450_l3: regulator-pm6450-l3 { + regulator-name = "pm6450_l3"; + qcom,set = ; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + qcom,init-voltage = <904000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob4 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob4"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = ; + L4B: + pm6450_l4: regulator-pm6450-l4 { + regulator-name = "pm6450_l4"; + qcom,set = ; + regulator-min-microvolt = <530000>; + regulator-max-microvolt = <860000>; + qcom,init-voltage = <808000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = ; + L5B: + pm6450_l5: regulator-pm6450-l5 { + regulator-name = "pm6450_l4"; + qcom,set = ; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1052000>; + qcom,init-voltage = <880000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob6 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob6"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = ; + L6B: + pm6450_l6: regulator-pm6450-l6 { + regulator-name = "pm6450_l6"; + qcom,set = ; + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + qcom,init-voltage = <824000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = ; + L7B: + pm6450_l7: regulator-pm6450-l7 { + regulator-name = "pm6450_l7"; + qcom,set = ; + regulator-min-microvolt = <830000>; + regulator-max-microvolt = <920000>; + qcom,init-voltage = <912000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-lmxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "lmx.lvl"; + VDD_LPI_MX_LEVEL: + L8B_LEVEL: + pm6450_l8_level: regulator-pm6450-l8-level { + regulator-name = "pm6450_l8_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-ldob9 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob9"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = ; + L9B: + pm6450_l9: regulator-pm6450-l9 { + regulator-name = "pm6450_l9"; + qcom,set = ; + regulator-min-microvolt = <504000>; + regulator-max-microvolt = <824000>; + qcom,init-voltage = <752000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob10 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob10"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = ; + L10B: + pm6450_l10: regulator-pm6450-l10 { + regulator-name = "pm6450_l10"; + qcom,set = ; + regulator-min-microvolt = <824000>; + regulator-max-microvolt = <901000>; + qcom,init-voltage = <824000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob11 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob11"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = ; + L11B: + pm6450_l11: regulator-pm6450-l11 { + regulator-name = "pm6450_l11"; + qcom,set = ; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <752000>; + qcom,init-voltage = <348000>; + }; + }; + + rpmh-regulator-ldob12 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob12"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = ; + L12B: + pm6450_l12: regulator-pm6450-l12 { + regulator-name = "pm6450_l12"; + qcom,set = ; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1080000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob13 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob13"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = ; + L13B: + pm6450_l13: regulator-pm6450-l13 { + regulator-name = "pm6450_l13"; + qcom,set = ; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob14 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob14"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = ; + L14B: + pm6450_l14: regulator-pm6450-l14 { + regulator-name = "pm6450_l14"; + qcom,set = ; + regulator-min-microvolt = <1245000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1150000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob16 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob16"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = ; + L16B: + pm6450_l16: regulator-pm6450-l16 { + regulator-name = "pm6450_l16"; + qcom,set = ; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1260000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob17 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob17"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = ; + L17B: + pm6450_l17: regulator-pm6450-l17 { + regulator-name = "pm6450_l17"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob18 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob18"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = ; + L18B: + pm6450_l18: regulator-pm6450-l18 { + regulator-name = "pm6450_l18"; + qcom,set = ; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + qcom,init-voltage = <1504000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob19 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob19"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = ; + L19B: + pm6450_l19: regulator-pm6450-l19 { + regulator-name = "pm6450_l19"; + qcom,set = ; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1950000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob20 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob20"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = ; + L20B: + pm6450_l20: regulator-pm6450-l20 { + regulator-name = "pm6450_l20"; + qcom,set = ; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + qcom,init-voltage = <1700000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob21 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob21"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = ; + L21B: + pm6450_l21: regulator-pm6450-l21 { + regulator-name = "pm6450_l21"; + qcom,set = ; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob22 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob22"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = ; + L22B: + pm6450_l22: regulator-pm6450-l22 { + regulator-name = "pm6450_l22"; + qcom,set = ; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob23 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob23"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = ; + L23B: + pm6450_l23: regulator-pm6450-l23 { + regulator-name = "pm6450_l23"; + qcom,set = ; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob24 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob24"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = ; + L24B: + pm6450_l24: regulator-pm6450-l24 { + regulator-name = "pm6450_l24"; + qcom,set = ; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <2700000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob25 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob25"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = ; + L25B: + pm6450_l25: regulator-pm6450-l25 { + regulator-name = "pm6450_l25"; + qcom,set = ; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <3072000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob26 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob26"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = ; + L26B: + pm6450_l26: regulator-pm6450-l26 { + regulator-name = "pm6450_l26"; + qcom,set = ; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <1620000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob27 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob27"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = ; + L27B: + pm6450_l27: regulator-pm6450-l27 { + regulator-name = "pm6450_l27"; + qcom,set = ; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <1620000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob28 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob28"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = ; + L28B: + pm6450_l28: regulator-pm6450-l28 { + regulator-name = "pm6450_l28"; + qcom,set = ; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <2700000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = ; + L1E: + pm8010l_l1: regulator-pm8010-l1 { + regulator-name = "pm8010_l1"; + qcom,set = ; + regulator-min-microvolt = <530000>; + regulator-max-microvolt = <864000>; + qcom,init-voltage = <530000>; + }; + }; + + rpmh-regulator-ldoe3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe3"; + qcom,regulator-type = "pmic5-ldo"; + /* mode voting is not allowed */ + L3E: + pm8010l_l3: regulator-pm8010-l3 { + regulator-name = "pm8010_l3"; + qcom,set = ; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <2700000>; + }; + }; + + rpmh-regulator-ldoe4 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe4"; + qcom,regulator-type = "pmic5-ldo"; + /* mode voting is not allowed */ + L4E: + pm8010_l4: regulator-pm8010-l4 { + regulator-name = "pm8010_l4"; + qcom,set = ; + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <3312000>; + qcom,init-voltage = <2700000>; + }; + }; + + rpmh-regulator-ldoe5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe5"; + qcom,regulator-type = "pmic5-ldo"; + /* mode voting is not allowed */ + L5E: + pm8010_l5: regulator-pm8010-l5 { + regulator-name = "pm8010_l5"; + qcom,set = ; + /* + * Remove min/max voltages for this regulator as initial + * voltage of L5E is set to be 2.4v/2.96v during PON + * depending upon the UFS mode. UFS is the only client + * on this and this regulator will only be voted + * for enabling/disabling conditions. + */ + }; + }; + + rpmh-regulator-ldoe6 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe6"; + qcom,regulator-type = "pmic5-ldo"; + /* mode voting is not allowed */ + L6E: + pm8010_l6: regulator-pm8010-l6 { + regulator-name = "pm8010_l6"; + qcom,set = ; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + qcom,init-voltage = <3000000>; + }; + }; + + rpmh-regulator-ldoe7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe7"; + qcom,regulator-type = "pmic5-ldo"; + /* mode voting is not allowed */ + L7E: + pm8010_l7: regulator-pm8010-l7 { + regulator-name = "pm8010_l7"; + qcom,set = ; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <3000000>; + }; + }; + + rpmh-regulator-mxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mx.lvl"; + proxy-supply = <&VDD_MX_LEVEL>; + + VDD_MX_LEVEL: + S1G_LEVEL: + pmg1110_s1_level: regulator-pmg1110-s1-level { + regulator-name = "pmg1110_s1_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = + ; + + }; + }; + + rpmh-regulator-sf1-vreg-enable { + compatible = "qcom,rpmh-xob-regulator"; + qcom,resource-name = "gpioi7"; + status = "disabled"; + sf1_vreg_enable: regulator-sf1-vreg-enable { + regulator-name = "sf1_vreg_enable"; + qcom,set = ; + }; + }; + + rpmh-regulator-sf1-vreg-mode { + compatible = "qcom,rpmh-xob-regulator"; + qcom,resource-name = "gpioi10"; + status = "disabled"; + sf1_vreg_mode: regulator-sf1-vreg-mode { + regulator-name = "sf1_vreg_mode"; + qcom,set = ; + }; + }; + + rpmh-regulator-vrmsd { + compatible = "qcom,rpmh-pbs-regulator"; + qcom,resource-name = "vrm.sd"; + + L24B_PBS: + pm6450_l24_pbs: regulator-pm6450-l24-pbs { + regulator-name = "pm6450_l24_pbs"; + qcom,set = ; + /* + * min/max voltages are voted on L24B and this regulator will + * only be voted for enabling/disabling conditions. + */ + }; + }; + + rpmh-regulator-vrmpx2 { + compatible = "qcom,rpmh-pbs-regulator"; + qcom,resource-name = "vrm.px2"; + + L28B_PBS: + pm6450_l28_pbs: regulator-pm6450-l28-pbs { + regulator-name = "pm6450_l28_pbs"; + qcom,set = ; + /* + * min/max voltages are voted on L28B and this regulator will + * only be voted for enabling/disabling conditions. + */ + }; + }; +}; diff --git a/qcom/ravelin-reserved-memory.dtsi b/qcom/ravelin-reserved-memory.dtsi new file mode 100644 index 00000000..03120f6d --- /dev/null +++ b/qcom/ravelin-reserved-memory.dtsi @@ -0,0 +1,174 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp_region@80000000 { + no-map; + reg = <0x0 0x80000000 0x0 0x600000>; + }; + + xbl_dtlog_mem: xbl_dtlog_region@80600000 { + no-map; + reg = <0x0 0x80600000 0x0 0x40000>; + }; + + xbl_ramdump_mem: xbl_ramdump_region@80640000 { + no-map; + reg = <0x0 0x80640000 0x0 0x1c0000>; + }; + + aop_image_mem: aop_image_region@80800000 { + no-map; + reg = <0x0 0x80800000 0x0 0x60000>; + }; + + aop_cmd_db_mem: aop_cmd_db_region@80860000 { + compatible = "qcom,cmd-db"; + no-map; + reg = <0x0 0x80860000 0x0 0x20000>; + }; + + aop_config_mem: aop_config_region@80880000 { + no-map; + reg = <0x0 0x80880000 0x0 0x20000>; + }; + + tme_crash_dump_mem: tme_crash_dump_region@808a0000 { + no-map; + reg = <0x0 0x808a0000 0x0 0x40000>; + }; + + tme_log_mem: tme_log_region@808e0000 { + no-map; + reg = <0x0 0x808e0000 0x0 0x4000>; + }; + + uefi_log_mem: uefi_log_region@808e4000 { + no-map; + reg = <0x0 0x808e4000 0x0 0x10000>; + }; + + chipinfo_mem: chipinfo_region@808f4000 { + no-map; + reg = <0x0 0x808f4000 0x0 0x1000>; + }; + + smem_mem: smem_region@80900000 { + no-map; + reg = <0x0 0x80900000 0x0 0x200000>; + }; + + cpucp_fw_mem: cpucp_fw_region@80b00000 { + no-map; + reg = <0x0 0x80b00000 0x0 0x100000>; + }; + + wlan_msa_mem: wlan_msa_mem_region@82a00000 { + no-map; + reg = <0x0 0x82a00000 0x0 0xc00000>; + }; + + camera_mem: camera_region@84b00000 { + no-map; + reg = <0x0 0x84b00000 0x0 0x800000>; + }; + + wpss_moselle_mem: wpss_moselle_region@85300000 { + no-map; + reg = <0x0 0x85300000 0x0 0x1900000>; + }; + + video_mem: video_region@86c00000 { + no-map; + reg = <0x0 0x86c00000 0x0 0x700000>; + }; + + adsp_mem: adsp_region@87300000 { + no-map; + reg = <0x0 0x87300000 0x0 0x2100000>; + }; + + ipa_fw_mem: ipa_fw_region@89400000 { + no-map; + reg = <0x0 0x89400000 0x0 0x10000>; + }; + + ipa_gsi_mem: ipa_gsi_region@89410000 { + no-map; + reg = <0x0 0x89410000 0x0 0xa000>; + }; + + gpu_microcode_mem: gpu_microcode_region@8941a000 { + no-map; + reg = <0x0 0x8941a000 0x0 0x2000>; + }; + + mpss_mem: mpss_region@8a000000 { + no-map; + reg = <0x0 0x8a000000 0x0 0xda00000>; + }; + + xbl_sc_mem: xbl_sc_region@a6e00000 { + no-map; + reg = <0x0 0xa6e00000 0x0 0x40000>; + }; + + global_sync_mem: global_sync_region@a6f00000 { + no-map; + reg = <0x0 0xa6f00000 0x0 0x100000>; + }; + + cpusys_vm_mem: cpusys_vm_region@e0600000 { + no-map; + reg = <0x0 0xe0600000 0x0 0x400000>; + }; + + trust_ui_vm_mem: trust_ui_vm_region@e0b00000 { + no-map; + reg = <0x0 0xe0b00000 0x0 0x4af3000>; + }; + + trust_ui_vm_qrtr: trust_ui_vm_qrtr@e55f3000 { + no-map; + reg = <0x0 0xe55f3000 0x0 0x9000>; + }; + + trust_ui_vm_vblk0_ring: trust_ui_vm_vblk0_ring@e55fc000 { + no-map; + reg = <0x0 0xe55fc000 0x0 0x4000>; + gunyah-label = <0x11>; + }; + + trust_ui_vm_swiotlb: trust_ui_vm_swiotlb@e5600000 { + no-map; + reg = <0x0 0xe5600000 0x0 0x100000>; + gunyah-label = <0x12>; + }; + + tz_stat_mem: tz_stat_region@e8800000 { + no-map; + reg = <0x0 0xe8800000 0x0 0x100000>; + }; + + tags_mem: tags_region@e8900000 { + no-map; + reg = <0x0 0xe8900000 0x0 0x680000>; + }; + + qtee_mem: qtee_region@e8f80000 { + no-map; + reg = <0x0 0xe8f80000 0x0 0x500000>; + }; + + trusted_apps_mem: trusted_apps_region@e9480000 { + no-map; + reg = <0x0 0xe9480000 0x0 0x1200000>; + }; + +}; diff --git a/qcom/ravelin-rumi-overlay.dts b/qcom/ravelin-rumi-overlay.dts new file mode 100644 index 00000000..50703f01 --- /dev/null +++ b/qcom/ravelin-rumi-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "ravelin-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin RUMI"; + compatible = "qcom,ravelin-rumi", "qcom,ravelin", "qcom,rumi"; + qcom,msm-id = <568 0x10000>; + qcom,board-id = <0x1000F 0>; +}; + diff --git a/qcom/ravelin-rumi.dts b/qcom/ravelin-rumi.dts new file mode 100644 index 00000000..1c1ac6d6 --- /dev/null +++ b/qcom/ravelin-rumi.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/memreserve/ 0x90000000 0x00010000; + +#include "ravelin.dtsi" +#include "ravelin-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin RUMI"; + compatible = "qcom,ravelin-rumi", "qcom,ravelin", "qcom,rumi"; + qcom,board-id = <0x1000F 0>; +}; + diff --git a/qcom/ravelin-rumi.dtsi b/qcom/ravelin-rumi.dtsi new file mode 100644 index 00000000..8b32a2fc --- /dev/null +++ b/qcom/ravelin-rumi.dtsi @@ -0,0 +1,243 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&soc { + timer { + clock-frequency = <500000>; + }; + + timer@17420000 { + clock-frequency = <500000>; + }; + + qcom,wdt@17410000 { + status = "disabled"; + }; + + usb_emuphy: phy@a784000 { + compatible = "qcom,usb-emu-phy"; + reg = <0x0a784000 0x9500>; + + qcom,emu-init-seq = <0xfffff 0x4 + 0xffff0 0x4 + 0x100000 0x20 + 0x0 0x20 + 0x000001A0 0x20 + 0x00100000 0x3c + 0x0 0x3c + 0x0 0x4>; + }; + + bi_tcxo: bi_tcxo { + compatible = "fixed-factor-clock"; + clock-mult = <1>; + clock-div = <4>; + clocks = <&xo_board>; + #clock-cells = <0>; + }; + + bi_tcxo_ao: bi_tcxo_ao { + compatible = "fixed-factor-clock"; + clock-mult = <1>; + clock-div = <4>; + clocks = <&xo_board>; + #clock-cells = <0>; + }; +}; + +&SILVER_CPU_OFF { + status = "nok"; +}; + +&SILVER_CPU_RAIL_OFF { + status = "nok"; +}; + +&GOLD_CPU_OFF { + status = "nok"; +}; + +&GOLD_CPU_RAIL_OFF { + status = "nok"; +}; + +&CLUSTER_OFF { + status = "nok"; +}; + +&CX_RET { + status = "nok"; +}; + +&disp_rsc { + status = "nok"; +}; + +&usb0 { + dwc3@a600000 { + usb-phy = <&usb_emuphy>, <&usb_nop_phy>; + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + }; + + +}; + +&qupv3_se7_2uart { + qcom,rumi_platform; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qrbtc-sdm845"; + + vdda-phy-supply = <&L5B>; + vdda-pll-supply = <&L16B>; + vdda-phy-max-microamp = <85710>; + vdda-pll-max-microamp = <18330>; + + status = "ok"; +}; + +&ufshc_mem { + limit-tx-hs-gear = <1>; + limit-rx-hs-gear = <1>; + limit-rate = <2>; /* HS Rate-B */ + + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + + vcc-supply = <&L24B>; + vcc-max-microamp = <1056000>; + + vccq-supply = <&L13B>; + vccq-max-microamp = <750000>; + + vccq2-supply = <&L19B>; + vccq2-max-microamp = <750000>; + + qcom,vddp-ref-clk-supply = <&L13B>; + qcom,vddp-ref-clk-max-microamp = <70>; + + qcom,disable-lpm; + rpm-level = <0>; + spm-level = <0>; + + status = "ok"; +}; + +&sdhc_1 { + status = "ok"; + vdd-supply = <&L5E>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L19B>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + + /delete-property/ mmc-ddr-1_8v; + /delete-property/ mmc-hs200-1_8v; + /delete-property/ mmc-hs400-1_8v; + /delete-property/ mmc-hs400-enhanced-strobe; + max-frequency = <100000000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; +}; + +&sdhc_2 { + status = "ok"; + vdd-supply = <&L24B>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L28B>; + qcom,vdd-io-voltage-level = <2960000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + is_rumi; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>; +}; + +&gcc { + clocks = <&bi_tcxo>, <&sleep_clk>, + <&pcie_0_pipe_clk>, <&ufs_phy_rx_symbol_0_clk>, + <&ufs_phy_rx_symbol_1_clk>, <&ufs_phy_tx_symbol_0_clk>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; +}; + +&camcc { + clocks = <&bi_tcxo>, + <&gcc GCC_CAMERA_AHB_CLK>; +}; + +&dispcc { + clocks = <&bi_tcxo>, <&bi_tcxo_ao>, + <&sleep_clk>, <&gcc GCC_DISP_AHB_CLK>; +}; + +&gpucc { + clocks = <&bi_tcxo>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; +}; + +&debugcc { + clocks = <&bi_tcxo>, + <&gcc 0>, <&camcc 0>, + <&dispcc 0>, <&gpucc 0>; +}; + +&rpmhcc { + compatible = "qcom,dummycc"; + clock-output-names = "rpmhcc_clocks"; +}; + +&cpufreq_hw { + clocks = <&bi_tcxo>, <&gcc GCC_GPLL0>; +}; + +&tsens0 { + status = "disabled"; +}; + +&tsens1 { + status = "disabled"; +}; + +&pcie0 { + reg = <0x01c00000 0x3000>, + <0x01c06000 0x2000>, + <0x60000000 0xf1d>, + <0x60000f20 0xa8>, + <0x60001000 0x1000>, + <0x60100000 0x100000>, + <0x01c05000 0x1000>; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf", + "rumi"; + qcom,target-link-speed = <0x1>; + qcom,link-check-max-count = <200>; /* 1 sec */ + qcom,no-l1-supported; + qcom,no-l1ss-supported; + qcom,no-aux-clk-sync; + + status = "ok"; +}; + +&pcie0_msi { + status = "ok"; +}; diff --git a/qcom/ravelin-stub-regulator.dtsi b/qcom/ravelin-stub-regulator.dtsi new file mode 100644 index 00000000..34b19d5b --- /dev/null +++ b/qcom/ravelin-stub-regulator.dtsi @@ -0,0 +1,429 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +/ { + VDD_MODEM_LEVEL: + S1B_LEVEL: + pm6450_s1_level: regulator-pm6450-s1-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_s1_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + VDD_MX_LEVEL: + S2B_LEVEL: + pm6450_s2_level: regulator-pm6450_s2_level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_s2_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + VDD_CX_LEVEL: + S5B_LEVEL: + pm6450_s5_level: regulator-pm6450-s5-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_s5_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + VDD_EBI_LEVEL: + S6B_LEVEL: + pm6450_s6: regulator-pm6450-s6-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_s6_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + S7B: + pm6450_s7: regulator-pm6450-s7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_s7"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + }; + + S8B: + pm6450_s8: regulator-pm6450-s8 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_s8"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <598000>; + regulator-max-microvolt = <1654000>; + }; + + S9B: + pm6450_s9: regulator-pm6450-s9 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_s9"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + }; + + L1B: + pm6450_l1: regulator-pm6450-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l1"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <650000>; + }; + + VDD_LPI_CX_LEVEL: + L2B_LEVEL: + pm6450_l2_level: regulator-pm6450-l2-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l2_level"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + L3B: + pm6450_l3: regulator-pm6450-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l3"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + }; + + L5B: + pm6450_l5: regulator-pm6450-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l5"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <830000>; + regulator-max-microvolt = <920000>; + }; + + L6B: + pm6450_l6: regulator-pm6450-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l6"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + }; + + L7B: + pm6450_l7: regulator-pm6450-l7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l7"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <830000>; + regulator-max-microvolt = <920000>; + }; + + VDD_LPI_MX_LEVEL: + L8B_LEVEL: + pm6450_l8_level: regulator-pm6450-l8-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l8_level"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + L9B: + pm6450_l9: regulator-pm6450-l9 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l9"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + }; + + L10B: + pm6450_l10: regulator-pm6450-l10 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l10"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <824000>; + regulator-max-microvolt = <901000>; + }; + + L11B: + pm6450_l11: regulator-pm6450-l11 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l11"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <348000>; + regulator-max-microvolt = <888000>; + }; + + L12B: + pm6450_l12: regulator-pm6450-l12 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l12"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <1139000>; + regulator-max-microvolt = <1236000>; + }; + + L13B: + pm6450_l13: regulator-pm6450-l13 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l13"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + }; + + L14B: + pm6450_l14: regulator-pm6450-l14 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l14"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <1170000>; + regulator-max-microvolt = <1304000>; + }; + + L15B: + pm6450_l15: regulator-pm6450-l15 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l15"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + }; + + L16B: + pm6450_l16: regulator-pm6450-l16 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l16"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + }; + + L17B: + pm6450_l17: regulator-pm6450-l17 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l17"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + L18B: + pm6450_l18: regulator-pm6450-l18 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l18"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + }; + + L19B: + pm6450_l19: regulator-pm6450-l19 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l19"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + L20B: + pm6450_l20: regulator-pm6450-l20 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l20"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + }; + + L21B: + pm6450_l21: regulator-pm6450-l21 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l21"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + }; + + L22B: + pm6450_l22: regulator-pm6450-l22 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l22"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1550000>; + regulator-max-microvolt = <2000000>; + }; + + L23B: + pm6450_l23: regulator-pm6450-l23 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l23"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + }; + + L24B: + pm6450_l24: regulator-pm6450-l24 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l24"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + + L25B: + pm6450_l25: regulator-pm6450-l25 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l25"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + + L26B: + pm6450_l26: regulator-pm6450-l26 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l26"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + }; + + L27B: + pm6450_l27: regulator-pm6450-l27 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l27"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + }; + + L28B: + pm6450_l28: regulator-pm6450-l28 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l28"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3300000>; + }; + + L1M: pm8010m_l1: regulator-pm8010m-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010m_l1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + qcom,hpm-min-load = <30000>; + }; + + L2M: pm8010m_l2: regulator-pm8010m-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010m_l2"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; + qcom,hpm-min-load = <30000>; + }; + + L3M: pm8010m_l3: regulator-pm8010m-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010m_l3"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3000000>; + qcom,hpm-min-load = <30000>; + }; + + L4M: pm8010m_l4: regulator-pm8010m-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010m_l4"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + qcom,hpm-min-load = <30000>; + }; + + L6M: pm8010m_l6: regulator-pm8010m-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010m_l6"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + qcom,hpm-min-load = <30000>; + }; + + L7M: pm8010m_l7: regulator-pm8010m-l7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010m_l7"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3000000>; + qcom,hpm-min-load = <30000>; + }; + + L1N: pm8010n_l1: regulator-pm8010n-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010n_l1"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; + qcom,hpm-min-load = <30000>; + }; + + L3N: pm8010n_l3: regulator-pm8010n-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010n_l3"; + regulator-min-microvolt = <1792000>; + regulator-max-microvolt = <1900000>; + qcom,hpm-min-load = <30000>; + }; + + L4N: pm8010n_l4: regulator-pm8010n-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010n_l4"; + regulator-min-microvolt = <1792000>; + regulator-max-microvolt = <1900000>; + qcom,hpm-min-load = <30000>; + }; + + L6N: pm8010n_l6: regulator-pm8010n-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010n_l6"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + qcom,hpm-min-load = <30000>; + }; + + L1E: pm8010e_l1: regulator-pm8010e-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010e_l1"; + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + qcom,hpm-min-load = <30000>; + }; + + L4E: pm8010e_l4: regulator-pm8010e-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010e_l4"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3312000>; + qcom,hpm-min-load = <30000>; + }; + + L5E: pm8010e_l5: regulator-pm8010e-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010e_l5"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3544000>; + qcom,hpm-min-load = <30000>; + }; +}; diff --git a/qcom/ravelin-thermal-modem.dtsi b/qcom/ravelin-thermal-modem.dtsi new file mode 100644 index 00000000..f0827432 --- /dev/null +++ b/qcom/ravelin-thermal-modem.dtsi @@ -0,0 +1,404 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + qmi-tmd-devices { + compatible = "qcom,qmi-cooling-devices"; + + modem { + qcom,instance-id = ; + + modem_lte_dsc: modem_lte_dsc { + qcom,qmi-dev-name = "modem_lte_dsc"; + #cooling-cells = <2>; + }; + + modem_lte_sub1_dsc: modem_lte_sub1_dsc { + qcom,qmi-dev-name = "modem_lte_sub1_dsc"; + #cooling-cells = <2>; + }; + + modem_nr_dsc: modem_nr_dsc { + qcom,qmi-dev-name = "modem_nr_dsc"; + #cooling-cells = <2>; + }; + + modem_nr_sub1_dsc: modem_nr_sub1_dsc { + qcom,qmi-dev-name = "modem_nr_sub1_dsc"; + #cooling-cells = <2>; + }; + + modem_nr_scg_dsc: modem_nr_scg_dsc { + qcom,qmi-dev-name = "modem_nr_scg_dsc"; + #cooling-cells = <2>; + }; + + modem_nr_scg_sub1_dsc: modem_nr_scg_sub1_dsc { + qcom,qmi-dev-name = "modem_nr_scg_sub1_dsc"; + #cooling-cells = <2>; + }; + + sdr0_lte_dsc: sdr0_lte_dsc { + qcom,qmi-dev-name = "sdr0_lte_dsc"; + #cooling-cells = <2>; + }; + + sdr1_lte_dsc: sdr1_lte_dsc { + qcom,qmi-dev-name = "sdr1_lte_dsc"; + #cooling-cells = <2>; + }; + + sdr0_nr_dsc: sdr0_nr_dsc { + qcom,qmi-dev-name = "sdr0_nr_dsc"; + #cooling-cells = <2>; + }; + + sdr1_nr_dsc: sdr1_nr_dsc { + qcom,qmi-dev-name = "sdr1_nr_dsc"; + #cooling-cells = <2>; + }; + + pa_lte_sdr0_dsc: pa_lte_sdr0_dsc { + qcom,qmi-dev-name = "pa_lte_sdr0_dsc"; + #cooling-cells = <2>; + }; + + pa_lte_sdr1_dsc: pa_lte_sdr1_dsc { + qcom,qmi-dev-name = "pa_lte_sdr1_dsc"; + #cooling-cells = <2>; + }; + + pa_lte_sdr0_sub1_dsc: pa_lte_sdr0_sub1_dsc { + qcom,qmi-dev-name = "pa_lte_sdr0_sub1_dsc"; + #cooling-cells = <2>; + }; + + pa_lte_sdr1_sub1_dsc: pa_lte_sdr1_sub1_dsc { + qcom,qmi-dev-name = "pa_lte_sdr1_sub1_dsc"; + #cooling-cells = <2>; + }; + + pa_nr_sdr0_dsc: pa_nr_sdr0_dsc { + qcom,qmi-dev-name = "pa_nr_sdr0_dsc"; + #cooling-cells = <2>; + }; + + pa_nr_sdr1_dsc: pa_nr_sdr1_dsc { + qcom,qmi-dev-name = "pa_nr_sdr1_dsc"; + #cooling-cells = <2>; + }; + + pa_nr_sdr0_sub1_dsc: pa_nr_sdr0_sub1_dsc { + qcom,qmi-dev-name = "pa_nr_sdr0_sub1_dsc"; + #cooling-cells = <2>; + }; + + pa_nr_sdr1_sub1_dsc: pa_nr_sdr1_sub1_dsc { + qcom,qmi-dev-name = "pa_nr_sdr1_sub1_dsc"; + #cooling-cells = <2>; + }; + + pa_nr_sdr0_scg_dsc: pa_nr_sdr0_scg { + qcom,qmi-dev-name = "pa_nr_sdr0_scg_dsc"; + #cooling-cells = <2>; + }; + + pa_nr_sdr1_scg_dsc: pa_nr_sdr1_scg { + qcom,qmi-dev-name = "pa_nr_sdr1_scg_dsc"; + #cooling-cells = <2>; + }; + + qmi_wlan: wlan { + qcom,qmi-dev-name = "wlan"; + #cooling-cells = <2>; + }; + + modem_vdd: modem_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + }; + + qmi_sensor: qmi-ts-sensors { + compatible = "qcom,qmi-sensors"; + #thermal-sensor-cells = <1>; + + modem { + qcom,instance-id = ; + qcom,qmi-sensor-names = "pa", + "pa_1", + "modem_bcl_warn", + "modem_cfg", + "lte_cc", + "mcg_fr1_cc", + "scg_fr1_cc", + "sub1_modem_cfg", + "sub1_lte_cc", + "sub1_mcg_fr1_cc", + "sub1_scg_fr1_cc", + "sdr0_pa0", + "sdr1_pa0", + "sdr0", + "sdr1"; + }; + }; +}; + +&thermal_zones { + pa { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_PA)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_PA_1)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + bcl-warn { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_BCL_WARN)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-cfg { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_EPM2)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + lte-cc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_EPM3)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mcg-fr1-cc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_EPM4)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + scg-fr1-cc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_EPM6)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sub1-modem-cfg { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SUB1_MODEM_CFG)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sub1-lte-cc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SUB1_LTE_CC)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sub1_mcg_fr1_cc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SUB1_MCG_FR1_CC)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sub1_scg_fr1_cc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SUB1_SCG_FR1_CC)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sdr0-pa { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SDR0_PA)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sdr1-pa { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SDR1_PA)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sdr0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SDR0)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sdr1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SDR1)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; diff --git a/qcom/ravelin-thermal-overlay.dtsi b/qcom/ravelin-thermal-overlay.dtsi new file mode 100644 index 00000000..2f260292 --- /dev/null +++ b/qcom/ravelin-thermal-overlay.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&thermal_zones { + pm6450_tz { + cooling-maps { + pm6450_lte { + trip = <&pm6450_trip0>; + cooling-device = <&modem_lte_dsc 255 255>; + }; + + pm6450_nr { + trip = <&pm6450_trip0>; + cooling-device = <&modem_nr_scg_dsc 255 255>; + }; + + pm6450_cpu0 { + trip = <&pm6450_trip0>; + cooling-device = <&cpu0_pause 1 1>; + }; + + pm6450_cpu1 { + trip = <&pm6450_trip0>; + cooling-device = <&cpu1_pause 1 1>; + }; + + pm6450_cpu2 { + trip = <&pm6450_trip0>; + cooling-device = <&cpu2_pause 1 1>; + }; + + pm6450_cpu3 { + trip = <&pm6450_trip0>; + cooling-device = <&cpu3_pause 1 1>; + }; + + pm6450_cpu4 { + trip = <&pm6450_trip0>; + cooling-device = <&cpu4_pause 1 1>; + }; + + pm6450_cpu5 { + trip = <&pm6450_trip0>; + cooling-device = <&cpu5_pause 1 1>; + }; + + pm6450_cpu6_7 { + trip = <&pm6450_trip0>; + cooling-device = <&cpu_6_7_pause 1 1>; + }; + + pm6450_gpu { + trip = <&pm6450_trip0>; + cooling-device = <&msm_gpu 3 THERMAL_NO_LIMIT>; + }; + }; + }; +}; diff --git a/qcom/ravelin-thermal.dtsi b/qcom/ravelin-thermal.dtsi new file mode 100644 index 00000000..e0f26fff --- /dev/null +++ b/qcom/ravelin-thermal.dtsi @@ -0,0 +1,951 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&msm_gpu { + #cooling-cells = <2>; +}; + +&soc { + tsens0: thermal-sensor@c263000 { + compatible = "qcom,tsens-v2"; + reg = <0x0c263000 0x1ff>, /* TM */ + <0x0c222000 0x1ff>; /* SROT */ + #qcom,sensors = <16>; + interrupts = , + , + ; + interrupt-names = "uplow","critical", "cold"; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c265000 { + compatible = "qcom,tsens-v2"; + reg = <0x0c265000 0x1ff>, /* TM */ + <0x0c223000 0x1ff>; /* SROT */ + #qcom,sensors = <16>; + interrupts = , + , + ; + interrupt-names = "uplow","critical", "cold"; + #thermal-sensor-cells = <1>; + }; + + qcom,cpu-pause { + compatible = "qcom,thermal-pause"; + + cpu0_pause: cpu0-pause { + qcom,cpus = <&CPU0>; + qcom,cdev-alias = "thermal-pause-1"; + #cooling-cells = <2>; + }; + + cpu1_pause: cpu1-pause { + qcom,cpus = <&CPU1>; + qcom,cdev-alias = "thermal-pause-2"; + #cooling-cells = <2>; + }; + + cpu2_pause: cpu2-pause { + qcom,cpus = <&CPU2>; + qcom,cdev-alias = "thermal-pause-4"; + #cooling-cells = <2>; + }; + + cpu3_pause: cpu3-pause { + qcom,cpus = <&CPU3>; + qcom,cdev-alias = "thermal-pause-8"; + #cooling-cells = <2>; + }; + + cpu4_pause: cpu4-pause { + qcom,cpus = <&CPU4>; + qcom,cdev-alias = "thermal-pause-10"; + #cooling-cells = <2>; + }; + + cpu5_pause: cpu5-pause { + qcom,cpus = <&CPU5>; + qcom,cdev-alias = "thermal-pause-20"; + #cooling-cells = <2>; + }; + + cpu6_pause: cpu6-pause { + qcom,cpus = <&CPU6>; + qcom,cdev-alias = "thermal-pause-40"; + #cooling-cells = <2>; + }; + + cpu7_pause: cpu7-pause { + qcom,cpus = <&CPU7>; + qcom,cdev-alias = "thermal-pause-80"; + #cooling-cells = <2>; + }; + + cpu_6_7_pause: cpu-6-7-pause { + qcom,cpus = <&CPU6 &CPU7>; + qcom,cdev-alias = "thermal-pause-C0"; + #cooling-cells = <2>; + }; + + /* Thermal-engine cooling devices */ + pause-cpu0 { + qcom,cpus = <&CPU0>; + qcom,cdev-alias = "pause-cpu0"; + }; + + pause-cpu1 { + qcom,cpus = <&CPU1>; + qcom,cdev-alias = "pause-cpu1"; + }; + + pause-cpu2 { + qcom,cpus = <&CPU2>; + qcom,cdev-alias = "pause-cpu2"; + }; + + pause-cpu3 { + qcom,cpus = <&CPU3>; + qcom,cdev-alias = "pause-cpu3"; + }; + + pause-cpu4 { + qcom,cpus = <&CPU4>; + qcom,cdev-alias = "pause-cpu4"; + }; + + pause-cpu5 { + qcom,cpus = <&CPU5>; + qcom,cdev-alias = "pause-cpu5"; + }; + + pause-cpu6 { + qcom,cpus = <&CPU6>; + qcom,cdev-alias = "pause-cpu6"; + }; + + pause-cpu7 { + qcom,cpus = <&CPU7>; + qcom,cdev-alias = "pause-cpu7"; + }; + }; + + qcom,cpu-hotplug { + compatible = "qcom,cpu-hotplug"; + + cpu0_hotplug: cpu0-hotplug { + qcom,cpu = <&CPU0>; + qcom,cdev-alias = "cpu-hotplug0"; + #cooling-cells = <2>; + }; + + cpu1_hotplug: cpu1-hotplug { + qcom,cpu = <&CPU1>; + qcom,cdev-alias = "cpu-hotplug1"; + #cooling-cells = <2>; + }; + + cpu2_hotplug: cpu2-hotplug { + qcom,cpu = <&CPU2>; + qcom,cdev-alias = "cpu-hotplug2"; + #cooling-cells = <2>; + }; + + cpu3_hotplug: cpu3-hotplug { + qcom,cpu = <&CPU3>; + qcom,cdev-alias = "cpu-hotplug3"; + #cooling-cells = <2>; + }; + + cpu4_hotplug: cpu4-hotplug { + qcom,cpu = <&CPU4>; + qcom,cdev-alias = "cpu-hotplug4"; + #cooling-cells = <2>; + }; + + cpu5_hotplug: cpu5-hotplug { + qcom,cpu = <&CPU5>; + qcom,cdev-alias = "cpu-hotplug5"; + #cooling-cells = <2>; + }; + + cpu6_hotplug: cpu6-hotplug { + qcom,cpu = <&CPU6>; + qcom,cdev-alias = "cpu-hotplug6"; + #cooling-cells = <2>; + }; + + cpu7_hotplug: cpu7-hotplug { + qcom,cpu = <&CPU7>; + qcom,cdev-alias = "cpu-hotplug7"; + #cooling-cells = <2>; + }; + }; + + thermal_ddr_freq_table: thermal-ddr-freq-table { + qcom,freq-tbl = < 2092800 >; + }; + + ddr_cdev: qcom,ddr-cdev { + compatible = "qcom,ddr-cooling-device"; + #cooling-cells = <2>; + qcom,freq-table = <&thermal_ddr_freq_table>; + qcom,bus-width = <4>; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + }; + + qcom,cpufreq-cdev { + compatible = "qcom,cpufreq-cdev"; + cpu-cluster0 { + qcom,cpus = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + }; + + cpu-cluster1 { + qcom,cpus = <&CPU6 &CPU7>; + }; + }; + + qcom,devfreq-cdev { + compatible = "qcom,devfreq-cdev"; + qcom,devfreq = <&msm_gpu>; + }; + + qcom,userspace-cdev { + compatible = "qcom,userspace-cooling-devices"; + + display_fps: display-fps { + qcom,max-level = <3>; + #cooling-cells = <2>; + }; + }; + + cx_sdpm@634000 { + compatible = "qcom,sdpm"; + reg = <0x00634000 0x1000>; + clock-names = "gpu_cc_gx_gfx3d", + "cam_cc_camnoc_axi", + "cam_cc_bps", + "gcc_video_venus", + "disp_cc_mdss_mdp"; + clocks = <&gpucc GPU_CC_GX_GFX3D_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, + <&camcc CAM_CC_BPS_CLK_SRC>, + <&gcc GCC_VIDEO_VENUS_CLK_SRC>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; + csr-id = <0 1 2 6 7>; + }; + + cx_pe: cx_rdpm_pe@635000 { + compatible = "qcom,policy-engine"; + #thermal-sensor-cells = <0>; + reg = <0x635000 0x1000>; + interrupts = ; + }; +}; + +#include "ravelin-thermal-modem.dtsi" + +&thermal_zones { + aoss-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 0>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 1>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu0_emerg: cpu0-emerg-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu00_cdev { + trip = <&cpu0_emerg>; + cooling-device = <&cpu0_pause 1 1>; + }; + }; + }; + + cpu-0-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 2>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu1_emerg: cpu1-emerg-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu01_cdev { + trip = <&cpu1_emerg>; + cooling-device = <&cpu1_pause 1 1>; + }; + }; + }; + + cpu-0-2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 3>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu2_emerg: cpu2-emerg-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu02_cdev { + trip = <&cpu2_emerg>; + cooling-device = <&cpu2_pause 1 1>; + }; + }; + }; + + cpu-0-3 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu3_emerg: cpu3-emerg-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu03_cdev { + trip = <&cpu3_emerg>; + cooling-device = <&cpu3_pause 1 1>; + }; + }; + }; + + cpu-0-4 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu4_emerg: cpu4-emerg-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu04_cdev { + trip = <&cpu4_emerg>; + cooling-device = <&cpu4_pause 1 1>; + }; + }; + }; + + cpu-0-5 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu5_emerg: cpu5-emerg-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu05_cdev { + trip = <&cpu5_emerg>; + cooling-device = <&cpu5_pause 1 1>; + }; + }; + }; + + cpuss-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu6_emerg0: cpu6-emerg0-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu10_cdev { + trip = <&cpu6_emerg0>; + cooling-device = <&cpu6_pause 1 1>; + }; + }; + }; + + cpu-1-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu6_emerg1: cpu6-emerg1-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu11_cdev { + trip = <&cpu6_emerg1>; + cooling-device = <&cpu6_pause 1 1>; + }; + }; + }; + + cpu-1-2 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 11>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu7_emerg0: cpu7-emerg0-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu12_cdev { + trip = <&cpu7_emerg0>; + cooling-device = <&cpu7_pause 1 1>; + }; + }; + }; + + cpu-1-3 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 12>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu7_emerg1: cpu7-emerg1-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu13_cdev { + trip = <&cpu7_emerg1>; + cooling-device = <&cpu7_pause 1 1>; + }; + }; + }; + + gpuss { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 13>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpu_tj_cfg: tj_cfg { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + gpu_cdev { + trip = <&gpu_tj_cfg>; + cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>; + }; + }; + }; + + camera { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 14>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + video { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 15>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + aoss-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 0>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + ddr { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 1>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + ddr_config0: ddr0-config { + temperature = <90000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + ddr_cdev { + trip = <&ddr_config0>; + cooling-device = <&ddr_cdev 1 1>; + }; + }; + }; + + mdmss-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 2>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdmss-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 3>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdmss-2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 4>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdmss-3 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 5>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + zeroc-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 128>; + trips { + thermal-engine-config { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + + min_temp_0_trip: cold-trip { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + zeroc-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 128>; + trips { + thermal-engine-config { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + + min_temp_1_trip: cold-trip { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + cx-pe { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&cx_pe>; + + trips { + cx_pe_config1: cx-pe-config1 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + + cooling-maps { + gpu_cdev { + trip = <&cx_pe_config1>; + cooling-device = <&msm_gpu 3 3>; + }; + + }; + }; +}; diff --git a/qcom/ravelin-usb.dtsi b/qcom/ravelin-usb.dtsi new file mode 100644 index 00000000..3038be02 --- /dev/null +++ b/qcom/ravelin-usb.dtsi @@ -0,0 +1,325 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&soc { + usb0: ssusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xa600000 0x100000>; + reg-names = "core_base"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; + clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + interrupts-extended = <&pdc 14 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 15 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + + qcom,use-pdc-interrupts; + + qcom,core-clk-rate = <133333333>; + qcom,core-clk-rate-hs = <66666667>; + qcom,pm-qos-latency = <2>; + qcom,num-gsi-evt-buffs = <0x3>; + qcom,gsi-reg-offset = + <0x0fc /* GSI_GENERAL_CFG */ + 0x110 /* GSI_DBL_ADDR_L */ + 0x120 /* GSI_DBL_ADDR_H */ + 0x130 /* GSI_RING_BASE_ADDR_L */ + 0x144 /* GSI_RING_BASE_ADDR_H */ + 0x1a4>; /* GSI_IF_STS */ + + usb-role-switch; + + interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; + interconnects = <&aggre2_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_USB3_0 &cnoc2 SLAVE_IPA_CFG>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_USB3_0>; + + extcon = <&eud>; + + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0xa600000 0xd800>; + + iommus = <&apps_smmu 0x540 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + dma-coherent; + + interrupts = ; + usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy>; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,is-utmi-l1-suspend; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + tx-fifo-resize; + dr_mode = "otg"; + maximum-speed = "super-speed"; + usb-role-switch; + }; + + port { + usb_port0: endpoint { + remote-endpoint = <&usb_port0_connector>; + }; + }; + }; + + /* USB port related High Speed PHY */ + usb2_phy0: hsphy@88e3000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e3000 0x11c>, + <0x088e2000 0x4>; + reg-names = "hsusb_phy_base", + "eud_enable_reg"; + + vdd-supply = <&L5B>; + vdda18-supply = <&L23B>; + vdda33-supply = <&L25B>; + qcom,vdd-voltage-level = <0 880000 920000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_EUSB3_0_CLKREF_EN>; + clock-names = "ref_clk_src", "ref_clk"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + /* USB port related QMP USB DP Combo PHY */ + usb_qmp_dp_phy: ssphy@88e8000 { + compatible = "qcom,usb-ssphy-qmp-dp-combo"; + reg = <0x88e8000 0x3000>; + reg-names = "qmp_phy_base"; + + vdd-supply = <&L7B>; + qcom,vdd-voltage-level = <0 912000 912000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&L16B>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_0_CLKREF_EN>; + clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", + "pipe_clk_ext_src", "ref_clk_src", + "com_aux_clk", "ref_clk"; + + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "global_phy_reset", "phy_reset"; + + pinctrl-names = "default"; + pinctrl-0 = <&usb3phy_portselect_default>; + + qcom,qmp-phy-reg-offset = + ; + + qcom,qmp-phy-init-seq = + /* */ + ; + }; + + usb_audio_qmi_dev { + compatible = "qcom,usb-audio-qmi-dev"; + iommus = <&apps_smmu 0x100f 0x0>; + qcom,iommu-dma = "disabled"; + qcom,usb-audio-stream-id = <0xf>; + qcom,usb-audio-intr-num = <2>; + }; + +}; diff --git a/qcom/ravelin-wcn6750.dtsi b/qcom/ravelin-wcn6750.dtsi new file mode 100644 index 00000000..1944911e --- /dev/null +++ b/qcom/ravelin-wcn6750.dtsi @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + qcom,smp2p-wpss { + smp2p_wlan_2_in: qcom,smp2p-wlan-2-in { + qcom,entry-name = "wlan_soc_wake"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_wlan_2_out: qcom,smp2p-wlan-2-out { + qcom,entry-name = "wlan_soc_wake"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_wlan_3_out: qcom,smp2p-wlan-3-out { + qcom,entry-name = "wlan_ep_power_save"; + #qcom,smem-state-cells = <1>; + }; + }; + + wpss_pas: remoteproc-wpss@8a00000 { + firmware-name = "qca6750/wpss.mdt"; + }; + + icnss2: qcom,wcn6750 { + status = "disabled"; + compatible = "qcom,wcn6750"; + reg = <0x17210040 0x0>, + <0xb0000000 0x10000>; + reg-names = "msi_addr", "smmu_iova_ipa"; + qcom,rproc-handle = <&wpss_pas>; + iommus = <&apps_smmu 0x1400 0x1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + qcom,iommu-dma = "fastmap"; + qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal"; + qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; + qcom,iommu-geometry = <0xa0000000 0x10010000>; + dma-coherent; + qcom,fw-prefix; + qcom,wlan; + tsens = "quiet-therm"; + qcom,wlan-msa-fixed-region = <&wlan_msa_mem>; + vdd-cx-mx-supply = <&S7B>; + qcom,vdd-cx-mx-config = <1010000 1120000 0 0 1>; + vdd-1.8-xo-supply = <&S9B>; + qcom,vdd-1.8-xo-config = <1856000 2040000 0 0 0>; + vdd-1.3-rfa-supply = <&S8B>; + qcom,vdd-1.3-rfa-config = <1250000 1352000 0 0 0>; + + qcom,smem-states = <&smp2p_wlan_1_out 0>, + <&smp2p_wlan_2_out 0>, + <&smp2p_wlan_3_out 0>; + qcom,smem-state-names = "wlan-smp2p-out", + "wlan-soc-wake-smp2p-out", + "wlan-ep-powersave-smp2p-out"; + + icnss_cdev_apss: qcom,icnss_cdev1 { + #cooling-cells = <2>; + }; + + icnss_cdev_wpss: qcom,icnss_cdev2 { + #cooling-cells = <2>; + }; + + qcom,smp2p_map_wlan_1_in { + interrupts-extended = <&smp2p_wlan_1_in 0 0>, + <&smp2p_wlan_1_in 1 0>; + interrupt-names = "qcom,smp2p-force-fatal-error", + "qcom,smp2p-early-crash-ind"; + }; + + qcom,smp2p_map_wlan_2_in { + interrupts-extended = <&smp2p_wlan_2_in 0 0>; + interrupt-names = "qcom,smp2p-soc-wake-ack"; + }; + }; + +}; + diff --git a/qcom/ravelin.dts b/qcom/ravelin.dts new file mode 100644 index 00000000..fd772285 --- /dev/null +++ b/qcom/ravelin.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin SoC"; + compatible = "qcom,ravelin"; + qcom,board-id = <0 0>; +}; + diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi new file mode 100644 index 00000000..03f7f28e --- /dev/null +++ b/qcom/ravelin.dtsi @@ -0,0 +1,2569 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + model = "Qualcomm Technologies, Inc. Ravelin"; + compatible = "qcom,ravelin"; + qcom,msm-id = <568 0x10000>; + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen: chosen { + stdout-path = "/soc/qcom,qup_uart@a88000:115200n8"; + bootargs = "console=ttyMSM0,115200n8 loglevel=6 log_buf_len=256K kernel.panic_on_rcu_stall=1 loop.max_part=7 pcie_ports=compat kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 ftrace_dump_on_oops pstore.compress=none kpti=0 swiotlb=noforce cgroup.memory=nokmem,nosocket kswapd_per_node=2 slub_debug=- allow_file_spec_access cpufreq.default_governor=performance transparent_hugepage=never can.stats_timer=0 disable_dma32=on android12_only.will_be_removed_soon.memblock_nomap_remove=on pcie_ports=compat"; + }; + + memory { device_type = "memory"; reg = <0 0 0 0>; }; + + ddr-regions { }; + + reserved_memory: reserved-memory { }; + + mem-offline { + compatible = "qcom,mem-offline"; + offline-sizes = <0x1 0x40000000 0x0 0x40000000>, + <0x1 0xc0000000 0x0 0x80000000>, + <0x2 0xc0000000 0x1 0x40000000>; + granule = <512>; + mboxes = <&qmp_aop 0>; + }; + + aliases: aliases { + serial0 = &qupv3_se7_2uart; /* Debug UART */ + serial1 = &qupv3_se0_2uart; /* HST debug UART */ + hsuart0 = &qupv3_se2_4uart; + ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ + mmc0 = &sdhc_1; /*SDC1 eMMC slot*/ + mmc1 = &sdhc_2; /* SDC2 SD card slot */ + }; + + mmio_sram: mmio-sram@17D09100 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "mmio-sram"; + reg = <0x0 0x17D09100 0x0 0x200>; + ranges = <0x0 0x0 0x0 0x17D09100 0x0 0x200>; + + cpu_scp_lpri: scp-shmem@0 { + compatible = "arm,scp-shmem"; + reg = <0x0 0x0 0x0 0x200>; + }; + }; + + firmware: firmware {}; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + cpu-idle-states = <&SILVER_CPU_OFF &SILVER_CPU_RAIL_OFF>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0 8>; + next-level-cache = <&L2_0>; + #cooling-cells = <2>; + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + + L3_0: l3-cache { + compatible = "cache"; + cache-level = <3>; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x100>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + cpu-idle-states = <&SILVER_CPU_OFF &SILVER_CPU_RAIL_OFF>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0 8>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + L2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x200>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + cpu-idle-states = <&SILVER_CPU_OFF &SILVER_CPU_RAIL_OFF>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0 8>; + next-level-cache = <&L2_2>; + #cooling-cells = <2>; + L2_2: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x300>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + cpu-idle-states = <&SILVER_CPU_OFF &SILVER_CPU_RAIL_OFF>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0 8>; + next-level-cache = <&L2_3>; + #cooling-cells = <2>; + L2_3: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x400>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + cpu-idle-states = <&SILVER_CPU_OFF &SILVER_CPU_RAIL_OFF>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; + next-level-cache = <&L2_4>; + #cooling-cells = <2>; + qcom,freq-domain = <&cpufreq_hw 0 8>; + L2_4: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x500>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + cpu-idle-states = <&SILVER_CPU_OFF &SILVER_CPU_RAIL_OFF>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0 8>; + next-level-cache = <&L2_5>; + #cooling-cells = <2>; + L2_5: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x600>; + capacity-dmips-mhz = <1945>; + dynamic-power-coefficient = <483>; + enable-method = "psci"; + cpu-idle-states = <&GOLD_CPU_OFF &GOLD_CPU_RAIL_OFF>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1 8>; + next-level-cache = <&L2_6>; + #cooling-cells = <2>; + L2_6: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x700>; + capacity-dmips-mhz = <1945>; + dynamic-power-coefficient = <483>; + enable-method = "psci"; + cpu-idle-states = <&GOLD_CPU_OFF &GOLD_CPU_RAIL_OFF>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1 8>; + next-level-cache = <&L2_7>; + #cooling-cells = <2>; + L2_7: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU6>; + }; + + core1 { + cpu = <&CPU7>; + }; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + SILVER_CPU_OFF: silver-c3 { /* C3 */ + compatible = "arm,idle-state"; + idle-state-name = "pc"; + entry-latency-us = <350>; + exit-latency-us = <900>; + min-residency-us = <1774>; + arm,psci-suspend-param = <0x40000003>; + local-timer-stop; + }; + + SILVER_CPU_RAIL_OFF: silver-c4 { /* C4 */ + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <800>; + exit-latency-us = <750>; + min-residency-us = <4090>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + + GOLD_CPU_OFF: gold-c3 { /* C3 */ + compatible = "arm,idle-state"; + idle-state-name = "pc"; + entry-latency-us = <400>; + exit-latency-us = <1550>; + min-residency-us = <2207>; + arm,psci-suspend-param = <0x40000003>; + local-timer-stop; + }; + + GOLD_CPU_RAIL_OFF: gold-c4 { /* C4 */ + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <600>; + exit-latency-us = <1550>; + min-residency-us = <4791>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + + CLUSTER_OFF: cluster-d4 { /* D4 */ + compatible = "domain-idle-state"; + idle-state-name = "l3-off"; + entry-latency-us = <1050>; + exit-latency-us = <2500>; + min-residency-us = <5309>; + arm,psci-suspend-param = <0x41000044>; + }; + + CX_RET: cx-ret { /* Cx Ret */ + compatible = "domain-idle-state"; + idle-state-name = "cx-ret"; + entry-latency-us = <1561>; + exit-latency-us = <2801>; + min-residency-us = <8550>; + arm,psci-suspend-param = <0x41003344>; + }; + }; + + soc: soc { }; + +}; + +#include "msm-arm-smmu-ravelin.dtsi" +#include "ravelin-dma-heaps.dtsi" +#include "ravelin-reserved-memory.dtsi" +#include "ravelin-dma-heaps.dtsi" +#include "ravelin-usb.dtsi" +#include "ravelin-coresight.dtsi" +#include "ravelin-debug.dtsi" + +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + system_cma: linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + linux,cma-default; + }; + + ramoops_mem: ramoops_region { + alloc-ranges = <0x0 0x00000000 0xffffffff 0xffffffff>; + size = <0x0 0x200000>; + no-map; + }; + + va_md_mem: va_md_mem_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x1 0x00000000 0xfffffffe 0xffffffff>; + reusable; + size = <0 0x1000000>; + }; + + user_contig_mem: user_contig_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + adsp_mem_heap: adsp_heap_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0xC00000>; + }; + + audio_cma_mem: audio_cma_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1C00000>; + }; + + non_secure_display_memory: non_secure_display_region { + compatible = "shared-dma-pool"; + reusable; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + size = <0x0 0x5c00000>; + alignment = <0x0 0x400000>; + }; +}; + +&firmware { + qcom_scm { + compatible = "qcom,scm"; + qcom,dload-mode = <&tcsr 0x13000>; + }; + + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + }; + + qcom_smcinvoke { + compatible = "qcom,smcinvoke"; + }; + +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@17200000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0x17200000 0x10000>, /* GICD */ + <0x17260000 0x100000>; /* GICR * 8 */ + interrupts = ; + }; + + wdog: qcom,wdt@17410000 { + compatible = "qcom,msm-watchdog"; + reg = <0x17410000 0x1000>; + reg-names = "wdt-base"; + interrupts = , + ; + qcom,bark-time = <11000>; + qcom,pet-time = <9360>; + qcom,ipi-ping; + qcom,wakeup-enable; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; + + apps_rsc: rsc@17a00000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x17a00000 0x10000>, + <0x17a10000 0x10000>, + <0x17a20000 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + + qcom,drv-count = <3>; + power-domains = <&CLUSTER_PD>; + + apps_rsc_drv2: drv@2 { + qcom,drv-id = <2>; + qcom,tcs-offset = <0xd00>; + channel@0 { + qcom,tcs-config = , + , + , + , + ; + }; + + rpmhcc: qcom,rpmhclk { + compatible = "qcom,sm4450-rpmh-clk"; + #clock-cells = <1>; + }; + + apps_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + }; + }; + }; + + bluetooth: bt_wcn3990 { + compatible = "qcom,wcn3990"; + qcom,bt-sw-ctrl-gpio = <&tlmm 56 GPIO_ACTIVE_HIGH>; + qcom,bt-vdd-io-supply = <&L21B>; /* IO */ + qcom,bt-vdd-core-supply = <&L14B>; /* RFA */ + qcom,bt-vdd-pa-supply = <&L7E>; /* CH0 */ + qcom,bt-vdd-xtal-supply = <&L23B>; /* XO */ + + qcom,bt-vdd-io-config = <1700000 1900000 1 0>; + qcom,bt-vdd-core-config = <1304000 1304000 1 0>; + qcom,bt-vdd-pa-config = <3000000 3312000 1 0>; + qcom,bt-vdd-xtal-config = <1700000 1900000 1 0>; + }; + + disp_rsc: rsc@af20000 { + lable = "disp_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0xaf20000 0x10000>; + reg-names = "drv-0"; + interrupts = ; + clocks = <&dispcc DISP_CC_MDSS_RSCC_AHB_CLK>; + qcom,drv-count = <1>; + + disp_rsc_drv0: drv@0 { + qcom,tcs-offset = <0x1c00>; + qcom,drv-id = <0>; + channel@0 { + qcom,tcs-config = , + , + , + , + ; + }; + + disp_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + qcom,tcs-wait = ; + qcom,no-amc; + }; + }; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,ravelin-pdc", "qcom,pdc"; + reg = <0xb220000 0x30000>, <0x174000f0 0x64>; + reg-names = "pdc-interrupt-base", "apps-shared-spi-cfg"; + qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>, + <126 716 12>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: cpu-pd0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD1: cpu-pd1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD2: cpu-pd2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD3: cpu-pd3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD4: cpu-pd4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD5: cpu-pd5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD6: cpu-pd6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD7: cpu-pd7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CLUSTER_PD: cluster-pd { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_OFF &CX_RET>; + }; + }; + + slimbam: bamdma@3304000 { + compatible = "qcom,bam-v1.7.0"; + qcom,controlled-remotely; + reg = <0x3304000 0x20000>, <0x326b000 0x1000>; + reg-names = "bam", "bam_remote_mem"; + num-channels = <31>; + interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + qcom,ee = <1>; + qcom,num-ees = <2>; + }; + + slim_msm: slim@3340000 { + compatible = "qcom,slim-ngd-v1.5.0"; + reg = <0x3340000 0x2C000>, <0x326a000 0x1000>; + reg-names = "ctrl", "slimbus_remote_mem"; + interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; + qcom,apps-ch-pipes = <0x0>; + qcom,ea-pc = <0x440>; + dmas = <&slimbam 3>, <&slimbam 4>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "ok"; + }; + + cluster-device { + compatible = "qcom,lpm-cluster-dev"; + power-domains = <&CLUSTER_PD>; + }; + + cpuss-sleep-stats@17800054 { + compatible = "qcom,cpuss-sleep-stats"; + reg = <0x17800054 0x4>, <0x17810054 0x4>, <0x17820054 0x4>, + <0x17830054 0x4>, <0x17840054 0x4>, <0x17850054 0x4>, + <0x17860054 0x4>, <0x17870054 0x4>, <0x17880098 0x4>, + <0x178C0000 0x10000>; + reg-names = "seq_lpm_cntr_cfg_cpu0", "seq_lpm_cntr_cfg_cpu1", + "seq_lpm_cntr_cfg_cpu2", "seq_lpm_cntr_cfg_cpu3", + "seq_lpm_cntr_cfg_cpu4", "seq_lpm_cntr_cfg_cpu5", + "seq_lpm_cntr_cfg_cpu6", "seq_lpm_cntr_cfg_cpu7", + "l3_seq_lpm_cntr_cfg", "apss_seq_mem_base"; + num-cpus = <8>; + }; + + sram@c3f0000 { + compatible = "qcom,rpmh-stats-v3"; + reg = <0xc3f0000 0x400>; + ss-name = "modem", "adsp", "adsp_island", + "apss", "wpss"; + qcom,qmp = <&aoss_qmp>; + }; + + sys-pm-vx@c320000 { + compatible = "qcom,sys-pm-violators", "qcom,sys-pm-ravelin"; + reg = <0xc320000 0x0400>; + qcom,qmp = <&aoss_qmp>; + }; + + memtimer: timer@17420000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17420000 0x1000>; + clock-frequency = <19200000>; + + frame@17421000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x17421000 0x1000>, + <0x17422000 0x1000>; + }; + + frame@17423000 { + frame-number = <1>; + interrupts = ; + reg = <0x17423000 0x1000>; + status = "disabled"; + }; + + frame@17425000 { + frame-number = <2>; + interrupts = ; + reg = <0x17425000 0x1000>; + status = "disabled"; + }; + + frame@17427000 { + frame-number = <3>; + interrupts = ; + reg = <0x17427000 0x1000>; + status = "disabled"; + }; + + frame@17429000 { + frame-number = <4>; + interrupts = ; + reg = <0x17429000 0x1000>; + status = "disabled"; + }; + + frame@1742b000 { + frame-number = <5>; + interrupts = ; + reg = <0x1742b000 0x1000>; + status = "disabled"; + }; + + frame@1742d000 { + frame-number = <6>; + interrupts = ; + reg = <0x1742d000 0x1000>; + status = "disabled"; + }; + }; + + cpucp: qcom,cpucp@17400000 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "qcom,cpucp"; + reg = <0x17400000 0x10>, + <0x17d90000 0x2000>; + reg-names = "rx", "tx"; + #mbox-cells = <1>; + interrupts = ; + }; + + scmi: qcom,scmi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "arm,scmi"; + mboxes = <&cpucp 0>; + mbox-names = "tx"; + shmem = <&cpu_scp_lpri>; + + scmi_pmu: protocol@86 { + reg = <0x86>; + #clock-cells = <1>; + }; + + scmi_plh: protocol@81 { + reg = <0x81>; + #clock-cells = <1>; + }; + + scmi_cpufreqstat: protocol@84 { + reg = <0x84>; + #clock-cells = <1>; + }; + + scmi_shared_rail: protocol@88 { + reg = <0x88>; + #clock-cells = <1>; + }; + }; + + cpucp_log: qcom,cpucp_log@17d09c00 { + compatible = "qcom,cpucp-log"; + reg = <0x17d09c00 0x200>, <0x17d09e00 0x200>; + mboxes = <&cpucp 1>; + }; + + qcom,secure-buffer { + compatible = "qcom,secure-buffer"; + qcom,vmid-cp-camera-preview-ro; + }; + + qcom,mem-buf { + compatible = "qcom,mem-buf"; + qcom,mem-buf-capabilities = "supplier"; + qcom,vmid = <3>; + }; + + qcom,mem-buf-msgq { + compatible = "qcom,mem-buf-msgq"; + }; + + qcom,rmtfs_sharedmem@0 { + compatible = "qcom,sharedmem-uio"; + reg = <0x0 0x280000>; + reg-names = "rmtfs"; + qcom,client-id = <0x00000001>; + }; + + qcom_tzlog: tz-log@146AA720 { + compatible = "qcom,tz-log"; + reg = <0x146AA720 0x3000>; + qcom,hyplog-enabled; + hyplog-address-offset = <0x410>; + hyplog-size-offset = <0x414>; + tmecrashdump-address-offset = <0x808a0000>; + status = "ok"; + }; + + qcom_qseecom: qseecom@c1700000 { + memory-region = <&qseecom_mem>; + qseecom_mem = <&qseecom_mem>; + qseecom_ta_mem = <&qseecom_ta_mem>; + user_contig_mem = <&user_contig_mem>; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,no-clock-support; + qcom,appsbl-qseecom-support; + qcom,commonlib64-loaded-by-uefi; + qcom,qsee-reentrancy-support = <2>; + }; + + ipcc_mproc: qcom,ipcc@ed18000 { + compatible = "qcom,ipcc"; + reg = <0xed18000 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + qcom,memshare { + compatible = "qcom,memshare"; + + qcom,client_1 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <0>; + qcom,allocate-boot-time; + label = "modem"; + }; + + qcom,client_2 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <2>; + label = "modem"; + }; + + mem_client_3_size: qcom,client_3 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x500000>; + qcom,client-id = <1>; + qcom,allocate-on-request; + label = "modem"; + }; + }; + + clocks { + xo_board: xo_board { + compatible = "fixed-clock"; + clock-frequency = <76800000>; + clock-output-names = "xo_board"; + #clock-cells = <0>; + }; + + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + clock-output-names = "sleep_clk"; + #clock-cells = <0>; + }; + + pcie_0_pipe_clk: pcie_0_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie_0_pipe_clk"; + #clock-cells = <0>; + }; + + ufs_phy_rx_symbol_0_clk: ufs_phy_rx_symbol_0_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "ufs_phy_rx_symbol_0_clk"; + #clock-cells = <0>; + }; + + ufs_phy_rx_symbol_1_clk: ufs_phy_rx_symbol_1_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "ufs_phy_rx_symbol_1_clk"; + #clock-cells = <0>; + }; + + ufs_phy_tx_symbol_0_clk: ufs_phy_tx_symbol_0_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "ufs_phy_tx_symbol_0_clk"; + #clock-cells = <0>; + }; + + usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk"; + #clock-cells = <0>; + }; + }; + + camcc: clock-controller@ade0000 { + compatible = "qcom,sm4450-camcc", "syscon"; + reg = <0xade0000 0x20000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "bi_tcxo", "iface"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sm4450-dispcc", "syscon"; + reg = <0xaf00000 0x20000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&gcc GCC_DISP_AHB_CLK>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "iface"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gcc: clock-controller@100000 { + compatible = "qcom,sm4450-gcc", "syscon"; + reg = <0x100000 0x1f4200>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, + <&pcie_0_pipe_clk>, <&ufs_phy_rx_symbol_0_clk>, + <&ufs_phy_rx_symbol_1_clk>, <&ufs_phy_tx_symbol_0_clk>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; + clock-names = "bi_tcxo", "sleep_clk", + "pcie_0_pipe_clk", "ufs_phy_rx_symbol_0_clk", + "ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk", + "usb3_phy_wrapper_gcc_usb30_pipe_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,sm4450-gpucc", "syscon"; + reg = <0x3d90000 0xa000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + clock-names = "bi_tcxo", "gpll0_out_main", + "gpll0_out_main_div", "gcc_gpu_snoc_dvm_gfx_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + apsscc: syscon@17aa0000 { + compatible = "syscon"; + reg = <0x17aa0000 0x1c>; + }; + + mccc: syscon@190ba000 { + compatible = "syscon"; + reg = <0x190ba000 0x54>; + }; + + debugcc: debug-clock-controller@0 { + compatible = "qcom,sm4450-debugcc"; + qcom,gcc = <&gcc>; + qcom,dispcc = <&dispcc>; + qcom,camcc = <&camcc>; + qcom,gpucc = <&gpucc>; + qcom,apsscc = <&apsscc>; + qcom,mccc = <&mccc>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc 0>, + <&camcc 0>, + <&dispcc 0>, + <&gpucc 0>; + clock-names = "xo_clk_src", + "gcc", + "camcc", + "dispcc", + "gpucc"; + #clock-cells = <1>; + }; + + cpufreq_hw: qcom,cpufreq-hw { + compatible = "qcom,cpufreq-epss"; + reg = <0x17d91000 0x1000>, <0x17d92000 0x1000>; + reg-names = "freq-domain0", "freq-domain1"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + qcom,lut-row-size = <4>; + qcom,skip-enable-check; + interrupts = , + ; + interrupt-names = "dcvsh0_int", "dcvsh1_int"; + #freq-domain-cells = <2>; + }; + + qcom,cpufreq-hw-debug { + qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>; + }; + + tcsr: syscon@1fc0000 { + compatible = "syscon"; + reg = <0x1fc0000 0x30000>; + }; + + tcsr_mutex_block: syscon@1f40000 { + compatible = "syscon"; + reg = <0x1f40000 0x20000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + smem: qcom,smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + }; + + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sleepstate_smp2p_out: sleepstate-out { + qcom,entry-name = "sleepstate"; + #qcom,smem-state-cells = <1>; + }; + + sleepstate_smp2p_in: qcom,sleepstate-in { + qcom,entry-name = "sleepstate_see"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg2_out: qcom,smp2p-rdbg2-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg2_in: qcom,smp2p-rdbg2-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p_sleepstate { + compatible = "qcom,smp2p-sleepstate"; + qcom,smem-states = <&sleepstate_smp2p_out 0>; + interrupt-parent = <&sleepstate_smp2p_in>; + interrupts = <0 0>; + interrupt-names = "smp2p-sleepstate-in"; + }; + + qcom,smp2p-wpss { + compatible = "qcom,smp2p"; + qcom,smem = <617>, <616>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_WPSS IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <13>; + + wpss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + wpss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_wlan_1_in: qcom,smp2p-wlan-1-in { + qcom,entry-name = "wlan"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_wlan_1_out: qcom,smp2p-wlan-1-out { + qcom,entry-name = "wlan"; + #qcom,smem-state-cells = <1>; + }; + }; + + qcom,glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + }; + + qcom,glink { + compatible = "qcom,glink"; + }; + + aoss_qmp: power-controller@c300000 { + compatible = "qcom,aoss-qmp"; + reg = <0xc300000 0x400>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + qmp_aop: qcom,qmp-aop { + compatible = "qcom,qmp-mbox"; + qcom,qmp = <&aoss_qmp>; + label = "aop"; + #mbox-cells = <1>; + }; + + qmp_tme: qcom,qmp-tme { + compatible = "qcom,qmp-mbox"; + qcom,remote-pid = <14>; + mboxes = <&ipcc_mproc IPCC_CLIENT_TME + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "tme_qmp"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "tme"; + qcom,early-boot; + priority = <0>; + mbox-desc-offset = <0x0>; + #mbox-cells = <1>; + }; + + qcom,tmecom-qmp-client { + compatible = "qcom,tmecom-qmp-client"; + mboxes = <&qmp_tme 0>; + mbox-names = "tmecom"; + label = "tmecom"; + depends-on-supply = <&qmp_tme>; + }; + + qcom_cedev: qcedev@1de0000 { + compatible = "qcom,qcedev"; + reg = <0x1de0000 0x20000>, + <0x1dc4000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = ; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,ce-hw-shared; + qcom,bam-ee = <0>; + qcom,smmu-s1-enable; + qcom,no-clock-support; + interconnect-names = "data_path"; + interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + iommus = <&apps_smmu 0x0480 0x0>, + <&apps_smmu 0x0481 0x0>; + qcom,iommu-dma = "atomic"; + dma-coherent; + + qcom_cedev_ns_cb { + compatible = "qcom,qcedev,context-bank"; + label = "ns_context"; + iommus = <&apps_smmu 0x0481 0x0>; + dma-coherent; + }; + + qcom_cedev_s_cb { + compatible = "qcom,qcedev,context-bank"; + label = "secure_context"; + iommus = <&apps_smmu 0x0483 0x0>; + qcom,iommu-vmid = <0x9>; + qcom,secure-context-bank; + dma-coherent; + }; + }; + + ufsphy_mem: ufsphy_mem@1d87000 { + reg = <0x1d87000 0xe10>; + reg-names = "phy_mem"; + #phy-cells = <0>; + + lanes-per-direction = <2>; + clock-names = "ref_clk_src", + "ref_aux_clk", "qref_clk", + "rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk", + "rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_0_CLKREF_EN>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC>, + <&ufs_phy_rx_symbol_0_clk>, + <&ufs_phy_rx_symbol_1_clk>, + <&ufs_phy_tx_symbol_0_clk>; + resets = <&ufshc_mem 0>; + status = "disabled"; + }; + + ufshc_mem: ufshc@1d84000 { + compatible = "qcom,ufshc"; + reg = <0x1d84000 0x3000>, + <0x1d88000 0x8000>, + <0x1d90000 0x9000>; + reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm"; + interrupts = ; + phys = <&ufsphy_mem>; + phy-names = "ufsphy"; + #reset-cells = <1>; + + lanes-per-direction = <2>; + dev-ref-clk-freq = <0>; /* 19.2 MHz */ + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <100000000 403000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + interconnects = <&aggre2_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_UFS_MEM_CFG>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + + qcom,ufs-bus-bw,name = "ufshc_mem"; + qcom,ufs-bus-bw,num-cases = <26>; + qcom,ufs-bus-bw,num-paths = <2>; + qcom,ufs-bus-bw,vectors-KBps = + /* + * During HS G3 UFS runs at nominal voltage corner, vote + * higher bandwidth to push other buses in the data path + * to run at nominal to achieve max throughput. + * 4GBps pushes BIMC to run at nominal. + * 200MBps pushes CNOC to run at nominal. + * Vote for half of this bandwidth for HS G3 1-lane. + * For max bandwidth, vote high enough to push the buses + * to run in turbo voltage corner. + */ + <0 0>, <0 0>, /* No vote */ + <922 0>, <1000 0>, /* PWM G1 */ + <1844 0>, <1000 0>, /* PWM G2 */ + <3688 0>, <1000 0>, /* PWM G3 */ + <7376 0>, <1000 0>, /* PWM G4 */ + <1844 0>, <1000 0>, /* PWM G1 L2 */ + <3688 0>, <1000 0>, /* PWM G2 L2 */ + <7376 0>, <1000 0>, /* PWM G3 L2 */ + <14752 0>, <1000 0>, /* PWM G4 L2 */ + <127796 0>, <1000 0>, /* HS G1 RA */ + <255591 0>, <1000 0>, /* HS G2 RA */ + <1492582 0>, <102400 0>, /* HS G3 RA */ + <2915200 0>, <204800 0>, /* HS G4 RA */ + <255591 0>, <1000 0>, /* HS G1 RA L2 */ + <511181 0>, <1000 0>, /* HS G2 RA L2 */ + <1492582 0>, <204800 0>, /* HS G3 RA L2 */ + <2915200 0>, <409600 0>, /* HS G4 RA L2 */ + <149422 0>, <1000 0>, /* HS G1 RB */ + <298189 0>, <1000 0>, /* HS G2 RB */ + <1492582 0>, <102400 0>, /* HS G3 RB */ + <2915200 0>, <204800 0>, /* HS G4 RB */ + <298189 0>, <1000 0>, /* HS G1 RB L2 */ + <596378 0>, <1000 0>, /* HS G2 RB L2 */ + /* As UFS working in HS G3 RB L2 mode, aggregated + * bandwidth (AB) should take care of providing + * optimum throughput requested. However, as tested, + * in order to scale up CNOC clock, instantaneous + * bindwidth (IB) needs to be given a proper value too. + */ + <1492582 0>, <204800 409600>, /* HS G3 RB L2 KBPs */ + <2915200 0>, <409600 409600>, /* HS G4 RB L2 */ + <7643136 0>, <307200 0>; /* Max. bandwidth */ + + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", + "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1", + "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1", + "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2", + "MAX"; + + reset-gpios = <&tlmm 136 GPIO_ACTIVE_LOW>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + iommus = <&apps_smmu 0x580 0x0>; + qcom,iommu-dma = "fastmap"; + dma-coherent; + + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + + status = "disabled"; + + qos0 { + mask = <0xf0>; + vote = <44>; + perf; + }; + + qos1 { + mask = <0x0f>; + vote = <44>; + }; + }; + + qcom_pmu: qcom,pmu { + compatible = "qcom,pmu"; + reg = < 0x17D09300 0x300>; + reg-names = "pmu-base"; + qcom,pmu-events-tbl = + < 0x0008 0xFF 0xFF 0x02 >, + < 0x0011 0xFF 0xFF 0x00 >, + < 0x0017 0xFF 0xFF 0xFF >, + < 0x002A 0xFF 0xFF 0xFF >, + < 0x4005 0xC0 0xFF 0xFF >; + }; + + ddr_freq_table: ddr-freq-table { + ddr4 { + qcom,ddr-type = <7>; + qcom,freq-tbl = + < 547000 >, + < 768000 >, + < 1017000 >, + < 1353600 >, + < 1555000 >, + < 1708000 >, + < 2092000 >; + }; + + ddr5 { + qcom,ddr-type = <8>; + qcom,freq-tbl = + < 547000 >, + < 768000 >, + < 1555000 >, + < 1708000 >, + < 2092000 >, + < 2736000 >, + < 3196000 >; + }; + }; + + ddrqos_freq_table: ddrqos-freq-table { + qcom,freq-tbl = + < 0 >, + < 1 >; + }; + + qcom_dcvs: qcom,dcvs { + compatible = "qcom,dcvs"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + qcom_l3_dcvs_hw: l3 { + compatible = "qcom,dcvs-hw"; + qcom,dcvs-hw-type = <2>; + qcom,bus-width = <32>; + reg = <0x17d90000 0x4000>, <0x17d90100 0xa0>; + reg-names = "l3-base", "l3tbl-base"; + + l3_dcvs_sp: sp { + compatible = "qcom,dcvs-path"; + qcom,dcvs-path-type = <0>; + qcom,shared-offset = <0x0090>; + }; + }; + + qcom_ddr_dcvs_hw: ddr { + compatible = "qcom,dcvs-hw"; + qcom,dcvs-hw-type = <0>; + qcom,bus-width = <4>; + qcom,freq-tbl = <&ddr_freq_table>; + + ddr_dcvs_sp: sp { + compatible = "qcom,dcvs-path"; + qcom,dcvs-path-type = <0>; + interconnects = <&gem_noc MASTER_APPSS_PROC + &mc_virt SLAVE_EBI1>; + }; + }; + + qcom_ddrqos_dcvs_hw: ddrqos { + compatible = "qcom,dcvs-hw"; + qcom,dcvs-hw-type = <3>; + qcom,bus-width = <1>; + qcom,freq-tbl = <&ddrqos_freq_table>; + + ddrqos_dcvs_sp: sp { + compatible = "qcom,dcvs-path"; + qcom,dcvs-path-type = <0>; + interconnects = <&gem_noc MASTER_APPSS_PROC + &mc_virt SLAVE_EBI1>; + }; + }; + }; + + qcom_memlat: qcom,memlat { + compatible = "qcom,memlat"; + qcom,be-stall-ev = <0x4005>; + + ddr { + compatible = "qcom,memlat-grp"; + qcom,target-dev = <&qcom_ddr_dcvs_hw>; + qcom,sampling-path = <&ddr_dcvs_sp>; + qcom,miss-ev = <0x2A>; + + silver { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + qcom,sampling-enabled; + ddr4-tbl { + qcom,ddr-type = <7>; + qcom,cpufreq-memfreq-tbl = + < 1094400 547000 >, + < 1478400 768000 >, + < 1804800 1017000 >; + }; + + ddr5-tbl { + qcom,ddr-type = <8>; + qcom,cpufreq-memfreq-tbl = + < 1094400 547000 >, + < 1478400 768000 >, + < 1804800 1555000 >; + }; + }; + + gold { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,sampling-enabled; + ddr4-tbl { + qcom,ddr-type = <7>; + qcom,cpufreq-memfreq-tbl = + < 960000 547000 >, + < 1190400 1017000 >, + < 1497600 1353600 >, + < 1651200 1555000 >, + < 2131200 1708000 >, + < 2400000 2092000 >; + }; + + ddr5-tbl { + qcom,ddr-type = <8>; + qcom,cpufreq-memfreq-tbl = + < 960000 547000 >, + < 1651200 1555000 >, + < 1900800 1708000 >, + < 2131200 2092000 >, + < 2400000 3196000 >; + }; + }; + + silver-compute { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + qcom,sampling-enabled; + qcom,compute-mon; + ddr4-tbl { + qcom,ddr-type = <7>; + qcom,cpufreq-memfreq-tbl = + < 1478400 547000 >, + < 1804800 768000 >; + }; + + ddr5-tbl { + qcom,ddr-type = <8>; + qcom,cpufreq-memfreq-tbl = + < 1478400 547000 >, + < 1804800 768000 >; + }; + }; + + gold-compute { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,sampling-enabled; + qcom,compute-mon; + ddr4-tbl { + qcom,ddr-type = <7>; + qcom,cpufreq-memfreq-tbl = + < 1190400 547000 >, + < 1497600 768000 >, + < 1651200 1017000 >, + < 1900800 1555000 >, + < 2131200 1708000 >, + < 2400000 2092000 >; + }; + + ddr5-tbl { + qcom,ddr-type = <8>; + qcom,cpufreq-memfreq-tbl = + < 1190400 547000 >, + < 1497600 768000 >, + < 1651200 1017000 >, + < 2054400 1555000 >, + < 2131200 1708000 >, + < 2400000 2092000 >; + }; + }; + + }; + + l3 { + compatible = "qcom,memlat-grp"; + qcom,target-dev = <&qcom_l3_dcvs_hw>; + qcom,sampling-path = <&l3_dcvs_sp>; + qcom,miss-ev = <0x17>; + + silver { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + qcom,cpufreq-memfreq-tbl = + < 499200 307200 >, + < 672000 556800 >, + < 806400 652800 >, + < 921600 825600 >, + < 1094400 940800 >, + < 1286400 1075200 >, + < 1478400 1209600 >, + < 1632000 1305600 >, + < 1804800 1440000 >; + qcom,sampling-enabled; + }; + + gold { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,cpufreq-memfreq-tbl = + < 691200 307200 >, + < 960000 556800 >, + < 1190400 825600 >, + < 1344000 940800 >, + < 1651200 1209600 >, + < 1900800 1305600 >, + < 2054400 1401600 >, + < 2208000 1440000 >; + qcom,sampling-enabled; + }; + + gold-compute { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,cpufreq-memfreq-tbl = + < 2054400 307200 >, + < 2361600 1401600 >; + qcom,sampling-enabled; + qcom,compute-mon; + }; + + }; + + ddrqos { + compatible = "qcom,memlat-grp"; + qcom,target-dev = <&qcom_ddrqos_dcvs_hw>; + qcom,sampling-path = <&ddrqos_dcvs_sp>; + qcom,miss-ev = <0x2A>; + + ddrqos_gold_lat: gold { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,cpufreq-memfreq-tbl = + < 2300000 0 >, + < 3000000 1 >; + qcom,sampling-enabled; + }; + + }; + }; + + bwmon_ddr: qcom,bwmon-ddr@19091000 { + compatible = "qcom,bwmon5"; + reg = <0x19091000 0x1000>; + reg-names = "base"; + interrupts = ; + qcom,hw-timer-hz = <19200000>; + qcom,count-unit = <0x10000>; + qcom,target-dev = <&qcom_ddr_dcvs_hw>; + }; + + sdhc1_opp_table: sdhc1-opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-peak-kBps = <1600000 280000>; + opp-avg-kBps = <104000 0>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + opp-peak-kBps = <5600000 1500000>; + opp-avg-kBps = <400000 0>; + }; + }; + + sdhc_1: sdhci@7C4000 { + status = "disabled"; + + compatible = "qcom,sdhci-msm-v5"; + reg = <0x007C4000 0x1000>, <0x007C5000 0x1000>, + <0x007C8000 0x8000>, <0x007D0000 0x9000>; + reg-names = "hc", "cqhci", "cqhci_ice", "cqhci_ice_hwkm"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + bus-width = <8>; + non-removable; + supports-cqe; + + no-sd; + no-sdio; + + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + qcom,devfreq,freq-table = <50000000 200000000>; + qcom,scaling-lower-bus-speed-mode = "DDR52"; + + cap-mmc-hw-reset; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "iface", "core", "ice_core"; + + qcom,ice-clk-rates = <300000000 100000000>; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x000F642C 0x0 0x01 + 0x2C010800 0x80040868>; + + /* Add dt entry for gcc hw reset */ + resets = <&gcc GCC_SDCC1_BCR>; + reset-names = "core_reset"; + + iommus = <&apps_smmu 0x560 0x0>; + dma-coherent; + qcom,iommu-dma = "fastmap"; + + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + + interconnects = <&aggre2_noc MASTER_SDCC_1 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_SDC1>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + operating-points-v2 = <&sdhc1_opp_table>; + + qos0 { + mask = <0x03>; + vote = <44>; + }; + + qos1 { + mask = <0x3f>; + vote = <44>; + }; + }; + + sdhc2_opp_table: sdhc2-opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-peak-kBps = <1600000 280000>; + opp-avg-kBps = <50000 0>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + opp-peak-kBps = <5600000 1500000>; + opp-avg-kBps = <104000 0>; + }; + }; + + sdhc_2: sdhci@8804000 { + status = "disabled"; + + compatible = "qcom,sdhci-msm-v5"; + reg = <0x08804000 0x1000>; + reg-names = "hc"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + bus-width = <4>; + no-sdio; + no-mmc; + qcom,restore-after-cx-collapse; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>; + clock-names = "iface", "core"; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x0007642C 0x0 0x10 + 0x2C010800 0x80040868>; + + iommus = <&apps_smmu 0x140 0x0>; + dma-coherent; + qcom,iommu-dma = "fastmap"; + + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + + interconnects = <&aggre1_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_SDCC_2>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + operating-points-v2 = <&sdhc2_opp_table>; + + qos0 { + mask = <0x03>; + vote = <44>; + }; + + qos1 { + mask = <0x3f>; + vote = <44>; + }; + }; + + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + msm_gpu: qcom,kgsl-3d0@3d00000 { }; + + qcom,msm-imem@146aa000 { + compatible = "qcom,msm-imem"; + ranges = <0x0 0x146aa000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x4>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 0xc>; + }; + + pil@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + + pil@6dc { + compatible = "qcom,msm-imem-pil-disable-timeout"; + reg = <0x6dc 0x4>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 0xc8>; + }; + }; + + qcom,mpm2-sleep-counter@c221000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0xc221000 0x1000>; + clock-frequency = <32768>; + }; + + qcom_ramoops { + compatible = "qcom,ramoops"; + memory-region = <&ramoops_mem>; + pmsg-size = <0x200000>; + mem-type = <2>; + }; + + logbuf: qcom,logbuf-vendor-hooks { + compatible = "qcom,logbuf-vendor-hooks"; + }; + + mini_dump_node { + compatible = "qcom,minidump"; + status = "ok"; + }; + + va_mini_dump { + compatible = "qcom,va-minidump"; + memory-region = <&va_md_mem>; + status = "ok"; + }; + + qcom,msm-adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <&adsp_mem_heap>; + restrict-access; + }; + + qcom,sps { + compatible = "qcom,msm-sps-4k"; + qcom,pipe-attr-ee; + }; + + msm_fastrpc: qcom,msm_fastrpc { + compatible = "qcom,msm-fastrpc-compute"; + qcom,adsp-remoteheap-vmid = <22 37>; + qcom,fastrpc-adsp-audio-pdr; + qcom,fastrpc-adsp-sensors-pdr; + qcom,rpc-latency-us = <235>; + qcom,fastrpc-gids = <2908>; + qcom,qos-cores = <0 1 2 3 4 5>; + + qcom,msm_fastrpc_compute_cb1 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1003 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb2 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1004 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb3 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1005 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + shared-cb = <4>; + }; + }; + + clk_virt: interconnect@0 { + compatible = "qcom,ravelin-clk_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect@1 { + compatible = "qcom,ravelin-mc_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + reg = <0x16E0000 0x13080>; + compatible = "qcom,ravelin-aggre1_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_SDCC2_AHB_CLK>; + }; + + aggre2_noc: interconnect@1700000 { + reg = <0x1700000 0x1B080>; + compatible = "qcom,ravelin-aggre2_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&rpmhcc RPMH_IPA_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; + }; + + cnoc2: interconnect@1500000 { + reg = <0x1500000 0x6200>; + compatible = "qcom,ravelin-cnoc2"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + cnoc3: interconnect@1510000 { + reg = <0x01510000 0xF200>; + compatible = "qcom,ravelin-cnoc3"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gem_noc: interconnect@19100000 { + reg = <0x19100000 0xBC080>; + compatible = "qcom,ravelin-gem_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + }; + + lpass_ag_noc: interconnect@3C40000 { + reg = <0x3C40000 0x17200>; + compatible = "qcom,ravelin-lpass_ag_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1740000 { + reg = <0x1740000 0x19080>; + compatible = "qcom,ravelin-mmss_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + }; + + pcie_anoc: interconnect@16C0000 { + reg = <0x16C0000 0x7080>; + compatible = "qcom,ravelin-pcie_anoc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; + }; + + system_noc: interconnect@1680000 { + reg = <0x1680000 0x19080>; + compatible = "qcom,ravelin-system_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + video_aggre_noc: interconnect@1760000 { + reg = <0x1760000 0x1100>; + compatible = "qcom,ravelin-video_aggre_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + qfprom: qfprom@221c8000 { + compatible = "qcom,ravelin-qfprom", "qcom,qfprom"; + reg = <0x221c8000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + read-only; + ranges; + + feat_conf12: feat_conf12@0130 { + reg = <0x0130 0x4>; + }; + + feat_conf13: feat_conf13@0134 { + reg = <0x0134 0x4>; + }; + + boot_config: boot_config@600 { + reg = <0x600 0x1>; + }; + + gpu_speed_bin: gpu_speed_bin@119 { + reg = <0x119 0x2>; + bits = <5 8>; + }; + }; + + qfprom_sys: qfprom@0 { + compatible = "qcom,qfprom-sys"; + nvmem-cells = <&feat_conf12>, + <&feat_conf13>, + <&boot_config>, + <&gpu_speed_bin>; + nvmem-cell-names = "feat_conf12", + "feat_conf13", + "boot_config", + "gpu_speed_bin"; + }; + + adsp_pas: remoteproc-adsp@03000000 { + compatible = "qcom,ravelin-adsp-pas"; + reg = <0x03000000 0x10000>; + status = "ok"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + cx-supply = <&VDD_LPI_CX_LEVEL>; + cx-uV-uA = ; + mx-supply = <&VDD_LPI_MX_LEVEL>; + mx-uV-uA = ; + reg-names = "cx", "mx"; + + interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + interconnect-names = "crypto_ddr"; + + qcom,qmp = <&aoss_qmp>; + memory-region = <&adsp_mem>; + + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 0>, + <&adsp_smp2p_in 2 0>, + <&adsp_smp2p_in 1 0>, + <&adsp_smp2p_in 3 0>, + <&adsp_smp2p_in 7 0>; + + interrupt-names = "wdog", + "fatal", + "handover", + "ready", + "stop-ack", + "shutdown-ack"; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink_edge: glink-edge { + qcom,remote-pid = <2>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "adsp_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "adsp"; + qcom,glink-label = "lpass"; + + qcom,adsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + + qcom,no-wake-svc = <0x190>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + }; + + }; + + modem_pas: remoteproc-mss@04080000 { + compatible = "qcom,ravelin-modem-pas"; + reg = <0x4080000 0x10000>; + status = "ok"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + cx-supply = <&VDD_CX_LEVEL>; + cx-uV-uA = ; + mx-supply = <&VDD_MODEM_LEVEL>; + mx-uV-uA = ; + reg-names = "cx", "mx"; + + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + interconnect-names = "rproc_ddr","crypto_ddr"; + + qcom,qmp = <&aoss_qmp>; + memory-region = <&mpss_mem &system_cma>; + + /* Inputs from mss */ + interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 0>, + <&modem_smp2p_in 2 0>, + <&modem_smp2p_in 1 0>, + <&modem_smp2p_in 3 0>, + <&modem_smp2p_in 7 0>; + + interrupt-names = "wdog", + "fatal", + "handover", + "ready", + "stop-ack", + "shutdown-ack"; + + /* Outputs to mss */ + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + qcom,remote-pid = <1>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "mpss_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "modem"; + qcom,glink-label = "mpss"; + + qcom,modem_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,modem_ds { + qcom,glink-channels = "DS"; + qcom,intents = <0x4000 0x2>; + }; + }; + }; + + wpss_pas: remoteproc-wpss@8a00000 { + compatible = "qcom,ravelin-wpss-pas"; + reg = <0x08a00000 0x10000>; + status = "ok"; + + memory-region = <&wpss_moselle_mem>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + cx-supply = <&VDD_CX_LEVEL>; + cx-uV-uA = ; + mx-supply = <&VDD_MX_LEVEL>; + mx-uV-uA = ; + reg-names = "cx","mx"; + + qcom,qmp = <&aoss_qmp>; + + /* Inputs from wpss */ + interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, + <&wpss_smp2p_in 0 0>, + <&wpss_smp2p_in 2 0>, + <&wpss_smp2p_in 1 0>, + <&wpss_smp2p_in 3 0>, + <&wpss_smp2p_in 7 0>; + + interrupt-names = "wdog", + "fatal", + "handover", + "ready", + "stop-ack", + "shutdown-ack"; + + /* Outputs to wpss */ + qcom,smem-states = <&wpss_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + qcom,remote-pid = <13>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "wpss_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "wpss"; + qcom,glink-label = "wpss"; + + qcom,wpss_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + }; + }; + + spmi_bus: spmi0_bus: qcom,spmi@c42d000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc42d000 0x4000>, + <0xc400000 0x3000>, + <0xc500000 0x400000>, + <0xc440000 0x80000>, + <0xc4c0000 0x10000>; + reg-names = "cnfg", "core", "chnls", "obsrvr", "intr"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + cell-index = <0>; + qcom,channel = <0>; + qcom,ee = <0>; + qcom,bus-id = <0>; + }; + + spmi0_debug_bus: qcom,spmi-debug@10b14000 { + compatible = "qcom,spmi-pmic-arb-debug"; + reg = <0x10b14000 0x60>, <0x221c8784 0x4>; + reg-names = "core", "fuse"; + clocks = <&aoss_qmp>; + clock-names = "core_clk"; + qcom,fuse-enable-bit = <18>; + #address-cells = <2>; + #size-cells = <0>; + depends-on-supply = <&spmi0_bus>; + + qcom,pmk8350-debug@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm6450-debug@1 { + compatible = "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm8010-debug@4 { + compatible = "qcom,spmi-pmic"; + reg = <4 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pmg1110-debug@6 { + compatible = "qcom,spmi-pmic"; + reg = <6 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + }; + + qcom,pmic_glink { + compatible = "qcom,qti-pmic-glink"; + qcom,pmic-glink-channel = "PMIC_RTR_ADSP_APPS"; + qcom,subsys-name = "lpass"; + qcom,protection-domain = "tms/servreg", "msm/adsp/charger_pd"; + depends-on-supply = <&ipcc_mproc>; + status = "disabled"; + + battery_charger: qcom,battery_charger { + compatible = "qcom,battery-charger"; + status = "disabled"; + }; + + ucsi: qcom,ucsi { + compatible = "qcom,ucsi-glink"; + status = "disabled"; + connector { + port { + usb_port0_connector: endpoint { + remote-endpoint = <&usb_port0>; + }; + }; + }; + }; + + altmode: qcom,altmode { + compatible = "qcom,altmode-glink"; + #altmode-cells = <1>; + status = "disabled"; + }; + }; + + thermal_zones: thermal-zones { + }; + + eud: qcom,msm-eud@88e0000 { + compatible = "qcom,msm-eud"; + interrupt-names = "eud_irq"; + interrupt-parent = <&pdc>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x088e0000 0x2000>, + <0x088e2000 0x1000>; + reg-names = "eud_base", "eud_mode_mgr2"; + clocks = <&gcc GCC_EUSB3_0_CLKREF_EN>; + clock-names = "eud_clkref_clk"; + qcom,secure-eud-en; + status = "ok"; + }; + + qrtr-gunyah { + compatible = "qcom,qrtr-gunyah"; + qcom,master; + gunyah-label = <3>; + peer-name = <2>; + shared-buffer = <&trust_ui_vm_qrtr>; + }; + + trust_ui_vm: qcom,trust_ui_vm@e55fc000 { + reg = <0xe55fc000 0x104000>; + vm_name = "trustedvm"; + shared-buffers = <&trust_ui_vm_vblk0_ring &trust_ui_vm_swiotlb>; + }; + + qcom,virtio_backend@0 { + compatible = "qcom,virtio_backend"; + qcom,vm = <&trust_ui_vm>; + qcom,label = <0x11>; + }; + + vendor_hooks: qcom,cpu-vendor-hooks { + compatible = "qcom,cpu-vendor-hooks"; + }; + +}; + +#include "ravelin-pinctrl.dtsi" +#include "diwali-gdsc.dtsi" +#include "ipcc-test-ravelin.dtsi" +#include "ravelin-qupv3.dtsi" +#include "ravelin-regulators.dtsi" +#include "ravelin-pcie.dtsi" +#include "ravelin-wcn6750.dtsi" + +&qupv3_se7_2uart { + status = "ok"; +}; + +&qupv3_se2_4uart { + status = "ok"; +}; + +&gcc_pcie_0_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gcc_ufs_phy_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gcc_usb30_prim_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gcc_vcodec0_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gcc_venus_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&cam_cc_camss_top_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; + qcom,support-hw-trigger; + status = "ok"; +}; + +&disp_cc_mdss_core_gdsc { + clocks = <&gcc GCC_DISP_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&disp_cc_mdss_core_int2_gdsc { + clocks = <&gcc GCC_DISP_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gpu_cc_cx_gdsc { + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gpu_cc_gx_gdsc { + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; + sw-reset = <&gpu_cc_gx_sw_reset>; + status = "ok"; +}; + +&qupv3_se8_i2c { + status = "ok"; + fsa4480: fsa4480@42 { + reg = <0x42>; + }; +}; + +#include "ravelin-thermal.dtsi" +#include "ravelin-msm-rdbg.dtsi" diff --git a/qcom/ravelinp-4gb.dts b/qcom/ravelinp-4gb.dts new file mode 100644 index 00000000..892d1dfa --- /dev/null +++ b/qcom/ravelinp-4gb.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelinp-4gb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. RavelinP 4Gb SoC"; + compatible = "qcom,ravelinp"; + qcom,board-id = <0 0x600>; +}; diff --git a/qcom/ravelinp-4gb.dtsi b/qcom/ravelinp-4gb.dtsi new file mode 100644 index 00000000..55da1771 --- /dev/null +++ b/qcom/ravelinp-4gb.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelinp.dtsi" +#include "ravelin-low-memory.dtsi" +/ { +}; + +&soc { +}; diff --git a/qcom/ravelinp-atp.dts b/qcom/ravelinp-atp.dts new file mode 100644 index 00000000..13710535 --- /dev/null +++ b/qcom/ravelinp-atp.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelinp.dtsi" +#include "ravelinp-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. RavelinP ATP"; + compatible = "qcom,ravelinp-atp", "qcom,ravelinp", "qcom,atp"; + qcom,board-id = <33 0>; +}; diff --git a/qcom/ravelinp-atp.dtsi b/qcom/ravelinp-atp.dtsi new file mode 100644 index 00000000..1a4b89e5 --- /dev/null +++ b/qcom/ravelinp-atp.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-atp.dtsi" diff --git a/qcom/ravelinp-idp-wcn3950-amoled-rcm.dts b/qcom/ravelinp-idp-wcn3950-amoled-rcm.dts new file mode 100644 index 00000000..8e9e430e --- /dev/null +++ b/qcom/ravelinp-idp-wcn3950-amoled-rcm.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelinp.dtsi" +#include "ravelinp-idp-wcn3950-amoled-rcm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. RavelinP WCN3950 IDP + AMOLED + RCM"; + compatible = "qcom,ravelinp-idp", "qcom,ravelinp", "qcom,idp"; + qcom,board-id = <34 2>; +}; diff --git a/qcom/ravelinp-idp-wcn3950-amoled-rcm.dtsi b/qcom/ravelinp-idp-wcn3950-amoled-rcm.dtsi new file mode 100644 index 00000000..47d70c57 --- /dev/null +++ b/qcom/ravelinp-idp-wcn3950-amoled-rcm.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-idp-wcn3950-amoled-rcm.dtsi" diff --git a/qcom/ravelinp-idp-wcn3988-4gb.dts b/qcom/ravelinp-idp-wcn3988-4gb.dts new file mode 100644 index 00000000..b3a2acf8 --- /dev/null +++ b/qcom/ravelinp-idp-wcn3988-4gb.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelinp-4gb.dtsi" +#include "ravelinp-idp-wcn3988-4gb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. RavelinP IDP 4GB DDR + WCN3988"; + compatible = "qcom,ravelinp-idp", "qcom,ravelinp", "qcom,idp"; + qcom,board-id = <34 0x601>; +}; diff --git a/qcom/ravelinp-idp-wcn3988-4gb.dtsi b/qcom/ravelinp-idp-wcn3988-4gb.dtsi new file mode 100644 index 00000000..228c590a --- /dev/null +++ b/qcom/ravelinp-idp-wcn3988-4gb.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-idp-wcn3988-4gb.dtsi" + diff --git a/qcom/ravelinp-idp.dts b/qcom/ravelinp-idp.dts new file mode 100644 index 00000000..b93d89fe --- /dev/null +++ b/qcom/ravelinp-idp.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelinp.dtsi" +#include "ravelinp-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. RavelinP IDP"; + compatible = "qcom,ravelinp-idp", "qcom,ravelinp", "qcom,idp"; + qcom,board-id = <34 0>; +}; diff --git a/qcom/ravelinp-idp.dtsi b/qcom/ravelinp-idp.dtsi new file mode 100644 index 00000000..122b06c7 --- /dev/null +++ b/qcom/ravelinp-idp.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-idp.dtsi" diff --git a/qcom/ravelinp-qrd-4gb.dts b/qcom/ravelinp-qrd-4gb.dts new file mode 100644 index 00000000..9b1d66c8 --- /dev/null +++ b/qcom/ravelinp-qrd-4gb.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelinp-4gb.dtsi" +#include "ravelinp-qrd-4gb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. RavelinP QRD 4GB DDR"; + compatible = "qcom,ravelinp-qrd", "qcom,ravelinp", "qcom,qrd"; + qcom,board-id = <0x1000B 0x600>; +}; diff --git a/qcom/ravelinp-qrd-4gb.dtsi b/qcom/ravelinp-qrd-4gb.dtsi new file mode 100644 index 00000000..c0e0c1bc --- /dev/null +++ b/qcom/ravelinp-qrd-4gb.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-qrd.dtsi" diff --git a/qcom/ravelinp-qrd.dts b/qcom/ravelinp-qrd.dts new file mode 100644 index 00000000..ecfcb70e --- /dev/null +++ b/qcom/ravelinp-qrd.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelinp.dtsi" +#include "ravelinp-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. RavelinP QRD"; + compatible = "qcom,ravelinp-qrd", "qcom,ravelinp", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; +}; + diff --git a/qcom/ravelinp-qrd.dtsi b/qcom/ravelinp-qrd.dtsi new file mode 100644 index 00000000..c0e0c1bc --- /dev/null +++ b/qcom/ravelinp-qrd.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-qrd.dtsi" diff --git a/qcom/ravelinp.dts b/qcom/ravelinp.dts new file mode 100644 index 00000000..184fdca6 --- /dev/null +++ b/qcom/ravelinp.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelinp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. RavelinP SoC"; + compatible = "qcom,ravelinp"; + qcom,board-id = <0 0>; +}; + diff --git a/qcom/ravelinp.dtsi b/qcom/ravelinp.dtsi new file mode 100644 index 00000000..a3bc1041 --- /dev/null +++ b/qcom/ravelinp.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin.dtsi" +/ { + model = "Qualcomm Technologies, Inc. RavelinP"; + compatible = "qcom,ravelinp"; + qcom,msm-id = <602 0x10000>; +};