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ARM: dts: msm: Add initial device tree for ravelin

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Add initial device tree support for ravelin target.
This is a snapshot of dtsi files as of KP.1.0
'commit <370d8eab7cc6> ("Merge "ARM: dts: qcom:
Disable cnss-kiwi SOL on anorak platform"")'.
Modified as per compilation and bootup.

Change-Id: Icb9a6e67879c68dbf894d1713fa2837882b9f00c
Signed-off-by: Swetha Chikkaboraiah <quic_schikk@quicinc.com>
This commit is contained in:
Swetha Chikkaboraiah
2024-03-04 13:52:23 +05:30
parent 1a1d6a94be
commit 1b78f8027a
66 changed files with 17076 additions and 0 deletions
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20
qcom/Makefile
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@@ -125,6 +125,26 @@ parrot-dtb-$(CONFIG_ARCH_PARROT) += \
parrot-overlays-dtb-$(CONFIG_ARCH_PARROT) += $(PARROT_BOARDS) $(PARROT_BASE_DTB) $(PARROT_4GB_BOARDS) $(PARROT_4GB_BASE_DTB)
dtb-y += $(parrot-dtb-y)
RAVELIN_BASE_DTB += ravelin.dtb ravelinp.dtb
RAVELIN_4GB_BASE_DTB += ravelin-4gb.dtb ravelinp-4gb.dtb
RAVELIN_BOARDS += \
ravelin-rumi-overlay.dtbo \
ravelin-atp-overlay.dtbo \
ravelin-idp-overlay.dtbo \
ravelin-idp-wcn3950-amoled-rcm-overlay.dtbo \
ravelin-qrd-overlay.dtbo \
RAVELIN_4GB_BOARDS += \
ravelin-idp-wcn3988-4gb-overlay.dtbo \
ravelin-qrd-4gb-overlay.dtbo \
parrot-dtb-$(CONFIG_ARCH_RAVELIN) += \
$(call add-overlays, $(RAVELIN_BOARDS),$(RAVELIN_BASE_DTB)) \
$(call add-overlays, $(RAVELIN_4GB_BOARDS),$(RAVELIN_4GB_BASE_DTB))
parrot-overlays-dtb-$(CONFIG_ARCH_RAVELIN) += $(RAVELIN_BOARDS) $(RAVELIN_BASE_DTB) $(RAVELIN_4GB_BOARDS) $(RAVELIN_4GB_BASE_DTB)
dtb-y += $(parrot-dtb-y)
endif
ifeq ($(CONFIG_ARCH_PINEAPPLE), y)

10
qcom/ipcc-test-ravelin.dtsi Normal file
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@@ -0,0 +1,10 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "ipcc-test.dtsi"
&soc {
/delete-node/ ipcc-self-ping-slpi;
};

379
qcom/msm-arm-smmu-ravelin.dtsi Normal file
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@@ -0,0 +1,379 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
&soc {
kgsl_smmu: kgsl-smmu@3da0000 {
compatible = "qcom,qsmmu-v500", "qcom,adreno-smmu";
reg = <0x3da0000 0x10000>,
<0x3dc2000 0x20>;
reg-names = "base", "tcu-base";
#iommu-cells = <2>;
qcom,use-3-lvl-tables;
qcom,num-context-banks-override = <0x5>;
qcom,num-smr-override = <0x7>;
#global-interrupts = <1>;
#size-cells = <1>;
#address-cells = <1>;
ranges;
dma-coherent;
qcom,regulator-names = "vdd";
vdd-supply = <&gpu_cc_cx_gdsc>;
qcom,actlr =
/* All CBs of GFX: +15 deep PF */
<0x0 0x1FFF 0x32B>;
clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
<&gpucc GPU_CC_HUB_CX_INT_CLK>,
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
<&gpucc GPU_CC_AHB_CLK>;
clock-names =
"gpu_cc_cx_gmu",
"gpu_cc_hub_cx_int",
"gpu_cc_hlos1_vote_gpu_smmu",
"gcc_gpu_memnoc_gfx",
"gcc_gpu_snoc_dvm_gfx",
"gpu_cc_ahb";
interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
gfx_0_tbu: gfx_0_tbu@3dc5000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x3dc5000 0x1000>,
<0x3dc2200 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x0 0x400>;
};
gfx_1_tbu: gfx_1_tbu@3dc9000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x3dc9000 0x1000>,
<0x3dc2208 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x400 0x400>;
};
};
apps_smmu: apps-smmu@15000000 {
compatible = "qcom,qsmmu-v500";
reg = <0x15000000 0x100000>,
<0x151e2000 0x20>;
reg-names = "base", "tcu-base";
#iommu-cells = <2>;
qcom,use-3-lvl-tables;
qcom,num-context-banks-override = <0x52>;
qcom,num-smr-override = <0x85>;
qcom,handoff-smrs = <0x800 0x402>;
#global-interrupts = <1>;
#size-cells = <1>;
#address-cells = <1>;
ranges;
dma-coherent;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>;
qcom,actlr =
/* For video clients, +3 PF */
<0x1980 0x3F 0x103>,
/* Display and camera clients, +0 PF */
<0x1900 0x3F 0x1>,
<0x1800 0xFF 0x1>,
<0x800 0x7FF 0x1>;
clocks = <&gcc GCC_HLOS1_VOTE_MMU_TCU_CLK>;
clock-names =
"gcc_hlos1_vote_mmu_tcu_clk";
interconnects = <&gem_noc MASTER_APPSS_PROC
&cnoc3 SLAVE_TCU>;
qcom,active-only;
anoc_1_tbu: anoc_1_tbu@151e5000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x151e5000 0x1000>,
<0x151e2200 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x0 0x400>;
qcom,iova-width = <36>;
qcom,micro-idle;
clocks = <&gcc GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK>;
clock-names =
"gcc_hlos1_vote_aggre_noc_mmu_tbu1_clk";
interconnects = <&gem_noc MASTER_APPSS_PROC
&cnoc3 SLAVE_IMEM>;
qcom,active-only;
};
anoc_2_tbu: anoc_2_tbu@151e9000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x151e9000 0x1000>,
<0x151e2208 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x400 0x400>;
qcom,iova-width = <36>;
qcom,micro-idle;
clocks = <&gcc GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK>;
clock-names =
"gcc_hlos1_vote_aggre_noc_mmu_tbu2_clk";
interconnects = <&gem_noc MASTER_APPSS_PROC
&cnoc3 SLAVE_IMEM>;
qcom,active-only;
};
mnoc_hf_0_tbu: mnoc_hf_0_tbu@151ed000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x151ed000 0x1000>,
<0x151e2210 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x800 0x400>;
qcom,iova-width = <32>;
qcom,micro-idle;
qcom,regulator-names = "vdd";
vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>;
clocks = <&gcc GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_CLK>;
clock-names =
"gcc_hlos1_vote_mmnoc_mmu_tbu_hf0_clk";
interconnects = <&mmss_noc MASTER_CAMNOC_HF
&mc_virt SLAVE_EBI1>;
qcom,active-only;
};
mnoc_hf_1_tbu: mnoc_hf_1_tbu@151f1000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x151f1000 0x1000>,
<0x151e2218 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0xc00 0x400>;
qcom,iova-width = <32>;
qcom,micro-idle;
qcom,regulator-names = "vdd";
vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc>;
clocks = <&gcc GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_CLK>;
clock-names =
"gcc_hlos1_vote_mmnoc_mmu_tbu_hf1_clk";
interconnects = <&mmss_noc MASTER_CAMNOC_HF
&mc_virt SLAVE_EBI1>;
qcom,active-only;
};
lpass_tbu: lpass_tbu@151f5000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x151f5000 0x1000>,
<0x151e2220 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x1000 0x400>;
qcom,iova-width = <32>;
qcom,micro-idle;
clocks = <&gcc GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK>;
clock-names =
"gcc_hlos1_vote_aggre_noc_mmu_audio_tbu_clk";
interconnects = <&lpass_ag_noc MASTER_LPASS_PROC
&mc_virt SLAVE_EBI1>;
qcom,active-only;
};
pcie_tbu: pcie_tbu@151f9000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x151f9000 0x1000>,
<0x151e2228 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x1400 0x400>;
qcom,iova-width = <36>;
qcom,micro-idle;
clocks = <&gcc GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK>;
clock-names =
"gcc_hlos1_vote_aggre_noc_mmu_pcie_tbu_clk";
interconnects = <&pcie_anoc MASTER_PCIE_0
&mc_virt SLAVE_EBI1>;
qcom,active-only;
};
sf_0_tbu: sf_0_tbu@151fd000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x151fd000 0x1000>,
<0x151e2230 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x1800 0x400>;
qcom,iova-width = <32>;
qcom,regulator-names = "vdd";
vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc>;
qcom,micro-idle;
clocks = <&gcc GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_CLK>;
clock-names =
"gcc_hlos1_vote_mmnoc_mmu_tbu_sf0_clk";
interconnects = <&mmss_noc MASTER_CAMNOC_SF
&mc_virt SLAVE_EBI1>;
qcom,active-only;
};
};
dma_dev@0x0 {
compatible = "qcom,iommu-dma";
memory-region = <&system_cma>;
};
iommu_test_device {
compatible = "qcom,iommu-debug-test";
usecase0_apps {
compatible = "qcom,iommu-debug-usecase";
iommus = <&apps_smmu 0x7e0 0>;
};
usecase1_apps_fastmap {
compatible = "qcom,iommu-debug-usecase";
iommus = <&apps_smmu 0x7e0 0>;
qcom,iommu-dma = "fastmap";
};
usecase2_apps_atomic {
compatible = "qcom,iommu-debug-usecase";
iommus = <&apps_smmu 0x7e0 0>;
qcom,iommu-dma = "atomic";
};
usecase3_apps_dma {
compatible = "qcom,iommu-debug-usecase";
iommus = <&apps_smmu 0x7e0 0>;
qcom,iommu-dma = "atomic";
};
usecase4_apps_coherent {
compatible = "qcom,iommu-debug-usecase";
iommus = <&apps_smmu 0x7e1 0>;
dma-coherent;
};
usecase5_kgsl_dma {
compatible = "qcom,iommu-debug-usecase";
iommus = <&kgsl_smmu 0x7 0x400>;
};
usecase6_kgsl_coherent {
compatible = "qcom,iommu-debug-usecase";
iommus = <&kgsl_smmu 0x407 0x400>;
dma-coherent;
};
usecase7_apps_secure {
compatible = "qcom,iommu-debug-usecase";
iommus = <&apps_smmu 0x7e0 0>;
qcom,iommu-dma = "atomic";
qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */
};
};
};

11
qcom/platform_map.bzl
View File

@@ -191,6 +191,10 @@ _platform_map = {
{"name": "parrot-sg.dtb"},
{"name": "parrotp-sg.dtb"},
{"name": "parrot-4gb.dtb"},
{"name": "ravelin.dtb"},
{"name": "ravelinp.dtb"},
{"name": "ravelin-4gb.dtb"},
{"name": "ravelinp-4gb.dtb"},
],
"dtbo_list": [
# keep sorted
@@ -214,6 +218,13 @@ _platform_map = {
{"name": "parrot-idp-wcn6750-amoled-4gb-overlay.dtbo"},
{"name": "parrot-qrd-4gb-overlay.dtbo"},
{"name": "parrot-qrd-wcn6750-4gb-overlay.dtbo"},
{"name": "ravelin-rumi-overlay.dtbo"},
{"name": "ravelin-atp-overlay.dtbo"},
{"name": "ravelin-idp-overlay.dtbo"},
{"name": "ravelin-idp-wcn3950-amoled-rcm-overlay.dtbo"},
{"name": "ravelin-qrd-overlay.dtbo"},
{"name": "ravelin-idp-wcn3988-4gb-overlay.dtbo"},
{"name": "ravelin-qrd-4gb-overlay.dtbo"},
],
},
}

532
qcom/pmi632.dtsi Normal file
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@@ -0,0 +1,532 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/iio/qcom,spmi-vadc.h>
&spmi_bus {
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
pmi632_2: qcom,pmi632@2 {
compatible = "qcom,spmi-pmic";
reg = <2 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmi632_pon: qcom,power-on@800 {
reg = <0x800>;
};
pmi632_vadc: vadc@3100 {
compatible = "qcom,spmi-adc5-lite";
reg = <0x3100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "eoc-int-en-set";
#io-channel-cells = <1>;
io-channel-ranges;
/* Channel nodes */
ref_gnd {
reg = <ADC5_REF_GND>;
label = "ref_gnd";
qcom,pre-scaling = <1 1>;
};
vref_1p25 {
reg = <ADC5_1P25VREF>;
label = "vref_1p25";
qcom,pre-scaling = <1 1>;
};
die_temp {
reg = <ADC5_DIE_TEMP>;
label = "die_temp";
qcom,pre-scaling = <1 1>;
};
vph_pwr {
reg = <ADC5_VPH_PWR>;
label = "vph_pwr";
qcom,pre-scaling = <1 3>;
};
vbat_sns {
reg = <ADC5_VBAT_SNS>;
label = "vbat_sns";
qcom,pre-scaling = <1 3>;
};
usb_in_i_uv {
reg = <ADC5_USB_IN_I>;
label = "usb_in_i_uv";
qcom,pre-scaling = <1 1>;
};
chg_temp {
reg = <ADC5_CHG_TEMP>;
label = "chg_temp";
qcom,pre-scaling = <1 1>;
};
bat_therm {
reg = <ADC5_BAT_THERM_100K_PU>;
label = "bat_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
bat_therm_30k {
reg = <ADC5_BAT_THERM_30K_PU>;
label = "bat_therm_30k";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
bat_therm_400k {
reg = <ADC5_BAT_THERM_400K_PU>;
label = "bat_therm_400k";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
bat_id {
reg = <ADC5_BAT_ID_100K_PU>;
label = "bat_id";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
i_parallel {
reg = <ADC5_PARALLEL_ISENSE>;
label = "i_parallel";
qcom,pre-scaling = <1 1>;
};
};
pmi632_adc_tm: adc_tm@3500 {
reg = <0x3500>;
interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "threshold";
#address-cells = <1>;
#size-cells = <0>;
#thermal-sensor-cells = <1>;
};
pmi632_tz: qcom,temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
interrupts = <0x2 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
io-channels = <&pmi632_vadc ADC5_DIE_TEMP>;
io-channel-names = "thermal";
#thermal-sensor-cells = <0>;
};
qcom,schgm-flash@a600 {
reg = <0xa600>;
interrupts = <0x2 0xa6 0x2 IRQ_TYPE_EDGE_RISING>,
<0x2 0xa6 0x6 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "flash-state-change",
"ilim2-s2";
qcom,flash-disable-soc = <10>;
};
pmi632_gpios: pinctrl@c000 {
reg = <0xc000>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pmi632_pbs_client3: qcom,pbs@7400 {
compatible = "qcom,qpnp-pbs";
reg = <0x7400>;
};
pmi632_sdam7: qcom,sdam@b600 {
compatible = "qcom,spmi-sdam";
reg = <0xb600>;
};
pmi632_bcl: bcl@3d00 {
compatible = "qcom,bcl-v5";
reg = <0x3d00>;
interrupts = <0x2 0x3d 0x0 IRQ_TYPE_NONE>,
<0x2 0x3d 0x1 IRQ_TYPE_NONE>,
<0x2 0x3d 0x2 IRQ_TYPE_NONE>;
interrupt-names = "bcl-lvl0",
"bcl-lvl1",
"bcl-lvl2";
qcom,ibat-use-qg-adc-5a;
#thermal-sensor-cells = <1>;
};
bcl_soc: bcl-soc {
compatible = "qcom,msm-bcl-soc";
#thermal-sensor-cells = <0>;
};
};
pmi632_3: qcom,pmi632@3 {
compatible ="qcom,spmi-pmic";
reg = <3 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmi632_vib: qcom,vibrator@5700 {
reg = <0x5700>;
qcom,vib-ldo-volt-uv = <3000000>;
qcom,disable-overdrive;
};
pmi632_pwm: qcom,pwms@b300 {
reg = <0xb300>;
reg-names = "lpg-base";
#pwm-cells = <2>;
qcom,num-lpg-channels = <5>;
nvmem-names = "ppg_sdam";
nvmem = <&pmi632_sdam7>;
qcom,pbs-client = <&pmi632_pbs_client3>;
qcom,lut-sdam-base = <0x80>;
qcom,lut-patterns = <0 0 0 14 28 42 56 70 84 100
100 84 70 56 42 28 14 0 0 0>;
lpg@1 {
qcom,lpg-chan-id = <1>;
qcom,ramp-step-ms = <200>;
qcom,ramp-low-index = <0>;
qcom,ramp-high-index = <19>;
qcom,ramp-pattern-repeat;
qcom,lpg-sdam-base = <0x48>;
};
lpg@2 {
qcom,lpg-chan-id = <2>;
qcom,ramp-step-ms = <200>;
qcom,ramp-low-index = <0>;
qcom,ramp-high-index = <19>;
qcom,ramp-pattern-repeat;
qcom,lpg-sdam-base = <0x56>;
};
lpg@3 {
qcom,lpg-chan-id = <3>;
qcom,ramp-step-ms = <200>;
qcom,ramp-low-index = <0>;
qcom,ramp-high-index = <19>;
qcom,ramp-pattern-repeat;
qcom,lpg-sdam-base = <0x64>;
};
};
pmi632_rgb: qcom,leds@d000 {
reg = <0xd000>;
red {
label = "red";
pwms = <&pmi632_pwm 0 1000000>;
led-sources = <0>;
linux,default-trigger = "timer";
};
green {
label = "green";
pwms = <&pmi632_pwm 1 1000000>;
led-sources = <1>;
linux,default-trigger = "timer";
};
blue {
label = "blue";
pwms = <&pmi632_pwm 2 1000000>;
led-sources = <2>;
linux,default-trigger = "timer";
};
};
pmi632_lcdb: qpnp-lcdb@ec00 {
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xec00>;
interrupts = <0x3 0xec 0x1 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "sc-irq";
qcom,voltage-step-ramp;
lcdb_ldo_vreg: ldo {
label = "ldo";
regulator-name = "lcdb_ldo";
regulator-min-microvolt = <4000000>;
regulator-max-microvolt = <6000000>;
};
lcdb_ncp_vreg: ncp {
label = "ncp";
regulator-name = "lcdb_ncp";
regulator-min-microvolt = <4000000>;
regulator-max-microvolt = <6000000>;
};
lcdb_bst_vreg: bst {
label = "bst";
regulator-name = "lcdb_bst";
regulator-min-microvolt = <4700000>;
regulator-max-microvolt = <6275000>;
};
};
flash_led: qcom,leds@d300 {
reg = <0xd300>;
label = "flash";
interrupts = <0x3 0xd3 0x0 IRQ_TYPE_EDGE_RISING>,
<0x3 0xd3 0x3 IRQ_TYPE_EDGE_RISING>,
<0x3 0xd3 0x4 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "led-fault-irq",
"all-ramp-down-done-irq",
"all-ramp-up-done-irq";
qcom,short-circuit-det;
qcom,open-circuit-det;
qcom,vph-droop-det;
qcom,thermal-derate-en;
qcom,thermal-derate-current = <200 500 1000>;
qcom,isc-delay = <192>;
pmi632_flash0: qcom,flash_0 {
label = "flash";
qcom,led-name = "led:flash_0";
qcom,max-current = <1500>;
qcom,default-led-trigger = "flash0_trigger";
qcom,id = <0>;
qcom,current-ma = <1000>;
qcom,duration-ms = <1280>;
qcom,ires-ua = <12500>;
qcom,hdrm-voltage-mv = <400>;
qcom,hdrm-vol-hi-lo-win-mv = <100>;
};
pmi632_flash1: qcom,flash_1 {
label = "flash";
qcom,led-name = "led:flash_1";
qcom,max-current = <1500>;
qcom,default-led-trigger = "flash1_trigger";
qcom,id = <1>;
qcom,current-ma = <1000>;
qcom,duration-ms = <1280>;
qcom,ires-ua = <12500>;
qcom,hdrm-voltage-mv = <400>;
qcom,hdrm-vol-hi-lo-win-mv = <100>;
};
pmi632_torch0: qcom,torch_0 {
label = "torch";
qcom,led-name = "led:torch_0";
qcom,max-current = <500>;
qcom,default-led-trigger = "torch0_trigger";
qcom,id = <0>;
qcom,current-ma = <300>;
qcom,ires-ua = <12500>;
qcom,hdrm-voltage-mv = <400>;
qcom,hdrm-vol-hi-lo-win-mv = <100>;
};
pmi632_torch1: qcom,torch_1 {
label = "torch";
qcom,led-name = "led:torch_1";
qcom,max-current = <500>;
qcom,default-led-trigger = "torch1_trigger";
qcom,id = <1>;
qcom,current-ma = <300>;
qcom,ires-ua = <12500>;
qcom,hdrm-voltage-mv = <400>;
qcom,hdrm-vol-hi-lo-win-mv = <100>;
};
pmi632_switch0: qcom,led_switch_0 {
label = "switch";
qcom,led-name = "led:switch_0";
qcom,led-mask = <3>;
qcom,default-led-trigger = "switch0_trigger";
};
pmi632_switch1: qcom,led_switch_1 {
label = "switch";
qcom,led-name = "led:switch_1";
qcom,led-mask = <2>;
qcom,default-led-trigger = "switch1_trigger";
};
};
};
};
&thermal_zones {
pmi632-tz {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pmi632_tz>;
trips {
pmi632_trip0: trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
pmi632_trip1: trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "passive";
};
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "passive";
};
};
};
pmi632-ibat-lvl0 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmi632_bcl 0>;
trips {
ibat_lvl0: ibat-lvl0 {
temperature = <4000>;
hysteresis = <200>;
type = "passive";
};
};
};
pmi632-ibat-lvl1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmi632_bcl 1>;
trips {
ibat_lvl1: ibat-lvl1 {
temperature = <5000>;
hysteresis = <200>;
type = "passive";
};
};
};
pmi632-bcl-lvl0 {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pmi632_bcl 5>;
trips {
thermal-engine-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
thermal-hal-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
b_bcl_lvl0: b-bcl-lvl0 {
temperature = <1>;
hysteresis = <1>;
type = "passive";
};
};
};
pmi632-bcl-lvl1 {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pmi632_bcl 6>;
trips {
thermal-engine-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
thermal-hal-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
b_bcl_lvl1: b-bcl-lvl1 {
temperature = <1>;
hysteresis = <1>;
type = "passive";
};
};
};
pmi632-bcl-lvl2 {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pmi632_bcl 7>;
trips {
thermal-engine-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
thermal-hal-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
b_bcl_lvl2: b-bcl-lvl2 {
temperature = <1>;
hysteresis = <1>;
type = "passive";
};
};
};
socd {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&bcl_soc>;
trips {
thermal-engine-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
thermal-hal-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
socd_trip:socd-trip {
temperature = <90>;
hysteresis = <1>;
type = "passive";
};
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "ravelin-4gb.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Ravelin 4Gb SoC";
compatible = "qcom,ravelin";
qcom,board-id = <0 0x600>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "ravelin.dtsi"
#include "ravelin-low-memory.dtsi"
/ {
};
&mem_client_3_size {
qcom,peripheral-size = <0x200000>;
};
&soc {
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "ravelin-atp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Ravelin ATP";
compatible = "qcom,ravelin-atp", "qcom,ravelin", "qcom,atp";
qcom,msm-id = <568 0x10000>, <602 0x10000>;
qcom,board-id = <33 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "ravelin.dtsi"
#include "ravelin-atp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Ravelin ATP";
compatible = "qcom,ravelin-atp", "qcom,ravelin", "qcom,atp";
qcom,board-id = <33 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "ravelin-pmic-overlay.dtsi"
#include "ravelin-pm7250b.dtsi"
#include "ravelin-thermal-overlay.dtsi"
&soc {
};
&qupv3_se1_spi {
status = "ok";
#address-cells = <1>;
#size-cells = <0>;
qcom,spi-touch-active = "focaltech,fts_ts";
focaltech@0 {
reg = <0x0>;
spi-max-frequency = <6000000>;
interrupt-parent = <&tlmm>;
interrupts = <91 0x2008>;
focaltech,reset-gpio = <&tlmm 90 0x00>;
focaltech,irq-gpio = <&tlmm 91 0x2008>;
focaltech,display-coords = <0 0 1080 2340>;
focaltech,max-touch-number = <5>;
focaltech,ic-type = <0x3658D488>;
focaltech,touch-type = "primary";
vdd-supply = <&L4E>;
pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", "pmx_ts_release";
pinctrl-0 = <&ts_spi_active>;
pinctrl-1 = <&ts_spi_int_suspend &ts_spi_reset_suspend>;
pinctrl-2 = <&ts_spi_release>;
};
};
&sdhc_1 {
status = "ok";
vdd-supply = <&L5E>;
qcom,vdd-current-level = <0 570000>;
vdd-io-supply = <&L19B>;
qcom,vdd-io-always-on;
qcom,vdd-io-lpm-sup;
qcom,vdd-io-current-level = <0 325000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_on>;
pinctrl-1 = <&sdc1_off>;
};
&sdhc_2 {
status = "ok";
vdd-supply = <&L24B>;
qcom,vdd-voltage-level = <2960000 2960000>;
qcom,vdd-current-level = <0 800000>;
/*
* min/max voltages are voted on L24B/L28B and L24B/L28B_PBS
* regulators will only be voted for enabling/disabling conditions
* to support FR84471 for chipsets where PMIC doesn't support
* PBS ram sequence to turn OFF regulators automatically on
* multicard tray removal and these new regulator resources are
* exposed by PMIC team as part of this FR.
*/
vdd-en-dis-supply = <&L24B_PBS>;
vdd-io-supply = <&L28B>;
qcom,vdd-io-voltage-level = <1800000 2960000>;
qcom,vdd-io-current-level = <0 22000>;
vdd-io-en-dis-supply = <&L28B_PBS>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
cd-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
};
&ufsphy_mem {
/*
* Here parrot phy is used for ravelin as it
* do not have its own list for module load and
* hence compatible is using parrot.
* We have plan to improve this by making phy binary
* target independent.
*/
compatible = "qcom,ufs-phy-qmp-v4-waipio";
vdda-phy-supply = <&L5B>;
vdda-pll-supply = <&L16B>;
vdda-phy-max-microamp = <88530>;
vdda-pll-max-microamp = <18310>;
status = "ok";
};
&ufshc_mem {
vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
vcc-supply = <&L5E>;
vcc-max-microamp = <1056000>;
vccq-supply = <&L13B>;
vccq-max-microamp = <750000>;
vccq2-supply = <&L19B>;
vccq2-max-microamp = <750000>;
qcom,vddp-ref-clk-supply = <&L13B>;
qcom,vddp-ref-clk-max-microamp = <100>;
/*
* ufs-dev-types and nvmem entries are for ufs device
* identification using nvmem interface. Use number of
* ufs devices supported for ufs-dev-types, and nvmem handle
* added by pmic for sdam register.
*
* Default value taken by driver is bit[0] = 0 for 3.x and
* bit[0] = 1 for 2.x driver code takes this as default case.
*
* But Bit value to identify ufs device is not consistent
* across the targets it could be bit[0] = 0/1 for UFS2.x/3x
* and vice versa. If the bit[0] value is not same as default
* value used in driver and if its reverted then use flag
* qcom,ufs-dev-revert to identify ufs device.
*/
ufs-dev-types = <2>;
qcom,ufs-dev-revert;
nvmem-cells = <&ufs_dev>, <&boot_config>;
nvmem-cell-names = "ufs_dev", "boot_conf";
status = "ok";
};
&battery_charger {
qcom,thermal-mitigation-step = <500000>;
qcom,wireless-charging-not-supported;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/arm/msm/qcom_dma_heap_dt_constants.h>
&soc {
qcom,dma-heaps {
compatible = "qcom,dma-heaps";
qcom,user_contig {
qcom,dma-heap-name = "qcom,user-contig";
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
memory-region = <&user_contig_mem>;
};
qcom,qseecom {
qcom,dma-heap-name = "qcom,qseecom";
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
memory-region = <&qseecom_mem>;
};
qcom,qseecom_ta {
qcom,dma-heap-name = "qcom,qseecom-ta";
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
memory-region = <&qseecom_ta_mem>;
};
qcom,audio_ml {
qcom,dma-heap-name = "qcom,audio-ml";
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
memory-region = <&audio_cma_mem>;
};
non_secure_display_dma_buf: qcom,display {
qcom,dma-heap-name = "qcom,display";
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
qcom,max-align = <9>;
memory-region = <&non_secure_display_memory>;
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "ravelin-idp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Ravelin IDP";
compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp";
qcom,msm-id = <568 0x10000>, <602 0x10000>;
qcom,board-id = <34 0>;
};

16
qcom/ravelin-idp-wcn3950-amoled-rcm-overlay.dts Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "ravelin-idp-wcn3950-amoled-rcm.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Ravelin WCN3950 IDP + AMOLED + RCM";
compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp";
qcom,msm-id = <568 0x10000>, <602 0x10000>;
qcom,board-id = <34 2>;
};

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qcom/ravelin-idp-wcn3950-amoled-rcm.dts Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "ravelin.dtsi"
#include "ravelin-idp-wcn3950-amoled-rcm.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Ravelin WCN3950 IDP + AMOLED + RCM";
compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp";
qcom,board-id = <34 2>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "ravelin-idp.dtsi"
&soc {
};
&qupv3_se1_i2c {
status = "disabled";
};
&qupv3_se1_spi {
#address-cells = <1>;
#size-cells = <0>;
status = "ok";
qcom,touch-active = "goodix,gt9916S";
goodix-berlin@0 {
reg = <0>;
spi-max-frequency = <1000000>;
goodix,avdd-name = "avdd";
avdd-supply = <&L4E>;
interrupt-parent = <&tlmm>;
interrupts = <91 0x2008>;
goodix,reset-gpio = <&tlmm 90 0x00>;
goodix,irq-gpio = <&tlmm 91 0x2008>;
goodix,irq-flags = <2>;
goodix,panel-max-x = <1080>;
goodix,panel-max-y = <2400>;
goodix,panel-max-w = <255>;
goodix,panel-max-p = <4096>;
goodix,firmware-name = "goodix_firmware_spi.bin";
goodix,config-name = "goodix_cfg_group_spi.bin";
pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", "pmx_ts_release";
pinctrl-0 = <&ts_spi_active>;
pinctrl-1 = <&ts_spi_int_suspend &ts_spi_reset_suspend>;
pinctrl-2 = <&ts_spi_release>;
qcom,touch-environment = "pvm";
};
};

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qcom/ravelin-idp-wcn3988-4gb-overlay.dts Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "ravelin-idp-wcn3988-4gb.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Ravelin IDP 4GB DDR + WCN3988";
compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp";
qcom,msm-id = <568 0x10000>, <602 0x10000>;
qcom,board-id = <34 0x601>;
};

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qcom/ravelin-idp-wcn3988-4gb.dts Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "ravelin-4gb.dtsi"
#include "ravelin-idp-wcn3988-4gb.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Ravelin IDP 4GB DDR + WCN3988";
compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp";
qcom,board-id = <34 0x601>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "ravelin-idp.dtsi"

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "ravelin.dtsi"
#include "ravelin-idp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Ravelin IDP";
compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp";
qcom,board-id = <34 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "ravelin-pmic-overlay.dtsi"
#include "ravelin-pm7250b.dtsi"
#include "ravelin-thermal-overlay.dtsi"
&soc {
};
&qupv3_se8_i2c {
awinic@64 {
reg = <0x64>;
awinic,red {
awinic,name = "red";
awinic,id = <0>;
awinic,imax = <2>;
awinic,led-current = <3>;
awinic,max-brightness = <255>;
awinic,rise-time-ms = <6>;
awinic,hold-time-ms = <0>;
awinic,fall-time-ms = <6>;
awinic,off-time-ms = <4>;
};
awinic,green {
awinic,name = "green";
awinic,id = <1>;
awinic,imax = <2>;
awinic,led-current = <3>;
awinic,max-brightness = <255>;
awinic,rise-time-ms = <6>;
awinic,hold-time-ms = <0>;
awinic,fall-time-ms = <6>;
awinic,off-time-ms = <4>;
};
awinic,blue {
awinic,name = "blue";
awinic,id = <2>;
awinic,imax = <2>;
awinic,led-current = <3>;
awinic,max-brightness = <255>;
awinic,rise-time-ms = <6>;
awinic,hold-time-ms = <0>;
awinic,fall-time-ms = <6>;
awinic,off-time-ms = <4>;
};
};
};
&qupv3_se1_i2c {
#address-cells = <1>;
#size-cells = <0>;
status = "ok";
qcom,i2c-touch-active = "focaltech,fts_ts";
focaltech@38 {
reg = <0x38>;
interrupt-parent = <&tlmm>;
interrupts = <13 0x2008>;
focaltech,reset-gpio = <&tlmm 12 0x00>;
focaltech,irq-gpio = <&tlmm 13 0x2008>;
focaltech,display-coords = <0 0 1080 2408>;
focaltech,max-touch-number = <10>;
focaltech,ic-type = <0x8726081C>;
focaltech,touch-type = "primary";
pinctrl-names = "pmx_ts_active","pmx_ts_suspend","pmx_ts_release";
pinctrl-0 = <&ts_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
pinctrl-2 = <&ts_release>;
focaltech,trusted-touch-mode = "vm_mode";
focaltech,touch-environment = "pvm";
focaltech,trusted-touch-type = "primary";
focaltech,trusted-touch-spi-irq = <566>;
focaltech,trusted-touch-io-bases = <0x984000 0x910000>;
focaltech,trusted-touch-io-sizes = <0x1000 0x4000>;
focaltech,trusted-touch-vm-gpio-list = <&tlmm 10 0 &tlmm 11 0
&tlmm 12 0 &tlmm 13 0x2008>;
};
};
&sdhc_1 {
status = "ok";
vdd-supply = <&L5E>;
qcom,vdd-current-level = <0 570000>;
vdd-io-supply = <&L19B>;
qcom,vdd-io-always-on;
qcom,vdd-io-lpm-sup;
qcom,vdd-io-current-level = <0 325000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_on>;
pinctrl-1 = <&sdc1_off>;
};
&sdhc_2 {
status = "ok";
vdd-supply = <&L24B>;
qcom,vdd-voltage-level = <2960000 2960000>;
qcom,vdd-current-level = <0 800000>;
/*
* min/max voltages are voted on L24B/L28B and L24B/L28B_PBS
* regulators will only be voted for enabling/disabling conditions
* to support FR84471 for chipsets where PMIC doesn't support
* PBS ram sequence to turn OFF regulators automatically on
* multicard tray removal and these new regulator resources are
* exposed by PMIC team as part of this FR.
*/
vdd-en-dis-supply = <&L24B_PBS>;
vdd-io-supply = <&L28B>;
qcom,vdd-io-voltage-level = <1800000 2960000>;
qcom,vdd-io-current-level = <0 22000>;
vdd-io-en-dis-supply = <&L28B_PBS>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
cd-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
};
&ufsphy_mem {
/*
* Here parrot phy is used for ravelin as it
* do not have its own list for module load and
* hence compatible is using parrot.
* We have plan to improve this by making phy binary
* target independent.
*/
compatible = "qcom,ufs-phy-qmp-v4-waipio";
vdda-phy-supply = <&L5B>;
vdda-pll-supply = <&L16B>;
vdda-phy-max-microamp = <88530>;
vdda-pll-max-microamp = <18310>;
status = "ok";
};
&ufshc_mem {
vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
vcc-supply = <&L5E>;
vcc-max-microamp = <1056000>;
vccq-supply = <&L13B>;
vccq-max-microamp = <750000>;
vccq2-supply = <&L19B>;
vccq2-max-microamp = <750000>;
qcom,vddp-ref-clk-supply = <&L13B>;
qcom,vddp-ref-clk-max-microamp = <100>;
/*
* ufs-dev-types and nvmem entries are for ufs device
* identification using nvmem interface. Use number of
* ufs devices supported for ufs-dev-types, and nvmem handle
* added by pmic for sdam register.
*
* Default value taken by driver is bit[0] = 0 for 3.x and
* bit[0] = 1 for 2.x driver code takes this as default case.
*
* But Bit value to identify ufs device is not consistent
* across the targets it could be bit[0] = 0/1 for UFS2.x/3x
* and vice versa. If the bit[0] value is not same as default
* value used in driver and if its reverted then use flag
* qcom,ufs-dev-revert to identify ufs device.
*/
ufs-dev-types = <2>;
qcom,ufs-dev-revert;
nvmem-cells = <&ufs_dev>, <&boot_config>;
nvmem-cell-names = "ufs_dev", "boot_conf";
status = "ok";
};
&battery_charger {
qcom,thermal-mitigation-step = <500000>;
qcom,wireless-charging-not-supported;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&trust_ui_vm_mem {
status = "disabled";
};
&trust_ui_vm_qrtr {
status = "disabled";
};
&trust_ui_vm_vblk0_ring {
status = "disabled";
};
&trust_ui_vm_swiotlb {
status = "disabled";
};
&non_secure_display_dma_buf {
status = "disabled";
};
&non_secure_display_memory {
status = "disabled";
};
&soc {
qcom,guestvm_loader@e0b00000 {
status = "disabled";
};
qrtr-gunyah {
status = "disabled";
};
qcom,virtio_backend@0 {
status = "disabled";
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
/* smp2p information */
qcom,smp2p_interrupt_rdbg_2_out {
compatible = "qcom,smp2p-interrupt-rdbg-2-out";
qcom,smem-states = <&smp2p_rdbg2_out 0>;
qcom,smem-state-names = "rdbg-smp2p-out";
};
qcom,smp2p_interrupt_rdbg_2_in {
compatible = "qcom,smp2p-interrupt-rdbg-2-in";
interrupts-extended = <&smp2p_rdbg2_in 0 0>;
interrupt-names = "rdbg-smp2p-in";
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,sm4450-gcc.h>
#include <dt-bindings/gpio/gpio.h>
&soc {
pcie0: qcom,pcie@1c00000 {
compatible = "qcom,pci-msm";
reg = <0x01c00000 0x3000>,
<0x01c06000 0x2000>,
<0x60000000 0xf1d>,
<0x60000f20 0xa8>,
<0x60001000 0x1000>,
<0x60100000 0x100000>;
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
cell-index = <0>;
linux,pci-domain = <0>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,
<0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>;
interrupt-parent = <&pcie0>;
interrupts = <0 1 2 3 4>;
interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
"int_d";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0xffffffff>;
interrupt-map = <0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
msi-parent = <&pcie0_msi>;
perst-gpio = <&tlmm 32 GPIO_ACTIVE_HIGH>;
wake-gpio = <&tlmm 31 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pcie0_perst_default
&pcie0_clkreq_default
&pcie0_wake_default>;
pinctrl-1 = <&pcie0_perst_default
&pcie0_clkreq_sleep
&pcie0_wake_default>;
gdsc-vdd-supply = <&gcc_pcie_0_gdsc>;
vreg-1p8-supply = <&L16B>;
vreg-0p9-supply = <&L5B>;
vreg-cx-supply = <&VDD_CX_LEVEL>;
vreg-mx-supply = <&VDD_MX_LEVEL>;
qcom,vreg-1p8-voltage-level = <1200000 1200000 15070>;
qcom,vreg-0p9-voltage-level = <880000 880000 46890>;
qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_NOM 0>;
qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_NOM 0>;
qcom,bw-scale = /* Gen1 */
<RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen2 */
RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen3 */
RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
100000000>;
interconnect-names = "icc_path";
interconnects = <&pcie_anoc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
<&gcc GCC_PCIE_0_CLKREF_EN>,
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
<&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
<&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>,
<&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
<&gcc GCC_PCIE_0_PIPE_DIV2_CLK>,
<&gcc GCC_QMIP_PCIE_AHB_CLK>,
<&pcie_0_pipe_clk>;
clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
"pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",
"pcie_phy_refgen_clk",
"pcie_ddrss_sf_tbu_clk",
"pcie_aggre_noc_0_axi_clk", "pcie_cfg_noc_pcie_anoc_ahb_clk",
"pcie_pipe_clk_mux", "pcie_0_pipe_div2_clk",
"pcie_qmip_pcie_ahb_clk", "pcie_pipe_clk_ext_src";
max-clock-frequency-hz = <0>, <0>, <0>, <19200000>, <0>, <0>,
<0>, <0>, <0>, <0>, <0>, <100000000>,
<0>, <0>, <0>, <0>;
resets = <&gcc GCC_PCIE_0_BCR>,
<&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "pcie_0_core_reset",
"pcie_0_phy_reset";
dma-coherent;
qcom,smmu-sid-base = <0x1400>;
iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
<0x100 &apps_smmu 0x1401 0x1>;
qcom,boot-option = <0x1>;
qcom,aux-clk-freq = <20>; /* 19.2 MHz */
qcom,drv-supported;
qcom,drv-l1ss-timeout-us = <5000>;
qcom,l1-2-th-scale = <2>;
qcom,l1-2-th-value = <150>;
qcom,slv-addr-space-size = <0x4000000>;
qcom,ep-latency = <10>;
qcom,num-parf-testbus-sel = <0xb9>;
qcom,config-recovery;
qcom,pcie-phy-ver = <107>;
qcom,phy-status-offset = <0x214>;
qcom,phy-status-bit = <6>;
qcom,phy-power-down-offset = <0x240>;
qcom,phy-sequence = <0x0240 0x03 0x0
0x0094 0x08 0x0
0x0154 0x34 0x0
0x016c 0x08 0x0
0x0058 0x0f 0x0
0x00a4 0x42 0x0
0x0110 0x24 0x0
0x011c 0x03 0x0
0x0118 0xb4 0x0
0x010c 0x02 0x0
0x01bc 0x11 0x0
0x00bc 0x82 0x0
0x00d4 0x03 0x0
0x00d0 0x55 0x0
0x00cc 0x55 0x0
0x00b0 0x1a 0x0
0x00ac 0x0a 0x0
0x00c4 0x68 0x0
0x00e0 0x02 0x0
0x00dc 0xaa 0x0
0x00d8 0xab 0x0
0x00b8 0x34 0x0
0x00b4 0x14 0x0
0x0158 0x01 0x0
0x0074 0x06 0x0
0x007c 0x16 0x0
0x0084 0x36 0x0
0x0078 0x06 0x0
0x0080 0x16 0x0
0x0088 0x36 0x0
0x01b0 0x1e 0x0
0x01ac 0xca 0x0
0x01b8 0x18 0x0
0x01b4 0xa2 0x0
0x0050 0x07 0x0
0x0010 0x01 0x0
0x001c 0x31 0x0
0x0020 0x01 0x0
0x0024 0xde 0x0
0x0028 0x07 0x0
0x0030 0x4c 0x0
0x0034 0x06 0x0
0x0ee4 0x20 0x0
0x0e84 0x75 0x0
0x0e90 0x3f 0x0
0x115c 0x7f 0x0
0x1160 0xff 0x0
0x1164 0xbf 0x0
0x1168 0x3f 0x0
0x116c 0xd8 0x0
0x1170 0xdc 0x0
0x1174 0xdc 0x0
0x1178 0x5c 0x0
0x117c 0x34 0x0
0x1180 0xa6 0x0
0x1190 0x34 0x0
0x1194 0x38 0x0
0x10d8 0x0f 0x0
0x0e3c 0x12 0x0
0x0e40 0x01 0x0
0x10dc 0x00 0x0
0x104c 0x08 0x0
0x1050 0x08 0x0
0x1044 0xf0 0x0
0x11a4 0x38 0x0
0x10cc 0xf0 0x0
0x10f4 0x07 0x0
0x1008 0x09 0x0
0x1014 0x05 0x0
0x0694 0x00 0x0
0x0654 0x00 0x0
0x06a8 0x0f 0x0
0x0048 0x90 0x0
0x0620 0xc1 0x0
0x0388 0x77 0x0
0x0398 0x0b 0x0
0x02dc 0x05 0x0
0x0200 0x00 0x0
0x0244 0x03 0x0>;
qcom,parf-debug-reg = <0x01B0 0x0024 0x0028 0x0224 0x0500
0x04D0 0x04D4 0x03C0 0x0630 0x0230
0x0000>;
qcom,dbi-debug-reg = <0x0104 0x0110 0x0080 0x0204 0x0730
0x0734 0x0738 0x073C>;
qcom,phy-debug-reg = <0x0068 0x0140 0x0144 0x0148 0x014C
0x0150 0x0160 0x0178 0x0ED0 0x0EDC
0x0F34 0x0F38 0x0f3C 0x0F40 0x0F44
0x0F48 0x0F4C 0x0F50 0x0F54 0x0F58
0x11E8 0x0A00 0x0A04 0x0A08 0x0A0C
0x0A10 0x0A14 0x0A18 0x0C20 0x0214
0x0218 0x021C 0x0220 0x0224 0x0228
0x022C 0x0230 0x0234 0x0238 0x023C
0x0600 0x0604 0x1204 0x1210>;
status = "disabled";
pcie0_rp: pcie0_rp {
reg = <0 0 0 0 0>;
};
};
pcie0_msi: qcom,pcie0_msi@0x17210040 {
compatible = "qcom,pci-msi";
msi-controller;
reg = <0x17210040 0x0>;
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/thermal/thermal_qti.h>
#include "pm7250b.dtsi"
&soc {
qcom,pmic_glink {
status = "okay";
};
qcom,pmic_glink_log {
compatible = "qcom,pmic-glink";
qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS";
qcom,battery_debug {
compatible = "qcom,battery-debug";
};
qcom,charger_ulog_glink {
compatible = "qcom,charger-ulog-glink";
};
spmi_glink_debug: qcom,spmi_glink_debug {
compatible = "qcom,spmi-glink-debug";
#address-cells = <1>;
#size-cells = <0>;
depends-on-supply = <&spmi0_bus>;
/* Primary SPMI bus */
spmi@0 {
reg = <0>;
#address-cells = <2>;
#size-cells = <0>;
qcom,pm7250b-debug@8 {
compatible = "qcom,spmi-pmic";
reg = <8 SPMI_USID>;
qcom,can-sleep;
};
};
};
};
};
&glink_edge {
qcom,pmic_glink_rpmsg {
qcom,glink-channels = "PMIC_RTR_ADSP_APPS";
};
qcom,pmic_glink_log_rpmsg {
qcom,glink-channels = "PMIC_LOGS_ADSP_APPS";
qcom,intents = <0x800 5
0xc00 3
0x2000 1>;
};
};
&battery_charger {
status = "okay";
};
&ucsi {
status = "okay";
};
&altmode {
status = "okay";
};
&spmi0_debug_bus {
qcom,pm7250b-debug@8 {
compatible = "qcom,spmi-pmic";
reg = <8 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
qcom,pm7250b-debug@9 {
compatible = "qcom,spmi-pmic";
reg = <9 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
};
&pm7250b_2 {
/* Slave ID - 8 */
reg = <8 SPMI_USID>;
};
&pm7250b_3 {
/* Slave ID - 9 */
reg = <9 SPMI_USID>;
};
&pm7250b_clkdiv {
clocks = <&rpmhcc RPMH_CXO_CLK>;
};
&pm7250b_vadc {
interrupts = <0x8 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
pm7250b_usb_conn_therm {
reg = <ADC5_AMUX_THM3_100K_PU>;
label = "pm7250b_usb_conn_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
pm7250b_charger_skin_therm {
reg = <ADC5_AMUX_THM1_100K_PU>;
label = "pm7250b_charger_skin_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
};
&pm7250b_adc_tm {
interrupts = <0x8 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
io-channels = <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>,
<&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>;
pm7250b_usb_conn_therm {
reg = <ADC5_AMUX_THM3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
pm7250b_charger_skin_therm {
reg = <ADC5_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
};
&thermal_zones {
socd {
cooling-maps {
socd_cpu_6_7 {
trip = <&socd_trip>;
cooling-device = <&cpu_6_7_pause 1 1>;
};
socd_gpu0 {
trip = <&socd_trip>;
cooling-device = <&msm_gpu 2 2>;
};
};
};
pm7250b-ibat-lvl0 {
trips {
ibat-lvl0 {
temperature = <4000>;
};
};
};
pm7250b-ibat-lvl1 {
trips {
ibat-lvl1 {
temperature = <5000>;
};
};
};
pm7250b-bcl-lvl0 {
cooling-maps {
vbat_lte0 {
trip = <&b_bcl_lvl0>;
cooling-device = <&modem_lte_dsc 8 8>;
};
vbat_nr0_scg {
trip = <&b_bcl_lvl0>;
cooling-device = <&modem_nr_scg_dsc 3 3>;
};
vbat_nr0 {
trip = <&b_bcl_lvl0>;
cooling-device = <&modem_nr_dsc 6 6>;
};
vbat_cpu_4 {
trip = <&b_bcl_lvl0>;
cooling-device = <&cpu4_pause 1 1>;
};
vbat_cpu_5 {
trip = <&b_bcl_lvl0>;
cooling-device = <&cpu5_pause 1 1>;
};
vbat_cpu_6 {
trip = <&b_bcl_lvl0>;
cooling-device = <&cpu6_pause 1 1>;
};
vbat_gpu0 {
trip = <&b_bcl_lvl0>;
cooling-device = <&msm_gpu 2 2>;
};
};
};
pm7250b-bcl-lvl1 {
cooling-maps {
vbat_lte1 {
trip = <&b_bcl_lvl1>;
cooling-device = <&modem_lte_dsc 255 255>;
};
vbat_nr1_scg {
trip = <&b_bcl_lvl1>;
cooling-device = <&modem_nr_scg_dsc 255 255>;
};
vbat_nr1 {
trip = <&b_bcl_lvl1>;
cooling-device = <&modem_nr_dsc 255 255>;
};
vbat_cpu_7 {
trip = <&b_bcl_lvl1>;
cooling-device = <&cpu7_pause 1 1>;
};
vbat_gpu1 {
trip = <&b_bcl_lvl1>;
cooling-device = <&msm_gpu 4 4>;
};
};
};
pm7250b-bcl-lvl2 {
cooling-maps {
vbat_gpu2 {
trip = <&b_bcl_lvl2>;
cooling-device = <&msm_gpu 3 THERMAL_NO_LIMIT>;
};
};
};
sys-therm-9 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM3_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sys-therm-7 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM1_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
};
&pm7250b_tz {
interrupts = <0x8 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
};
&pm7250b_bcl {
interrupts = <0x8 0x1d 0x0 IRQ_TYPE_EDGE_RISING>,
<0x8 0x1d 0x1 IRQ_TYPE_EDGE_RISING>,
<0x8 0x1d 0x2 IRQ_TYPE_EDGE_RISING>;
};
&pm7250b_gpios {
display_panel_supply_ctrl {
display_panel_vddio_default: display_panel_vddio_default {
pins = "gpio11";
function = "normal";
input-disable;
output-enable;
bias-disable;
power-source = <0>;
qcom,drive-strength = <2>;
};
display_panel_extvdd_default: display_panel_extvdd_default {
pins = "gpio12";
function = "normal";
input-disable;
output-enable;
bias-disable;
power-source = <0>;
qcom,drive-strength = <2>;
};
};
};
&soc {
display_panel_vddio: display_gpio_regulator@1 {
compatible = "qti-regulator-fixed";
regulator-name = "display_panel_vddio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <233>;
gpio = <&pm7250b_gpios 11 0>;
enable-active-high;
regulator-boot-on;
proxy-supply = <&display_panel_vddio>;
qcom,proxy-consumer-enable;
pinctrl-names = "default";
pinctrl-0 = <&display_panel_vddio_default>;
};
display_panel_extvdd: display_gpio_regulator@2 {
compatible = "qti-regulator-fixed";
regulator-name = "display_panel_extvdd";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-enable-ramp-delay = <233>;
gpio = <&pm7250b_gpios 12 0>;
enable-active-high;
regulator-boot-on;
proxy-supply = <&display_panel_extvdd>;
qcom,proxy-consumer-enable;
pinctrl-names = "default";
pinctrl-0 = <&display_panel_extvdd_default>;
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/thermal/thermal_qti.h>
#include "pmi632.dtsi"
&soc {
qcom,pmic_glink {
status = "okay";
};
qcom,pmic_glink_log {
compatible = "qcom,pmic-glink";
qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS";
qcom,battery_debug {
compatible = "qcom,battery-debug";
};
qcom,charger_ulog_glink {
compatible = "qcom,charger-ulog-glink";
};
spmi_glink_debug: qcom,spmi_glink_debug {
compatible = "qcom,spmi-glink-debug";
#address-cells = <1>;
#size-cells = <0>;
depends-on-supply = <&spmi0_bus>;
/* Primary SPMI bus */
spmi@0 {
reg = <0>;
#address-cells = <2>;
#size-cells = <0>;
qcom,pmi632-debug@2 {
compatible = "qcom,spmi-pmic";
reg = <2 SPMI_USID>;
qcom,can-sleep;
};
};
};
};
};
&glink_edge {
qcom,pmic_glink_rpmsg {
qcom,glink-channels = "PMIC_RTR_ADSP_APPS";
};
qcom,pmic_glink_log_rpmsg {
qcom,glink-channels = "PMIC_LOGS_ADSP_APPS";
qcom,intents = <0x800 5
0xc00 3
0x2000 1>;
};
};
&battery_charger {
status = "okay";
};
&ucsi {
status = "okay";
};
&altmode {
status = "disabled";
};
&spmi0_debug_bus {
qcom,pmi632-debug@2 {
compatible = "qcom,spmi-pmic";
reg = <2 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
qcom,pmi632-debug@3 {
compatible = "qcom,spmi-pmic";
reg = <3 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
};
&pmi632_gpios {
usb_conn_therm {
usb_conn_therm_default: usb_conn_therm_default {
pins = "gpio1";
bias-high-impedance;
};
};
charger_skin_temp {
charger_skin_temp_default: charger_skin_temp_default {
pins = "gpio3";
bias-high-impedance;
};
};
smb_skin_therm {
smb_skin_therm_default: smb_skin_therm_default {
pins = "gpio4";
bias-high-impedance;
};
};
};
&pmi632_vadc {
pinctrl-names = "default";
pinctrl-0 = <&usb_conn_therm_default &charger_skin_temp_default
&smb_skin_therm_default>;
pmi632_usb_conn_therm {
reg = <ADC5_GPIO1_100K_PU>;
label = "pmi632_usb_conn_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
pmi632_charger_skin_temp {
reg = <ADC5_GPIO2_100K_PU>;
label = "pmi632_charger_skin_temp";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
pmi632_smb_skin_therm {
reg = <ADC5_GPIO3_100K_PU>;
label = "pmi632_smb_skin_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
};
&pmi632_adc_tm {
io-channels = <&pmi632_vadc ADC5_GPIO1_100K_PU>,
<&pmi632_vadc ADC5_GPIO2_100K_PU>,
<&pmi632_vadc ADC5_GPIO3_100K_PU>;
pmi632_usb_conn_therm {
reg = <ADC5_GPIO1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
pmi632_charger_skin_temp {
reg = <ADC5_GPIO2_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
pmi632_smb_skin_therm {
reg = <ADC5_GPIO3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
};
&thermal_zones {
socd {
cooling-maps {
socd_cpu_6_7 {
trip = <&socd_trip>;
cooling-device = <&cpu_6_7_pause 1 1>;
};
socd_gpu0 {
trip = <&socd_trip>;
cooling-device = <&msm_gpu 2 2>;
};
};
};
pmi632-bcl-lvl0 {
cooling-maps {
vbat_lte0 {
trip = <&b_bcl_lvl0>;
cooling-device = <&modem_lte_dsc 8 8>;
};
vbat_nr0_scg {
trip = <&b_bcl_lvl0>;
cooling-device = <&modem_nr_scg_dsc 3 3>;
};
vbat_nr0 {
trip = <&b_bcl_lvl0>;
cooling-device = <&modem_nr_dsc 6 6>;
};
vbat_cpu_4 {
trip = <&b_bcl_lvl0>;
cooling-device = <&cpu4_pause 1 1>;
};
vbat_cpu_5 {
trip = <&b_bcl_lvl0>;
cooling-device = <&cpu5_pause 1 1>;
};
vbat_cpu_6 {
trip = <&b_bcl_lvl0>;
cooling-device = <&cpu6_pause 1 1>;
};
vbat_gpu0 {
trip = <&b_bcl_lvl0>;
cooling-device = <&msm_gpu 2 2>;
};
};
};
pmi632-bcl-lvl1 {
cooling-maps {
vbat_lte1 {
trip = <&b_bcl_lvl1>;
cooling-device = <&modem_lte_dsc 255 255>;
};
vbat_nr1_scg {
trip = <&b_bcl_lvl1>;
cooling-device = <&modem_nr_scg_dsc 255 255>;
};
vbat_nr1 {
trip = <&b_bcl_lvl1>;
cooling-device = <&modem_nr_dsc 255 255>;
};
vbat_cpu_7 {
trip = <&b_bcl_lvl1>;
cooling-device = <&cpu7_pause 1 1>;
};
vbat_gpu1 {
trip = <&b_bcl_lvl1>;
cooling-device = <&msm_gpu 4 4>;
};
};
};
pmi632-bcl-lvl2 {
cooling-maps {
vbat_gpu2 {
trip = <&b_bcl_lvl2>;
cooling-device = <&msm_gpu 3 THERMAL_NO_LIMIT>;
};
};
};
sys-therm-9 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmi632_adc_tm ADC5_GPIO1_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sys-therm-7 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmi632_adc_tm ADC5_GPIO2_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sys-therm-8 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmi632_adc_tm ADC5_GPIO3_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
};
&flash_led {
qcom,use-qti-battery-interface;
};
&pmi632_lcdb {
status = "ok";
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/iio/qcom,spmi-adc7-pm6450.h>
#include <dt-bindings/gpio/gpio.h>
#include "pmk8350.dtsi"
#include "pm6450.dtsi"
&soc {
reboot_reason {
compatible = "qcom,reboot-reason";
nvmem-cells = <&restart_reason>;
nvmem-cell-names = "restart_reason";
};
pmic-pon-log {
compatible = "qcom,pmic-pon-log";
nvmem = <&pmk8350_sdam_5>;
nvmem-names = "pon_log";
};
};
&pmk8350 {
/delete-node/ pon_pbs@800;
/delete-node/ pon_hlos@1300;
pon_hlos@1300 {
compatible = "qcom,pm8998-pon";
reg = <0x1300>, <0x800>;
reg-names = "pon_hlos", "pon_pbs";
qcom,log-kpd-event;
pwrkey {
compatible = "qcom,pmk8350-pwrkey";
interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>;
linux,code = <KEY_POWER>;
};
resin {
compatible = "qcom,pmk8350-resin";
interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>;
linux,code = <KEY_VOLUMEDOWN>;
};
};
};
&pmk8350_vadc {
pinctrl-names = "default";
pinctrl-0 = <&quiet_therm_default &wide_rfc_therm_default
&rear_cam_flash_therm_default &pa_therm2_default &pa_therm1_default>;
/delete-node/ pm8350_ref_gnd;
/delete-node/ pm8350_vref_1p25;
/delete-node/ pm8350_die_temp;
/delete-node/ pm8350_vph_pwr;
/delete-node/ pm8350b_ref_gnd;
/delete-node/ pm8350b_vref_1p25;
/delete-node/ pm8350b_die_temp;
/delete-node/ pm8350b_vph_pwr;
/delete-node/ pm8350b_vbat_sns;
/delete-node/ pmr735b_ref_gnd;
/delete-node/ pmr735b_vref_1p25;
/delete-node/ pmr735b_die_temp;
/delete-node/ pmr735a_ref_gnd;
/delete-node/ pmr735a_vref_1p25;
/delete-node/ pmr735a_die_temp;
/* PM6450 Channel nodes */
pm6450_ref_gnd {
reg = <PM6450_ADC7_REF_GND>;
label = "pm6450_ref_gnd";
qcom,pre-scaling = <1 1>;
};
pm6450_vref_1p25 {
reg = <PM6450_ADC7_1P25VREF>;
label = "pm6450_vref_1p25";
qcom,pre-scaling = <1 1>;
};
pm6450_die_temp {
reg = <PM6450_ADC7_DIE_TEMP>;
label = "pm6450_die_temp";
qcom,pre-scaling = <1 1>;
};
pm6450_quiet_therm {
reg = <PM6450_ADC7_AMUX1_GPIO2_100K_PU>;
label = "pm6450_quiet_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
pmk8350_wide_rfc_therm {
reg = <PMK8350_ADC7_AMUX_THM2_100K_PU>;
label = "pmk8350_wide_rfc_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
pm6450_rear_cam_flash_therm {
reg = <PM6450_ADC7_AMUX4_GPIO5_100K_PU>;
label = "pm6450_rear_cam_flash_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
pm6450_pa_therm2 {
reg = <PM6450_ADC7_AMUX3_GPIO4_100K_PU>;
label = "pm6450_pa_therm2";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
pmk8350_pa_therm1 {
reg = <PMK8350_ADC7_AMUX_THM3_100K_PU>;
label = "pmk8350_pa_therm1";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
};
&spmi_bus {
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
pm8010_e: qcom,pm8010@4 {
compatible = "qcom,spmi-pmic";
reg = <4 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8010e_tz: pm8010-e-temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
};
};
&pmk8350_adc_tm {
io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>,
<&pmk8350_vadc PM6450_ADC7_AMUX1_GPIO2_100K_PU>,
<&pmk8350_vadc PMK8350_ADC7_AMUX_THM2_100K_PU>,
<&pmk8350_vadc PM6450_ADC7_AMUX4_GPIO5_100K_PU>,
<&pmk8350_vadc PM6450_ADC7_AMUX3_GPIO4_100K_PU>,
<&pmk8350_vadc PMK8350_ADC7_AMUX_THM3_100K_PU>;
pmk8350_xo_therm {
reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
pm6450_quiet_therm {
reg = <PM6450_ADC7_AMUX1_GPIO2_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
pmk8350_wide_rfc_therm {
reg = <PMK8350_ADC7_AMUX_THM2_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
pm6450_rear_cam_flash_therm {
reg = <PM6450_ADC7_AMUX4_GPIO5_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
pm6450_pa2_therm {
reg = <PM6450_ADC7_AMUX3_GPIO4_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
pmk8350_pa1_therm {
reg = <PMK8350_ADC7_AMUX_THM3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
};
&pmk8350_gpios {
wide_rfc_therm {
wide_rfc_therm_default: wide_rfc_therm_default {
pins = "gpio1";
bias-high-impedance;
};
};
pa_therm1 {
pa_therm1_default: pa_therm1_default {
pins = "gpio2";
bias-high-impedance;
};
};
};
&pmk8350_sdam_23 {
adc_scaling: scaling@bf {
reg = <0xbf 0x1>;
bits = <0 2>;
};
};
&pmk8350_sdam_1 {
ufs_dev: ufs_dev@94 {
reg = <0x94 0x1>;
bits = <0 0>;
};
};
&pm6450_gpios {
quiet_therm {
quiet_therm_default: quiet_therm_default {
pins = "gpio2";
bias-high-impedance;
};
};
rear_cam_flash_therm {
rear_cam_flash_therm_default: rear_cam_flash_therm_default {
pins = "gpio5";
bias-high-impedance;
};
};
pa_therm2 {
pa_therm2_default: pa_therm2_default {
pins = "gpio4";
bias-high-impedance;
};
};
};
&thermal_zones {
pm8010e_tz {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&pm8010e_tz>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "passive";
};
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
sys-therm-6 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM1_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sys-therm-4 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM2_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sys-therm-1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8350_adc_tm PM6450_ADC7_AMUX1_GPIO2_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sys-therm-3 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8350_adc_tm PM6450_ADC7_AMUX4_GPIO5_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sys-therm-11 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8350_adc_tm PM6450_ADC7_AMUX3_GPIO4_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sys-therm-5 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM3_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
};
&tlmm {
key_vol_up_default: key_vol_up_default {
mux {
pins = "gpio53";
function = "gpio";
};
config {
pins = "gpio53";
drive-strength = <2>;
bias-pull-up;
input-enable;
};
};
pm8010m_active: pm8010m-active {
mux {
pins = "gpio29";
function = "gpio";
};
config {
pins = "gpio29";
bias-pull-up;
output-high;
drive-strength = <2>;
};
};
pm8010n_active: pm8010n-active {
mux {
pins = "gpio30";
function = "gpio";
};
config {
pins = "gpio30";
bias-pull-up;
output-high;
drive-strength = <2>;
};
};
};
&soc {
gpio_keys {
compatible = "gpio-keys";
label = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&key_vol_up_default>;
vol_up {
label = "volume_up";
gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
linux,code = <KEY_VOLUMEUP>;
gpio-key,wakeup;
debounce-interval = <15>;
linux,can-disable;
};
};
};
/*
* Each QUP device that's a parent to PMIC must be listed as a critical device
* to GCC
*/
&gcc {
qcom,critical-devices = <&qupv3_se8_i2c>;
};
&qupv3_se8_i2c {
#address-cells = <1>;
#size-cells = <0>;
status = "ok";
pm8010m@8 {
compatible = "qcom,i2c-pmic";
reg = <0x8>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pm8010m_active>;
pm8010-chip@900 {
reg = <0x900>;
PM8010M_EN: qcom,pm8008-chip-en {
regulator-name = "pm8010m-chip-en";
};
};
qcom,revid@100 {
reg = <0x100>;
};
};
pm8010m@9 {
compatible = "qcom,i2c-pmic";
reg = <0x9>;
#address-cells = <1>;
#size-cells = <0>;
qcom,pm8010m-regulator {
#address-cells = <1>;
#size-cells = <0>;
pm8008_en-supply = <&PM8010M_EN>;
vdd_l1_l2-supply = <&S8B>;
L1M: pm8010m_l1: regulator@4000 {
reg = <0x4000>;
regulator-name = "pm8010m_l1";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1200000>;
qcom,min-dropout-voltage = <88000>;
qcom,hpm-min-load = <30000>;
};
L2M: pm8010m_l2: regulator@4100 {
reg = <0x4100>;
regulator-name = "pm8010m_l2";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1150000>;
qcom,min-dropout-voltage = <80000>;
qcom,hpm-min-load = <30000>;
};
L3M: pm8010m_l3: regulator@4200 {
reg = <0x4200>;
regulator-name = "pm8010m_l3";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3000000>;
qcom,hpm-min-load = <0>;
};
L4M: pm8010m_l4: regulator@4300 {
reg = <0x4300>;
regulator-name = "pm8010m_l4";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2900000>;
qcom,hpm-min-load = <0>;
};
L6M: pm8010m_l6: regulator@4500 {
reg = <0x4500>;
regulator-name = "pm8010m_l6";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3000000>;
qcom,hpm-min-load = <0>;
};
L7M: pm8010m_l7: regulator@4600 {
reg = <0x4600>;
regulator-name = "pm8010m_l7";
regulator-min-microvolt = <2650000>;
regulator-max-microvolt = <2950000>;
qcom,hpm-min-load = <0>;
};
};
};
pm8010n@c {
compatible = "qcom,i2c-pmic";
reg = <0xc>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pm8010n_active>;
pm8010-chip@900 {
reg = <0x900>;
PM8010N_EN: qcom,pm8008-chip-en {
regulator-name = "pm8010n-chip-en";
};
};
qcom,revid@100 {
reg = <0x100>;
};
};
pm8010n@d {
compatible = "qcom,i2c-pmic";
reg = <0xd>;
#address-cells = <1>;
#size-cells = <0>;
qcom,pm8010n-regulator {
#address-cells = <1>;
#size-cells = <0>;
pm8008_en-supply = <&PM8010N_EN>;
vdd_l1_l2-supply = <&S8B>;
vdd_l3_l4-supply = <&S9B>;
L1N: pm8010n_l1: regulator@4000 {
reg = <0x4000>;
regulator-name = "pm8010n_l1";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1150000>;
qcom,min-dropout-voltage = <72000>;
qcom,hpm-min-load = <30000>;
};
L3N: pm8010n_l3: regulator@4200 {
reg = <0x4200>;
regulator-name = "pm8010n_l3";
regulator-min-microvolt = <1736000>;
regulator-max-microvolt = <3312000>;
qcom,hpm-min-load = <0>;
qcom,min-dropout-voltage = <120000>;
};
L4N: pm8010n_l4: regulator@4300 {
reg = <0x4300>;
regulator-name = "pm8010N_l4";
regulator-min-microvolt = <1704000>;
regulator-max-microvolt = <1900000>;
qcom,hpm-min-load = <0>;
qcom,min-dropout-voltage = <152000>;
};
L6N: pm8010n_l6: regulator@4500 {
reg = <0x4500>;
regulator-name = "pm8010n_l6";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3000000>;
qcom,hpm-min-load = <0>;
};
};
};
};
&pm6450_pwm_1 {
status = "ok";
};
&pm6450_gpios {
lcd_backlight_ctrl {
lcd_backlight_pwm_default: lcd_backlight_pwm_default {
pins = "gpio7";
function = "func1";
input-disable;
output-enable;
bias-disable;
power-source = <1>; /* 1.8V */
qcom,drive-strength = <2>;
};
lcd_backlight_en_default: lcd_backlight_en_default {
pins = "gpio6";
function = "normal";
input-disable;
output-enable;
bias-disable;
power-source = <0>;
qcom,drive-strength = <2>;
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
wil6210: qcom,wil6210 {
qcom,pcie-parent = <&pcie0>;
qcom,wigig-en = <&tlmm 91 0>;
pinctrl-names = "default";
pinctrl-0 = <&wil6210_refclk_en_pin>;
qcom,11ad-bus-bw,name = "wil6210";
qcom,11ad-bus-bw,num-cases = <3>;
qcom,11ad-bus-bw,num-paths = <1>;
qcom,11ad-bus-bw,vectors-KBps = <100 512 0 0>,
<100 512 600000 800000>,
<100 512 1300000 1300000>;
qcom,use-ext-supply;
vdd-s1c-supply = <&S9B>;
qcom,keep-radio-on-during-sleep;
qcom,use-ap-power-save;
status = "disabled";
};
};
&pcie0_rp {
#address-cells = <5>;
#size-cells = <0>;
wil6210_pci: wil6210_pci {
reg = <0 0 0 0 0>;
qcom,iommu-group = <&wil6210_pci_iommu_group>;
#address-cells = <1>;
#size-cells = <1>;
wil6210_pci_iommu_group: wil6210_pci_iommu_group {
reg = <0 0>;
qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
qcom,iommu-dma = "fastmap";
qcom,iommu-pagetable = "coherent";
};
};
};
&tlmm {
talyn_pins {
wil6210_refclk_en_pin: wil6210_refclk_en_pin {
mux {
pins = "gpio83";
function = "gpio";
};
config {
pins = "gpio83";
drive-strength = <2>;
bias-pull-down;
};
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "ravelin-qrd-4gb.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Ravelin QRD 4GB DDR";
compatible = "qcom,ravelin-qrd", "qcom,ravelin", "qcom,qrd";
qcom,msm-id = <568 0x10000>, <602 0x10000>;
qcom,board-id = <0x1000B 0x600>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "ravelin-4gb.dtsi"
#include "ravelin-qrd-4gb.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Ravelin QRD 4GB DDR";
compatible = "qcom,ravelin-qrd", "qcom,ravelin", "qcom,qrd";
qcom,board-id = <0x1000B 0x600>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "ravelin-qrd.dtsi"

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "ravelin-qrd.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Ravelin QRD";
compatible = "qcom,ravelin-qrd", "qcom,ravelin", "qcom,qrd";
qcom,msm-id = <568 0x10000>, <602 0x10000>, <581 0x10000>, <582 0x10000>;
qcom,board-id = <0x1000B 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "ravelin.dtsi"
#include "ravelin-qrd.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Ravelin QRD";
compatible = "qcom,ravelin-qrd", "qcom,ravelin", "qcom,qrd";
qcom,board-id = <0x1000B 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "ravelin-pmic-overlay.dtsi"
#include "ravelin-pmi632.dtsi"
#include "ravelin-thermal-overlay.dtsi"
&soc {
};
&qupv3_se1_i2c {
#address-cells = <1>;
#size-cells = <0>;
status = "ok";
qcom,i2c-touch-active = "focaltech,fts_ts";
focaltech@38 {
status = "ok";
reg = <0x38>;
interrupt-parent = <&tlmm>;
interrupts = <13 0x2008>;
focaltech,reset-gpio = <&tlmm 12 0x00>;
focaltech,irq-gpio = <&tlmm 13 0x2008>;
focaltech,display-coords = <0 0 1080 2408>;
focaltech,max-touch-number = <10>;
focaltech,ic-type = <0x8726081C>;
focaltech,touch-type = "primary";
focaltech,touch-environment = "pvm";
pinctrl-names = "pmx_ts_active","pmx_ts_suspend","pmx_ts_release";
pinctrl-0 = <&ts_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
pinctrl-2 = <&ts_release>;
};
};
&sdhc_1 {
status = "ok";
vdd-supply = <&L5E>;
qcom,vdd-current-level = <0 570000>;
vdd-io-supply = <&L19B>;
qcom,vdd-io-always-on;
qcom,vdd-io-lpm-sup;
qcom,vdd-io-current-level = <0 325000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_on>;
pinctrl-1 = <&sdc1_off>;
};
&sdhc_2 {
status = "ok";
vdd-supply = <&L24B>;
qcom,vdd-voltage-level = <2960000 2960000>;
qcom,vdd-current-level = <0 800000>;
/*
* min/max voltages are voted on L24B/L28B and L24B/L28B_PBS
* regulators will only be voted for enabling/disabling conditions
* to support FR84471 for chipsets where PMIC doesn't support
* PBS ram sequence to turn OFF regulators automatically on
* multicard tray removal and these new regulator resources are
* exposed by PMIC team as part of this FR.
*/
vdd-en-dis-supply = <&L24B_PBS>;
vdd-io-supply = <&L28B>;
qcom,vdd-io-voltage-level = <1800000 2960000>;
qcom,vdd-io-current-level = <0 22000>;
vdd-io-en-dis-supply = <&L28B_PBS>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
cd-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
};
&ufsphy_mem {
/*
* Here parrot phy is used for ravelin as it
* do not have its own list for module load and
* hence compatible is using parrot.
* We have plan to improve this by making phy binary
* target independent.
*/
compatible = "qcom,ufs-phy-qmp-v4-waipio";
vdda-phy-supply = <&L5B>;
vdda-pll-supply = <&L16B>;
vdda-phy-max-microamp = <88530>;
vdda-pll-max-microamp = <18310>;
status = "ok";
};
&ufshc_mem {
vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
vcc-supply = <&L5E>;
vcc-max-microamp = <1056000>;
vccq-supply = <&L13B>;
vccq-max-microamp = <750000>;
vccq2-supply = <&L19B>;
vccq2-max-microamp = <750000>;
qcom,vddp-ref-clk-supply = <&L13B>;
qcom,vddp-ref-clk-max-microamp = <100>;
/*
* ufs-dev-types and nvmem entries are for ufs device
* identification using nvmem interface. Use number of
* ufs devices supported for ufs-dev-types, and nvmem handle
* added by pmic for sdam register.
*
* Default value taken by driver is bit[0] = 0 for 3.x and
* bit[0] = 1 for 2.x driver code takes this as default case.
*
* But Bit value to identify ufs device is not consistent
* across the targets it could be bit[0] = 0/1 for UFS2.x/3x
* and vice versa. If the bit[0] value is not same as default
* value used in driver and if its reverted then use flag
* qcom,ufs-dev-revert to identify ufs device.
*/
ufs-dev-types = <2>;
qcom,ufs-dev-revert;
nvmem-cells = <&ufs_dev>, <&boot_config>;
nvmem-cell-names = "ufs_dev", "boot_conf";
status = "ok";
};
&usb0 {
dwc3@a600000 {
usb-phy = <&usb2_phy0>, <&usb_nop_phy>;
maximum-speed = "high-speed";
};
};
&usb_qmp_dp_phy {
status = "disabled";
};
&usb2_phy0 {
qcom,param-override-seq =
<0x86 0x6c>;
};
&battery_charger {
qcom,thermal-mitigation-step = <500000>;
qcom,wireless-charging-not-supported;
qcom,thermal-mitigation = <11500000 11000000 10500000 10000000 9500000
9000000 8500000 8000000 7500000 7000000 6500000
6000000 5500000 5000000 4500000 4000000 3500000
3000000 2500000 2000000 1500000 1000000 500000>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
/* QUPv3 SE Instances
* Qup0 0: SE 0
* Qup0 1: SE 1
* Qup0 2: SE 2
* Qup0 3: SE 3
* Qup0 4: SE 4
* Qup1 0: SE 5
* Qup1 1: SE 6
* Qup1 2: SE 7
* Qup1 3: SE 8
* Qup1 4: SE 9
*/
/* GPI Instance */
gpi_dma0: qcom,gpi-dma@900000 {
compatible = "qcom,gpi-dma";
#dma-cells = <5>;
reg = <0x900000 0x60000>;
reg-names = "gpi-top";
iommus = <&apps_smmu 0x176 0x0>;
qcom,max-num-gpii = <12>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
qcom,static-gpii-mask = <0x1>;
qcom,gpii-mask = <0x3e>;
qcom,ev-factor = <2>;
qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
dma-coherent;
qcom,gpi-ee-offset = <0x10000>;
status = "ok";
};
/* QUPv3_0 wrapper instance */
qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x9c0000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
iommus = <&apps_smmu 0x163 0x0>;
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
dma-coherent;
status = "ok";
/* HS UART Instance */
qupv3_se2_4uart: qcom,qup_uart@988000 {
compatible = "qcom,msm-geni-serial-hs";
reg = <0x988000 0x4000>;
reg-names = "se_phys";
interrupts-extended = <&intc GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
<&tlmm 17 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "active", "sleep", "shutdown";
pinctrl-0 = <&qupv3_se2_default_cts>, <&qupv3_se2_default_rts>,
<&qupv3_se2_default_tx>, <&qupv3_se2_default_rx>;
pinctrl-1 = <&qupv3_se2_cts>, <&qupv3_se2_rts>,
<&qupv3_se2_tx>, <&qupv3_se2_rx>;
pinctrl-2 = <&qupv3_se2_cts>, <&qupv3_se2_rts>,
<&qupv3_se2_tx>, <&qupv3_se2_default_rx>;
pinctrl-3 = <&qupv3_se2_default_cts>, <&qupv3_se2_default_rts>,
<&qupv3_se2_default_tx>, <&qupv3_se2_default_rx>;
qcom,wakeup-byte = <0xFD>;
status = "disabled";
};
/* HST Debug UART Instance */
qupv3_se0_2uart: qcom,qup_uart@980000 {
compatible = "qcom,geni-debug-uart";
reg = <0x980000 0x4000>;
reg-names = "se_phys";
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se0_2uart_tx_active>, <&qupv3_se0_2uart_rx_active>;
pinctrl-1 = <&qupv3_se0_2uart_sleep>;
status = "disabled";
};
qupv3_se0_i2c: i2c@980000 {
compatible = "qcom,i2c-geni";
reg = <0x980000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>;
pinctrl-1 = <&qupv3_se0_i2c_sleep>;
dmas = <&gpi_dma0 0 0 3 64 0>,
<&gpi_dma0 1 0 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se1_i2c: i2c@984000 {
compatible = "qcom,i2c-geni";
reg = <0x984000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se1_i2c_sda_active>, <&qupv3_se1_i2c_scl_active>;
pinctrl-1 = <&qupv3_se1_i2c_sleep>;
dmas = <&gpi_dma0 0 1 3 64 2>,
<&gpi_dma0 1 1 3 64 2>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se1_spi: spi@984000 {
compatible = "qcom,spi-geni";
reg = <0x984000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se1_spi_mosi_active>, <&qupv3_se1_spi_miso_active>,
<&qupv3_se1_spi_clk_active>, <&qupv3_se1_spi_cs_active>;
pinctrl-1 = <&qupv3_se1_spi_sleep>;
dmas = <&gpi_dma0 0 1 1 64 2>,
<&gpi_dma0 1 1 1 64 2>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se3_i2c: i2c@98c000 {
compatible = "qcom,i2c-geni";
reg = <0x98c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se3_i2c_sda_active>, <&qupv3_se3_i2c_scl_active>;
pinctrl-1 = <&qupv3_se3_i2c_sleep>;
dmas = <&gpi_dma0 0 3 3 64 0>,
<&gpi_dma0 1 3 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se3_spi: spi@98c000 {
compatible = "qcom,spi-geni";
reg = <0x98c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se3_spi_mosi_active>, <&qupv3_se3_spi_miso_active>,
<&qupv3_se3_spi_clk_active>, <&qupv3_se3_spi_cs_active>;
pinctrl-1 = <&qupv3_se3_spi_sleep>;
dmas = <&gpi_dma0 0 3 1 64 0>,
<&gpi_dma0 1 3 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se4_i2c: i2c@990000 {
compatible = "qcom,i2c-geni";
reg = <0x990000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se4_i2c_sda_active>, <&qupv3_se4_i2c_scl_active>;
pinctrl-1 = <&qupv3_se4_i2c_sleep>;
dmas = <&gpi_dma0 0 4 3 64 0>,
<&gpi_dma0 1 4 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se4_spi: spi@990000 {
compatible = "qcom,spi-geni";
reg = <0x990000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se4_spi_mosi_active>, <&qupv3_se4_spi_miso_active>,
<&qupv3_se4_spi_clk_active>, <&qupv3_se4_spi_cs_active>;
pinctrl-1 = <&qupv3_se4_spi_sleep>;
dmas = <&gpi_dma0 0 4 1 64 0>,
<&gpi_dma0 1 4 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
};
/* GPI Instance */
gpi_dma1: qcom,gpi-dma@a00000 {
compatible = "qcom,gpi-dma";
#dma-cells = <5>;
reg = <0xa00000 0x60000>;
reg-names = "gpi-top";
iommus = <&apps_smmu 0x416 0x0>;
qcom,max-num-gpii = <12>;
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
qcom,gpii-mask = <0x3f>;
qcom,ev-factor = <2>;
qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
dma-coherent;
qcom,gpi-ee-offset = <0x10000>;
status = "ok";
};
/* QUPv3_1 wrapper instance */
qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0xac0000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
iommus = <&apps_smmu 0x403 0x0>;
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
dma-coherent;
ranges;
status = "ok";
/* PORed Debug UART Instance */
qupv3_se7_2uart: qcom,qup_uart@a88000 {
compatible = "qcom,geni-debug-uart";
reg = <0xa88000 0x4000>;
reg-names = "se_phys";
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se7_2uart_tx_active>, <&qupv3_se7_2uart_rx_active>;
pinctrl-1 = <&qupv3_se7_2uart_sleep>;
status = "disabled";
};
qupv3_se5_i2c: i2c@a80000 {
compatible = "qcom,i2c-geni";
reg = <0xa80000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se5_i2c_sda_active>, <&qupv3_se5_i2c_scl_active>;
pinctrl-1 = <&qupv3_se5_i2c_sleep>;
dmas = <&gpi_dma1 0 0 3 64 0>,
<&gpi_dma1 1 0 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se5_spi: spi@a80000 {
compatible = "qcom,spi-geni";
reg = <0xa80000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se5_spi_mosi_active>, <&qupv3_se5_spi_miso_active>,
<&qupv3_se5_spi_clk_active>, <&qupv3_se5_spi_cs_active>;
pinctrl-1 = <&qupv3_se5_spi_sleep>;
dmas = <&gpi_dma1 0 0 1 64 0>,
<&gpi_dma1 1 0 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se6_i2c: i2c@a84000 {
compatible = "qcom,i2c-geni";
reg = <0xa84000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se6_i2c_sda_active>, <&qupv3_se6_i2c_scl_active>;
pinctrl-1 = <&qupv3_se6_i2c_sleep>;
dmas = <&gpi_dma1 0 1 3 64 0>,
<&gpi_dma1 1 1 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se6_spi: spi@a84000 {
compatible = "qcom,spi-geni";
reg = <0xa84000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se6_spi_mosi_active>, <&qupv3_se6_spi_miso_active>,
<&qupv3_se6_spi_clk_active>, <&qupv3_se6_spi_cs_active>;
pinctrl-1 = <&qupv3_se6_spi_sleep>;
dmas = <&gpi_dma1 0 1 1 64 0>,
<&gpi_dma1 1 1 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se8_i2c: i2c@a8c000 {
compatible = "qcom,i2c-geni";
reg = <0xa8c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se8_i2c_sda_active>, <&qupv3_se8_i2c_scl_active>;
pinctrl-1 = <&qupv3_se8_i2c_sleep>;
dmas = <&gpi_dma1 0 3 3 64 0>,
<&gpi_dma1 1 3 3 64 0>;
dma-names = "tx", "rx";
qcom,shared;
status = "disabled";
};
qupv3_se8_spi: spi@a8c000 {
compatible = "qcom,spi-geni";
reg = <0xa8c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se8_spi_mosi_active>, <&qupv3_se8_spi_miso_active>,
<&qupv3_se8_spi_clk_active>, <&qupv3_se8_spi_cs_active>;
pinctrl-1 = <&qupv3_se8_spi_sleep>;
dmas = <&gpi_dma1 0 3 1 64 0>,
<&gpi_dma1 1 3 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se9_i2c: i2c@a90000 {
compatible = "qcom,i2c-geni";
reg = <0xa90000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se9_i2c_sda_active>, <&qupv3_se9_i2c_scl_active>;
pinctrl-1 = <&qupv3_se9_i2c_sleep>;
dmas = <&gpi_dma1 0 4 3 64 0>,
<&gpi_dma1 1 4 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se9_spi: spi@a90000 {
compatible = "qcom,spi-geni";
reg = <0xa90000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se9_spi_mosi_active>, <&qupv3_se9_spi_miso_active>,
<&qupv3_se9_spi_clk_active>, <&qupv3_se9_spi_cs_active>;
pinctrl-1 = <&qupv3_se9_spi_sleep>;
dmas = <&gpi_dma1 0 4 1 64 0>,
<&gpi_dma1 1 4 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
};
};

814
qcom/ravelin-regulators.dtsi Normal file
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@@ -0,0 +1,814 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
&apps_rsc_drv2 {
rpmh-regulator-msslvl {
compatible = "qcom,rpmh-arc-regulator";
qcom,resource-name = "mss.lvl";
VDD_MODEM_LEVEL:
S1B_LEVEL:
pm6450_s1_level: regulator-pm6450-s1-level {
regulator-name = "pm6450_s1_level";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
qcom,init-voltage-level =
<RPMH_REGULATOR_LEVEL_RETENTION>;
};
};
rpmh-regulator-cxlvl {
compatible = "qcom,rpmh-arc-regulator";
qcom,resource-name = "cx.lvl";
proxy-supply = <&VDD_CX_LEVEL>;
VDD_CX_LEVEL:
S5B_LEVEL:
pm6450_s5_level: regulator-pm6450-s5-level {
regulator-name = "pm6450_s5_level";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
qcom,init-voltage-level =
<RPMH_REGULATOR_LEVEL_TURBO>;
qcom,proxy-consumer-enable;
qcom,proxy-consumer-voltage =
<RPMH_REGULATOR_LEVEL_TURBO
RPMH_REGULATOR_LEVEL_MAX>;
};
VDD_CX_LEVEL_AO:
S5B_LEVEL_AO:
pm6450_s5_level_ao: regulator-pm6450-s5-level-ao {
regulator-name = "pm6450_s5_level_ao";
qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
qcom,init-voltage-level =
<RPMH_REGULATOR_LEVEL_RETENTION>;
};
};
rpmh-regulator-ebilvl {
compatible = "qcom,rpmh-arc-regulator";
qcom,resource-name = "ebi.lvl";
VDD_EBI_LEVEL:
S6B_LEVEL:
pm6450_s6_level: regulator-pm6450-s6-level {
regulator-name = "pm6450_s6_level";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
qcom,init-voltage-level =
<RPMH_REGULATOR_LEVEL_RETENTION>;
};
};
rpmh-regulator-smpb7 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "smpb7";
S7B:
pm6450_s7: regulator-pm6450-s7 {
regulator-name = "pm6450_s7";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1010000>;
regulator-max-microvolt = <1170000>;
qcom,init-voltage = <1120000>;
};
};
rpmh-regulator-smpb8 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "smpb8";
S8B:
pm6450_s8: regulator-pm6450-s8 {
regulator-name = "pm6450_s8";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <382000>;
regulator-max-microvolt = <1744000>;
qcom,init-voltage = <1352000>;
};
};
rpmh-regulator-smpb9 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "smpb9";
S9B:
pm6450_s9: regulator-pm6450-s9 {
regulator-name = "pm6450_s9";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1856000>;
regulator-max-microvolt = <2040000>;
qcom,init-voltage = <1872000>;
};
};
rpmh-regulator-ldob1 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob1";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L1B:
pm6450_l1: regulator-pm6450-l1 {
regulator-name = "pm6450_l1";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <312000>;
regulator-max-microvolt = <650000>;
qcom,init-voltage = <504000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-lcxlvl {
compatible = "qcom,rpmh-arc-regulator";
qcom,resource-name = "lcx.lvl";
VDD_LPI_CX_LEVEL:
L2B_LEVEL:
pm6450_l2_level: regulator-pm6450-l2-level {
regulator-name = "pm6450_l2_level";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
qcom,init-voltage-level =
<RPMH_REGULATOR_LEVEL_RETENTION>;
};
};
rpmh-regulator-ldob3 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob3";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L3B:
pm6450_l3: regulator-pm6450-l3 {
regulator-name = "pm6450_l3";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <870000>;
regulator-max-microvolt = <970000>;
qcom,init-voltage = <904000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob4 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob4";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L4B:
pm6450_l4: regulator-pm6450-l4 {
regulator-name = "pm6450_l4";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <530000>;
regulator-max-microvolt = <860000>;
qcom,init-voltage = <808000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob5 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob5";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L5B:
pm6450_l5: regulator-pm6450-l5 {
regulator-name = "pm6450_l4";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <312000>;
regulator-max-microvolt = <1052000>;
qcom,init-voltage = <880000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob6 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob6";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L6B:
pm6450_l6: regulator-pm6450-l6 {
regulator-name = "pm6450_l6";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <751000>;
regulator-max-microvolt = <824000>;
qcom,init-voltage = <824000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob7 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob7";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L7B:
pm6450_l7: regulator-pm6450-l7 {
regulator-name = "pm6450_l7";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <830000>;
regulator-max-microvolt = <920000>;
qcom,init-voltage = <912000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-lmxlvl {
compatible = "qcom,rpmh-arc-regulator";
qcom,resource-name = "lmx.lvl";
VDD_LPI_MX_LEVEL:
L8B_LEVEL:
pm6450_l8_level: regulator-pm6450-l8-level {
regulator-name = "pm6450_l8_level";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
qcom,init-voltage-level =
<RPMH_REGULATOR_LEVEL_RETENTION>;
};
};
rpmh-regulator-ldob9 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob9";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L9B:
pm6450_l9: regulator-pm6450-l9 {
regulator-name = "pm6450_l9";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <504000>;
regulator-max-microvolt = <824000>;
qcom,init-voltage = <752000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob10 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob10";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L10B:
pm6450_l10: regulator-pm6450-l10 {
regulator-name = "pm6450_l10";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <824000>;
regulator-max-microvolt = <901000>;
qcom,init-voltage = <824000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob11 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob11";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L11B:
pm6450_l11: regulator-pm6450-l11 {
regulator-name = "pm6450_l11";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <312000>;
regulator-max-microvolt = <752000>;
qcom,init-voltage = <348000>;
};
};
rpmh-regulator-ldob12 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob12";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L12B:
pm6450_l12: regulator-pm6450-l12 {
regulator-name = "pm6450_l12";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1080000>;
regulator-max-microvolt = <1304000>;
qcom,init-voltage = <1080000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob13 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob13";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L13B:
pm6450_l13: regulator-pm6450-l13 {
regulator-name = "pm6450_l13";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1080000>;
regulator-max-microvolt = <1304000>;
qcom,init-voltage = <1200000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob14 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob14";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L14B:
pm6450_l14: regulator-pm6450-l14 {
regulator-name = "pm6450_l14";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1245000>;
regulator-max-microvolt = <1304000>;
qcom,init-voltage = <1150000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob16 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob16";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L16B:
pm6450_l16: regulator-pm6450-l16 {
regulator-name = "pm6450_l16";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <312000>;
regulator-max-microvolt = <1260000>;
qcom,init-voltage = <1200000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob17 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob17";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L17B:
pm6450_l17: regulator-pm6450-l17 {
regulator-name = "pm6450_l17";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
qcom,init-voltage = <1200000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob18 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob18";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L18B:
pm6450_l18: regulator-pm6450-l18 {
regulator-name = "pm6450_l18";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1504000>;
regulator-max-microvolt = <2000000>;
qcom,init-voltage = <1504000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob19 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob19";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L19B:
pm6450_l19: regulator-pm6450-l19 {
regulator-name = "pm6450_l19";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <1950000>;
qcom,init-voltage = <1800000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob20 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob20";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L20B:
pm6450_l20: regulator-pm6450-l20 {
regulator-name = "pm6450_l20";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <1900000>;
qcom,init-voltage = <1700000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob21 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob21";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L21B:
pm6450_l21: regulator-pm6450-l21 {
regulator-name = "pm6450_l21";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1504000>;
regulator-max-microvolt = <2000000>;
qcom,init-voltage = <1800000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob22 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob22";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L22B:
pm6450_l22: regulator-pm6450-l22 {
regulator-name = "pm6450_l22";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1504000>;
regulator-max-microvolt = <2000000>;
qcom,init-voltage = <1800000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob23 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob23";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L23B:
pm6450_l23: regulator-pm6450-l23 {
regulator-name = "pm6450_l23";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
qcom,init-voltage = <1800000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob24 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob24";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L24B:
pm6450_l24: regulator-pm6450-l24 {
regulator-name = "pm6450_l24";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3544000>;
qcom,init-voltage = <2700000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob25 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob25";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L25B:
pm6450_l25: regulator-pm6450-l25 {
regulator-name = "pm6450_l25";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3544000>;
qcom,init-voltage = <3072000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob26 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob26";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L26B:
pm6450_l26: regulator-pm6450-l26 {
regulator-name = "pm6450_l26";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3300000>;
qcom,init-voltage = <1620000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob27 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob27";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L27B:
pm6450_l27: regulator-pm6450-l27 {
regulator-name = "pm6450_l27";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3300000>;
qcom,init-voltage = <1620000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob28 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob28";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L28B:
pm6450_l28: regulator-pm6450-l28 {
regulator-name = "pm6450_l28";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3300000>;
qcom,init-voltage = <2700000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldoe1 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldoe1";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L1E:
pm8010l_l1: regulator-pm8010-l1 {
regulator-name = "pm8010_l1";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <530000>;
regulator-max-microvolt = <864000>;
qcom,init-voltage = <530000>;
};
};
rpmh-regulator-ldoe3 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldoe3";
qcom,regulator-type = "pmic5-ldo";
/* mode voting is not allowed */
L3E:
pm8010l_l3: regulator-pm8010-l3 {
regulator-name = "pm8010_l3";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3300000>;
qcom,init-voltage = <2700000>;
};
};
rpmh-regulator-ldoe4 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldoe4";
qcom,regulator-type = "pmic5-ldo";
/* mode voting is not allowed */
L4E:
pm8010_l4: regulator-pm8010-l4 {
regulator-name = "pm8010_l4";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <2600000>;
regulator-max-microvolt = <3312000>;
qcom,init-voltage = <2700000>;
};
};
rpmh-regulator-ldoe5 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldoe5";
qcom,regulator-type = "pmic5-ldo";
/* mode voting is not allowed */
L5E:
pm8010_l5: regulator-pm8010-l5 {
regulator-name = "pm8010_l5";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
/*
* Remove min/max voltages for this regulator as initial
* voltage of L5E is set to be 2.4v/2.96v during PON
* depending upon the UFS mode. UFS is the only client
* on this and this regulator will only be voted
* for enabling/disabling conditions.
*/
};
};
rpmh-regulator-ldoe6 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldoe6";
qcom,regulator-type = "pmic5-ldo";
/* mode voting is not allowed */
L6E:
pm8010_l6: regulator-pm8010-l6 {
regulator-name = "pm8010_l6";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3312000>;
qcom,init-voltage = <3000000>;
};
};
rpmh-regulator-ldoe7 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldoe7";
qcom,regulator-type = "pmic5-ldo";
/* mode voting is not allowed */
L7E:
pm8010_l7: regulator-pm8010-l7 {
regulator-name = "pm8010_l7";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <3544000>;
qcom,init-voltage = <3000000>;
};
};
rpmh-regulator-mxlvl {
compatible = "qcom,rpmh-arc-regulator";
qcom,resource-name = "mx.lvl";
proxy-supply = <&VDD_MX_LEVEL>;
VDD_MX_LEVEL:
S1G_LEVEL:
pmg1110_s1_level: regulator-pmg1110-s1-level {
regulator-name = "pmg1110_s1_level";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
qcom,init-voltage-level =
<RPMH_REGULATOR_LEVEL_TURBO>;
qcom,proxy-consumer-enable;
qcom,proxy-consumer-voltage =
<RPMH_REGULATOR_LEVEL_TURBO
RPMH_REGULATOR_LEVEL_MAX>;
};
};
rpmh-regulator-sf1-vreg-enable {
compatible = "qcom,rpmh-xob-regulator";
qcom,resource-name = "gpioi7";
status = "disabled";
sf1_vreg_enable: regulator-sf1-vreg-enable {
regulator-name = "sf1_vreg_enable";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
};
};
rpmh-regulator-sf1-vreg-mode {
compatible = "qcom,rpmh-xob-regulator";
qcom,resource-name = "gpioi10";
status = "disabled";
sf1_vreg_mode: regulator-sf1-vreg-mode {
regulator-name = "sf1_vreg_mode";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
};
};
rpmh-regulator-vrmsd {
compatible = "qcom,rpmh-pbs-regulator";
qcom,resource-name = "vrm.sd";
L24B_PBS:
pm6450_l24_pbs: regulator-pm6450-l24-pbs {
regulator-name = "pm6450_l24_pbs";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
/*
* min/max voltages are voted on L24B and this regulator will
* only be voted for enabling/disabling conditions.
*/
};
};
rpmh-regulator-vrmpx2 {
compatible = "qcom,rpmh-pbs-regulator";
qcom,resource-name = "vrm.px2";
L28B_PBS:
pm6450_l28_pbs: regulator-pm6450-l28-pbs {
regulator-name = "pm6450_l28_pbs";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
/*
* min/max voltages are voted on L28B and this regulator will
* only be voted for enabling/disabling conditions.
*/
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&reserved_memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
hyp_mem: hyp_region@80000000 {
no-map;
reg = <0x0 0x80000000 0x0 0x600000>;
};
xbl_dtlog_mem: xbl_dtlog_region@80600000 {
no-map;
reg = <0x0 0x80600000 0x0 0x40000>;
};
xbl_ramdump_mem: xbl_ramdump_region@80640000 {
no-map;
reg = <0x0 0x80640000 0x0 0x1c0000>;
};
aop_image_mem: aop_image_region@80800000 {
no-map;
reg = <0x0 0x80800000 0x0 0x60000>;
};
aop_cmd_db_mem: aop_cmd_db_region@80860000 {
compatible = "qcom,cmd-db";
no-map;
reg = <0x0 0x80860000 0x0 0x20000>;
};
aop_config_mem: aop_config_region@80880000 {
no-map;
reg = <0x0 0x80880000 0x0 0x20000>;
};
tme_crash_dump_mem: tme_crash_dump_region@808a0000 {
no-map;
reg = <0x0 0x808a0000 0x0 0x40000>;
};
tme_log_mem: tme_log_region@808e0000 {
no-map;
reg = <0x0 0x808e0000 0x0 0x4000>;
};
uefi_log_mem: uefi_log_region@808e4000 {
no-map;
reg = <0x0 0x808e4000 0x0 0x10000>;
};
chipinfo_mem: chipinfo_region@808f4000 {
no-map;
reg = <0x0 0x808f4000 0x0 0x1000>;
};
smem_mem: smem_region@80900000 {
no-map;
reg = <0x0 0x80900000 0x0 0x200000>;
};
cpucp_fw_mem: cpucp_fw_region@80b00000 {
no-map;
reg = <0x0 0x80b00000 0x0 0x100000>;
};
wlan_msa_mem: wlan_msa_mem_region@82a00000 {
no-map;
reg = <0x0 0x82a00000 0x0 0xc00000>;
};
camera_mem: camera_region@84b00000 {
no-map;
reg = <0x0 0x84b00000 0x0 0x800000>;
};
wpss_moselle_mem: wpss_moselle_region@85300000 {
no-map;
reg = <0x0 0x85300000 0x0 0x1900000>;
};
video_mem: video_region@86c00000 {
no-map;
reg = <0x0 0x86c00000 0x0 0x700000>;
};
adsp_mem: adsp_region@87300000 {
no-map;
reg = <0x0 0x87300000 0x0 0x2100000>;
};
ipa_fw_mem: ipa_fw_region@89400000 {
no-map;
reg = <0x0 0x89400000 0x0 0x10000>;
};
ipa_gsi_mem: ipa_gsi_region@89410000 {
no-map;
reg = <0x0 0x89410000 0x0 0xa000>;
};
gpu_microcode_mem: gpu_microcode_region@8941a000 {
no-map;
reg = <0x0 0x8941a000 0x0 0x2000>;
};
mpss_mem: mpss_region@8a000000 {
no-map;
reg = <0x0 0x8a000000 0x0 0xda00000>;
};
xbl_sc_mem: xbl_sc_region@a6e00000 {
no-map;
reg = <0x0 0xa6e00000 0x0 0x40000>;
};
global_sync_mem: global_sync_region@a6f00000 {
no-map;
reg = <0x0 0xa6f00000 0x0 0x100000>;
};
cpusys_vm_mem: cpusys_vm_region@e0600000 {
no-map;
reg = <0x0 0xe0600000 0x0 0x400000>;
};
trust_ui_vm_mem: trust_ui_vm_region@e0b00000 {
no-map;
reg = <0x0 0xe0b00000 0x0 0x4af3000>;
};
trust_ui_vm_qrtr: trust_ui_vm_qrtr@e55f3000 {
no-map;
reg = <0x0 0xe55f3000 0x0 0x9000>;
};
trust_ui_vm_vblk0_ring: trust_ui_vm_vblk0_ring@e55fc000 {
no-map;
reg = <0x0 0xe55fc000 0x0 0x4000>;
gunyah-label = <0x11>;
};
trust_ui_vm_swiotlb: trust_ui_vm_swiotlb@e5600000 {
no-map;
reg = <0x0 0xe5600000 0x0 0x100000>;
gunyah-label = <0x12>;
};
tz_stat_mem: tz_stat_region@e8800000 {
no-map;
reg = <0x0 0xe8800000 0x0 0x100000>;
};
tags_mem: tags_region@e8900000 {
no-map;
reg = <0x0 0xe8900000 0x0 0x680000>;
};
qtee_mem: qtee_region@e8f80000 {
no-map;
reg = <0x0 0xe8f80000 0x0 0x500000>;
};
trusted_apps_mem: trusted_apps_region@e9480000 {
no-map;
reg = <0x0 0xe9480000 0x0 0x1200000>;
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "ravelin-rumi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Ravelin RUMI";
compatible = "qcom,ravelin-rumi", "qcom,ravelin", "qcom,rumi";
qcom,msm-id = <568 0x10000>;
qcom,board-id = <0x1000F 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/memreserve/ 0x90000000 0x00010000;
#include "ravelin.dtsi"
#include "ravelin-rumi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Ravelin RUMI";
compatible = "qcom,ravelin-rumi", "qcom,ravelin", "qcom,rumi";
qcom,board-id = <0x1000F 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,sm4450-gcc.h>
#include <dt-bindings/gpio/gpio.h>
&soc {
timer {
clock-frequency = <500000>;
};
timer@17420000 {
clock-frequency = <500000>;
};
qcom,wdt@17410000 {
status = "disabled";
};
usb_emuphy: phy@a784000 {
compatible = "qcom,usb-emu-phy";
reg = <0x0a784000 0x9500>;
qcom,emu-init-seq = <0xfffff 0x4
0xffff0 0x4
0x100000 0x20
0x0 0x20
0x000001A0 0x20
0x00100000 0x3c
0x0 0x3c
0x0 0x4>;
};
bi_tcxo: bi_tcxo {
compatible = "fixed-factor-clock";
clock-mult = <1>;
clock-div = <4>;
clocks = <&xo_board>;
#clock-cells = <0>;
};
bi_tcxo_ao: bi_tcxo_ao {
compatible = "fixed-factor-clock";
clock-mult = <1>;
clock-div = <4>;
clocks = <&xo_board>;
#clock-cells = <0>;
};
};
&SILVER_CPU_OFF {
status = "nok";
};
&SILVER_CPU_RAIL_OFF {
status = "nok";
};
&GOLD_CPU_OFF {
status = "nok";
};
&GOLD_CPU_RAIL_OFF {
status = "nok";
};
&CLUSTER_OFF {
status = "nok";
};
&CX_RET {
status = "nok";
};
&disp_rsc {
status = "nok";
};
&usb0 {
dwc3@a600000 {
usb-phy = <&usb_emuphy>, <&usb_nop_phy>;
dr_mode = "peripheral";
maximum-speed = "high-speed";
};
};
&qupv3_se7_2uart {
qcom,rumi_platform;
};
&ufsphy_mem {
compatible = "qcom,ufs-phy-qrbtc-sdm845";
vdda-phy-supply = <&L5B>;
vdda-pll-supply = <&L16B>;
vdda-phy-max-microamp = <85710>;
vdda-pll-max-microamp = <18330>;
status = "ok";
};
&ufshc_mem {
limit-tx-hs-gear = <1>;
limit-rx-hs-gear = <1>;
limit-rate = <2>; /* HS Rate-B */
vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
vdd-hba-fixed-regulator;
vcc-supply = <&L24B>;
vcc-max-microamp = <1056000>;
vccq-supply = <&L13B>;
vccq-max-microamp = <750000>;
vccq2-supply = <&L19B>;
vccq2-max-microamp = <750000>;
qcom,vddp-ref-clk-supply = <&L13B>;
qcom,vddp-ref-clk-max-microamp = <70>;
qcom,disable-lpm;
rpm-level = <0>;
spm-level = <0>;
status = "ok";
};
&sdhc_1 {
status = "ok";
vdd-supply = <&L5E>;
qcom,vdd-voltage-level = <2960000 2960000>;
qcom,vdd-current-level = <0 570000>;
vdd-io-supply = <&L19B>;
qcom,vdd-io-always-on;
qcom,vdd-io-lpm-sup;
qcom,vdd-io-voltage-level = <1800000 1800000>;
qcom,vdd-io-current-level = <0 325000>;
/delete-property/ mmc-ddr-1_8v;
/delete-property/ mmc-hs200-1_8v;
/delete-property/ mmc-hs400-1_8v;
/delete-property/ mmc-hs400-enhanced-strobe;
max-frequency = <100000000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_on>;
pinctrl-1 = <&sdc1_off>;
};
&sdhc_2 {
status = "ok";
vdd-supply = <&L24B>;
qcom,vdd-voltage-level = <2960000 2960000>;
qcom,vdd-current-level = <0 800000>;
vdd-io-supply = <&L28B>;
qcom,vdd-io-voltage-level = <2960000 2960000>;
qcom,vdd-io-current-level = <0 22000>;
is_rumi;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
cd-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
};
&gcc {
clocks = <&bi_tcxo>, <&sleep_clk>,
<&pcie_0_pipe_clk>, <&ufs_phy_rx_symbol_0_clk>,
<&ufs_phy_rx_symbol_1_clk>, <&ufs_phy_tx_symbol_0_clk>,
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
};
&camcc {
clocks = <&bi_tcxo>,
<&gcc GCC_CAMERA_AHB_CLK>;
};
&dispcc {
clocks = <&bi_tcxo>, <&bi_tcxo_ao>,
<&sleep_clk>, <&gcc GCC_DISP_AHB_CLK>;
};
&gpucc {
clocks = <&bi_tcxo>,
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>,
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
};
&debugcc {
clocks = <&bi_tcxo>,
<&gcc 0>, <&camcc 0>,
<&dispcc 0>, <&gpucc 0>;
};
&rpmhcc {
compatible = "qcom,dummycc";
clock-output-names = "rpmhcc_clocks";
};
&cpufreq_hw {
clocks = <&bi_tcxo>, <&gcc GCC_GPLL0>;
};
&tsens0 {
status = "disabled";
};
&tsens1 {
status = "disabled";
};
&pcie0 {
reg = <0x01c00000 0x3000>,
<0x01c06000 0x2000>,
<0x60000000 0xf1d>,
<0x60000f20 0xa8>,
<0x60001000 0x1000>,
<0x60100000 0x100000>,
<0x01c05000 0x1000>;
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf",
"rumi";
qcom,target-link-speed = <0x1>;
qcom,link-check-max-count = <200>; /* 1 sec */
qcom,no-l1-supported;
qcom,no-l1ss-supported;
qcom,no-aux-clk-sync;
status = "ok";
};
&pcie0_msi {
status = "ok";
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
/ {
VDD_MODEM_LEVEL:
S1B_LEVEL:
pm6450_s1_level: regulator-pm6450-s1-level {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_s1_level";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
};
VDD_MX_LEVEL:
S2B_LEVEL:
pm6450_s2_level: regulator-pm6450_s2_level {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_s2_level";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
};
VDD_CX_LEVEL:
S5B_LEVEL:
pm6450_s5_level: regulator-pm6450-s5-level {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_s5_level";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
};
VDD_EBI_LEVEL:
S6B_LEVEL:
pm6450_s6: regulator-pm6450-s6-level {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_s6_level";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
};
S7B:
pm6450_s7: regulator-pm6450-s7 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_s7";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1010000>;
regulator-max-microvolt = <1170000>;
};
S8B:
pm6450_s8: regulator-pm6450-s8 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_s8";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <598000>;
regulator-max-microvolt = <1654000>;
};
S9B:
pm6450_s9: regulator-pm6450-s9 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_s9";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <1900000>;
};
L1B:
pm6450_l1: regulator-pm6450-l1 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l1";
qcom,hpm-min-load = <30000>;
regulator-min-microvolt = <312000>;
regulator-max-microvolt = <650000>;
};
VDD_LPI_CX_LEVEL:
L2B_LEVEL:
pm6450_l2_level: regulator-pm6450-l2-level {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l2_level";
qcom,hpm-min-load = <30000>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
};
L3B:
pm6450_l3: regulator-pm6450-l3 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l3";
qcom,hpm-min-load = <30000>;
regulator-min-microvolt = <870000>;
regulator-max-microvolt = <970000>;
};
L5B:
pm6450_l5: regulator-pm6450-l5 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l5";
qcom,hpm-min-load = <30000>;
regulator-min-microvolt = <830000>;
regulator-max-microvolt = <920000>;
};
L6B:
pm6450_l6: regulator-pm6450-l6 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l6";
qcom,hpm-min-load = <30000>;
regulator-min-microvolt = <751000>;
regulator-max-microvolt = <824000>;
};
L7B:
pm6450_l7: regulator-pm6450-l7 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l7";
qcom,hpm-min-load = <30000>;
regulator-min-microvolt = <830000>;
regulator-max-microvolt = <920000>;
};
VDD_LPI_MX_LEVEL:
L8B_LEVEL:
pm6450_l8_level: regulator-pm6450-l8-level {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l8_level";
qcom,hpm-min-load = <30000>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
};
L9B:
pm6450_l9: regulator-pm6450-l9 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l9";
qcom,hpm-min-load = <30000>;
regulator-min-microvolt = <870000>;
regulator-max-microvolt = <970000>;
};
L10B:
pm6450_l10: regulator-pm6450-l10 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l10";
qcom,hpm-min-load = <30000>;
regulator-min-microvolt = <824000>;
regulator-max-microvolt = <901000>;
};
L11B:
pm6450_l11: regulator-pm6450-l11 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l11";
qcom,hpm-min-load = <30000>;
regulator-min-microvolt = <348000>;
regulator-max-microvolt = <888000>;
};
L12B:
pm6450_l12: regulator-pm6450-l12 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l12";
qcom,hpm-min-load = <30000>;
regulator-min-microvolt = <1139000>;
regulator-max-microvolt = <1236000>;
};
L13B:
pm6450_l13: regulator-pm6450-l13 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l13";
qcom,hpm-min-load = <30000>;
regulator-min-microvolt = <1080000>;
regulator-max-microvolt = <1304000>;
};
L14B:
pm6450_l14: regulator-pm6450-l14 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l14";
qcom,hpm-min-load = <30000>;
regulator-min-microvolt = <1170000>;
regulator-max-microvolt = <1304000>;
};
L15B:
pm6450_l15: regulator-pm6450-l15 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l15";
qcom,hpm-min-load = <30000>;
regulator-min-microvolt = <1080000>;
regulator-max-microvolt = <1304000>;
};
L16B:
pm6450_l16: regulator-pm6450-l16 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l16";
qcom,hpm-min-load = <30000>;
regulator-min-microvolt = <1140000>;
regulator-max-microvolt = <1260000>;
};
L17B:
pm6450_l17: regulator-pm6450-l17 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l17";
qcom,hpm-min-load = <30000>;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
L18B:
pm6450_l18: regulator-pm6450-l18 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l18";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1504000>;
regulator-max-microvolt = <2000000>;
};
L19B:
pm6450_l19: regulator-pm6450-l19 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l19";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
};
L20B:
pm6450_l20: regulator-pm6450-l20 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l20";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <1900000>;
};
L21B:
pm6450_l21: regulator-pm6450-l21 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l21";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1504000>;
regulator-max-microvolt = <2000000>;
};
L22B:
pm6450_l22: regulator-pm6450-l22 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l22";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1550000>;
regulator-max-microvolt = <2000000>;
};
L23B:
pm6450_l23: regulator-pm6450-l23 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l23";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <1950000>;
};
L24B:
pm6450_l24: regulator-pm6450-l24 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l24";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3544000>;
};
L25B:
pm6450_l25: regulator-pm6450-l25 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l25";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3544000>;
};
L26B:
pm6450_l26: regulator-pm6450-l26 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l26";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3300000>;
};
L27B:
pm6450_l27: regulator-pm6450-l27 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l27";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3300000>;
};
L28B:
pm6450_l28: regulator-pm6450-l28 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l28";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <3300000>;
};
L1M: pm8010m_l1: regulator-pm8010m-l1 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8010m_l1";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1200000>;
qcom,hpm-min-load = <30000>;
};
L2M: pm8010m_l2: regulator-pm8010m-l2 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8010m_l2";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1150000>;
qcom,hpm-min-load = <30000>;
};
L3M: pm8010m_l3: regulator-pm8010m-l3 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8010m_l3";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3000000>;
qcom,hpm-min-load = <30000>;
};
L4M: pm8010m_l4: regulator-pm8010m-l4 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8010m_l4";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2900000>;
qcom,hpm-min-load = <30000>;
};
L6M: pm8010m_l6: regulator-pm8010m-l6 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8010m_l6";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2900000>;
qcom,hpm-min-load = <30000>;
};
L7M: pm8010m_l7: regulator-pm8010m-l7 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8010m_l7";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3000000>;
qcom,hpm-min-load = <30000>;
};
L1N: pm8010n_l1: regulator-pm8010n-l1 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8010n_l1";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1150000>;
qcom,hpm-min-load = <30000>;
};
L3N: pm8010n_l3: regulator-pm8010n-l3 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8010n_l3";
regulator-min-microvolt = <1792000>;
regulator-max-microvolt = <1900000>;
qcom,hpm-min-load = <30000>;
};
L4N: pm8010n_l4: regulator-pm8010n-l4 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8010n_l4";
regulator-min-microvolt = <1792000>;
regulator-max-microvolt = <1900000>;
qcom,hpm-min-load = <30000>;
};
L6N: pm8010n_l6: regulator-pm8010n-l6 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8010n_l6";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2900000>;
qcom,hpm-min-load = <30000>;
};
L1E: pm8010e_l1: regulator-pm8010e-l1 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8010e_l1";
regulator-min-microvolt = <751000>;
regulator-max-microvolt = <824000>;
qcom,hpm-min-load = <30000>;
};
L4E: pm8010e_l4: regulator-pm8010e-l4 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8010e_l4";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3312000>;
qcom,hpm-min-load = <30000>;
};
L5E: pm8010e_l5: regulator-pm8010e-l5 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8010e_l5";
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <3544000>;
qcom,hpm-min-load = <30000>;
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/thermal/thermal_qti.h>
&soc {
qmi-tmd-devices {
compatible = "qcom,qmi-cooling-devices";
modem {
qcom,instance-id = <QMI_MODEM_INST_ID>;
modem_lte_dsc: modem_lte_dsc {
qcom,qmi-dev-name = "modem_lte_dsc";
#cooling-cells = <2>;
};
modem_lte_sub1_dsc: modem_lte_sub1_dsc {
qcom,qmi-dev-name = "modem_lte_sub1_dsc";
#cooling-cells = <2>;
};
modem_nr_dsc: modem_nr_dsc {
qcom,qmi-dev-name = "modem_nr_dsc";
#cooling-cells = <2>;
};
modem_nr_sub1_dsc: modem_nr_sub1_dsc {
qcom,qmi-dev-name = "modem_nr_sub1_dsc";
#cooling-cells = <2>;
};
modem_nr_scg_dsc: modem_nr_scg_dsc {
qcom,qmi-dev-name = "modem_nr_scg_dsc";
#cooling-cells = <2>;
};
modem_nr_scg_sub1_dsc: modem_nr_scg_sub1_dsc {
qcom,qmi-dev-name = "modem_nr_scg_sub1_dsc";
#cooling-cells = <2>;
};
sdr0_lte_dsc: sdr0_lte_dsc {
qcom,qmi-dev-name = "sdr0_lte_dsc";
#cooling-cells = <2>;
};
sdr1_lte_dsc: sdr1_lte_dsc {
qcom,qmi-dev-name = "sdr1_lte_dsc";
#cooling-cells = <2>;
};
sdr0_nr_dsc: sdr0_nr_dsc {
qcom,qmi-dev-name = "sdr0_nr_dsc";
#cooling-cells = <2>;
};
sdr1_nr_dsc: sdr1_nr_dsc {
qcom,qmi-dev-name = "sdr1_nr_dsc";
#cooling-cells = <2>;
};
pa_lte_sdr0_dsc: pa_lte_sdr0_dsc {
qcom,qmi-dev-name = "pa_lte_sdr0_dsc";
#cooling-cells = <2>;
};
pa_lte_sdr1_dsc: pa_lte_sdr1_dsc {
qcom,qmi-dev-name = "pa_lte_sdr1_dsc";
#cooling-cells = <2>;
};
pa_lte_sdr0_sub1_dsc: pa_lte_sdr0_sub1_dsc {
qcom,qmi-dev-name = "pa_lte_sdr0_sub1_dsc";
#cooling-cells = <2>;
};
pa_lte_sdr1_sub1_dsc: pa_lte_sdr1_sub1_dsc {
qcom,qmi-dev-name = "pa_lte_sdr1_sub1_dsc";
#cooling-cells = <2>;
};
pa_nr_sdr0_dsc: pa_nr_sdr0_dsc {
qcom,qmi-dev-name = "pa_nr_sdr0_dsc";
#cooling-cells = <2>;
};
pa_nr_sdr1_dsc: pa_nr_sdr1_dsc {
qcom,qmi-dev-name = "pa_nr_sdr1_dsc";
#cooling-cells = <2>;
};
pa_nr_sdr0_sub1_dsc: pa_nr_sdr0_sub1_dsc {
qcom,qmi-dev-name = "pa_nr_sdr0_sub1_dsc";
#cooling-cells = <2>;
};
pa_nr_sdr1_sub1_dsc: pa_nr_sdr1_sub1_dsc {
qcom,qmi-dev-name = "pa_nr_sdr1_sub1_dsc";
#cooling-cells = <2>;
};
pa_nr_sdr0_scg_dsc: pa_nr_sdr0_scg {
qcom,qmi-dev-name = "pa_nr_sdr0_scg_dsc";
#cooling-cells = <2>;
};
pa_nr_sdr1_scg_dsc: pa_nr_sdr1_scg {
qcom,qmi-dev-name = "pa_nr_sdr1_scg_dsc";
#cooling-cells = <2>;
};
qmi_wlan: wlan {
qcom,qmi-dev-name = "wlan";
#cooling-cells = <2>;
};
modem_vdd: modem_vdd {
qcom,qmi-dev-name = "cpuv_restriction_cold";
#cooling-cells = <2>;
};
};
};
qmi_sensor: qmi-ts-sensors {
compatible = "qcom,qmi-sensors";
#thermal-sensor-cells = <1>;
modem {
qcom,instance-id = <QMI_MODEM_INST_ID>;
qcom,qmi-sensor-names = "pa",
"pa_1",
"modem_bcl_warn",
"modem_cfg",
"lte_cc",
"mcg_fr1_cc",
"scg_fr1_cc",
"sub1_modem_cfg",
"sub1_lte_cc",
"sub1_mcg_fr1_cc",
"sub1_scg_fr1_cc",
"sdr0_pa0",
"sdr1_pa0",
"sdr0",
"sdr1";
};
};
};
&thermal_zones {
pa {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_PA)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
pa1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_PA_1)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
bcl-warn {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_BCL_WARN)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
modem-cfg {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_EPM2)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
lte-cc {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_EPM3)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
mcg-fr1-cc {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_EPM4)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
scg-fr1-cc {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_EPM6)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sub1-modem-cfg {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SUB1_MODEM_CFG)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sub1-lte-cc {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SUB1_LTE_CC)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sub1_mcg_fr1_cc {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SUB1_MCG_FR1_CC)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sub1_scg_fr1_cc {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SUB1_SCG_FR1_CC)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sdr0-pa {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SDR0_PA)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sdr1-pa {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SDR1_PA)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sdr0 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SDR0)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sdr1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SDR1)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/thermal/thermal_qti.h>
&thermal_zones {
pm6450_tz {
cooling-maps {
pm6450_lte {
trip = <&pm6450_trip0>;
cooling-device = <&modem_lte_dsc 255 255>;
};
pm6450_nr {
trip = <&pm6450_trip0>;
cooling-device = <&modem_nr_scg_dsc 255 255>;
};
pm6450_cpu0 {
trip = <&pm6450_trip0>;
cooling-device = <&cpu0_pause 1 1>;
};
pm6450_cpu1 {
trip = <&pm6450_trip0>;
cooling-device = <&cpu1_pause 1 1>;
};
pm6450_cpu2 {
trip = <&pm6450_trip0>;
cooling-device = <&cpu2_pause 1 1>;
};
pm6450_cpu3 {
trip = <&pm6450_trip0>;
cooling-device = <&cpu3_pause 1 1>;
};
pm6450_cpu4 {
trip = <&pm6450_trip0>;
cooling-device = <&cpu4_pause 1 1>;
};
pm6450_cpu5 {
trip = <&pm6450_trip0>;
cooling-device = <&cpu5_pause 1 1>;
};
pm6450_cpu6_7 {
trip = <&pm6450_trip0>;
cooling-device = <&cpu_6_7_pause 1 1>;
};
pm6450_gpu {
trip = <&pm6450_trip0>;
cooling-device = <&msm_gpu 3 THERMAL_NO_LIMIT>;
};
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/thermal/thermal_qti.h>
&msm_gpu {
#cooling-cells = <2>;
};
&soc {
tsens0: thermal-sensor@c263000 {
compatible = "qcom,tsens-v2";
reg = <0x0c263000 0x1ff>, /* TM */
<0x0c222000 0x1ff>; /* SROT */
#qcom,sensors = <16>;
interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 500 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "uplow","critical", "cold";
#thermal-sensor-cells = <1>;
};
tsens1: thermal-sensor@c265000 {
compatible = "qcom,tsens-v2";
reg = <0x0c265000 0x1ff>, /* TM */
<0x0c223000 0x1ff>; /* SROT */
#qcom,sensors = <16>;
interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 501 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "uplow","critical", "cold";
#thermal-sensor-cells = <1>;
};
qcom,cpu-pause {
compatible = "qcom,thermal-pause";
cpu0_pause: cpu0-pause {
qcom,cpus = <&CPU0>;
qcom,cdev-alias = "thermal-pause-1";
#cooling-cells = <2>;
};
cpu1_pause: cpu1-pause {
qcom,cpus = <&CPU1>;
qcom,cdev-alias = "thermal-pause-2";
#cooling-cells = <2>;
};
cpu2_pause: cpu2-pause {
qcom,cpus = <&CPU2>;
qcom,cdev-alias = "thermal-pause-4";
#cooling-cells = <2>;
};
cpu3_pause: cpu3-pause {
qcom,cpus = <&CPU3>;
qcom,cdev-alias = "thermal-pause-8";
#cooling-cells = <2>;
};
cpu4_pause: cpu4-pause {
qcom,cpus = <&CPU4>;
qcom,cdev-alias = "thermal-pause-10";
#cooling-cells = <2>;
};
cpu5_pause: cpu5-pause {
qcom,cpus = <&CPU5>;
qcom,cdev-alias = "thermal-pause-20";
#cooling-cells = <2>;
};
cpu6_pause: cpu6-pause {
qcom,cpus = <&CPU6>;
qcom,cdev-alias = "thermal-pause-40";
#cooling-cells = <2>;
};
cpu7_pause: cpu7-pause {
qcom,cpus = <&CPU7>;
qcom,cdev-alias = "thermal-pause-80";
#cooling-cells = <2>;
};
cpu_6_7_pause: cpu-6-7-pause {
qcom,cpus = <&CPU6 &CPU7>;
qcom,cdev-alias = "thermal-pause-C0";
#cooling-cells = <2>;
};
/* Thermal-engine cooling devices */
pause-cpu0 {
qcom,cpus = <&CPU0>;
qcom,cdev-alias = "pause-cpu0";
};
pause-cpu1 {
qcom,cpus = <&CPU1>;
qcom,cdev-alias = "pause-cpu1";
};
pause-cpu2 {
qcom,cpus = <&CPU2>;
qcom,cdev-alias = "pause-cpu2";
};
pause-cpu3 {
qcom,cpus = <&CPU3>;
qcom,cdev-alias = "pause-cpu3";
};
pause-cpu4 {
qcom,cpus = <&CPU4>;
qcom,cdev-alias = "pause-cpu4";
};
pause-cpu5 {
qcom,cpus = <&CPU5>;
qcom,cdev-alias = "pause-cpu5";
};
pause-cpu6 {
qcom,cpus = <&CPU6>;
qcom,cdev-alias = "pause-cpu6";
};
pause-cpu7 {
qcom,cpus = <&CPU7>;
qcom,cdev-alias = "pause-cpu7";
};
};
qcom,cpu-hotplug {
compatible = "qcom,cpu-hotplug";
cpu0_hotplug: cpu0-hotplug {
qcom,cpu = <&CPU0>;
qcom,cdev-alias = "cpu-hotplug0";
#cooling-cells = <2>;
};
cpu1_hotplug: cpu1-hotplug {
qcom,cpu = <&CPU1>;
qcom,cdev-alias = "cpu-hotplug1";
#cooling-cells = <2>;
};
cpu2_hotplug: cpu2-hotplug {
qcom,cpu = <&CPU2>;
qcom,cdev-alias = "cpu-hotplug2";
#cooling-cells = <2>;
};
cpu3_hotplug: cpu3-hotplug {
qcom,cpu = <&CPU3>;
qcom,cdev-alias = "cpu-hotplug3";
#cooling-cells = <2>;
};
cpu4_hotplug: cpu4-hotplug {
qcom,cpu = <&CPU4>;
qcom,cdev-alias = "cpu-hotplug4";
#cooling-cells = <2>;
};
cpu5_hotplug: cpu5-hotplug {
qcom,cpu = <&CPU5>;
qcom,cdev-alias = "cpu-hotplug5";
#cooling-cells = <2>;
};
cpu6_hotplug: cpu6-hotplug {
qcom,cpu = <&CPU6>;
qcom,cdev-alias = "cpu-hotplug6";
#cooling-cells = <2>;
};
cpu7_hotplug: cpu7-hotplug {
qcom,cpu = <&CPU7>;
qcom,cdev-alias = "cpu-hotplug7";
#cooling-cells = <2>;
};
};
thermal_ddr_freq_table: thermal-ddr-freq-table {
qcom,freq-tbl = < 2092800 >;
};
ddr_cdev: qcom,ddr-cdev {
compatible = "qcom,ddr-cooling-device";
#cooling-cells = <2>;
qcom,freq-table = <&thermal_ddr_freq_table>;
qcom,bus-width = <4>;
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
};
qcom,cpufreq-cdev {
compatible = "qcom,cpufreq-cdev";
cpu-cluster0 {
qcom,cpus = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
};
cpu-cluster1 {
qcom,cpus = <&CPU6 &CPU7>;
};
};
qcom,devfreq-cdev {
compatible = "qcom,devfreq-cdev";
qcom,devfreq = <&msm_gpu>;
};
qcom,userspace-cdev {
compatible = "qcom,userspace-cooling-devices";
display_fps: display-fps {
qcom,max-level = <3>;
#cooling-cells = <2>;
};
};
cx_sdpm@634000 {
compatible = "qcom,sdpm";
reg = <0x00634000 0x1000>;
clock-names = "gpu_cc_gx_gfx3d",
"cam_cc_camnoc_axi",
"cam_cc_bps",
"gcc_video_venus",
"disp_cc_mdss_mdp";
clocks = <&gpucc GPU_CC_GX_GFX3D_CLK_SRC>,
<&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
<&camcc CAM_CC_BPS_CLK_SRC>,
<&gcc GCC_VIDEO_VENUS_CLK_SRC>,
<&dispcc DISP_CC_MDSS_MDP_CLK_SRC>;
csr-id = <0 1 2 6 7>;
};
cx_pe: cx_rdpm_pe@635000 {
compatible = "qcom,policy-engine";
#thermal-sensor-cells = <0>;
reg = <0x635000 0x1000>;
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
};
};
#include "ravelin-thermal-modem.dtsi"
&thermal_zones {
aoss-0 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 0>;
trips {
thermal-engine-config {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
};
};
cpu-0-0 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 1>;
trips {
thermal-engine-config {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
cpu0_emerg: cpu0-emerg-cfg {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
};
};
cooling-maps {
cpu00_cdev {
trip = <&cpu0_emerg>;
cooling-device = <&cpu0_pause 1 1>;
};
};
};
cpu-0-1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 2>;
trips {
thermal-engine-config {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
cpu1_emerg: cpu1-emerg-cfg {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
};
};
cooling-maps {
cpu01_cdev {
trip = <&cpu1_emerg>;
cooling-device = <&cpu1_pause 1 1>;
};
};
};
cpu-0-2 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 3>;
trips {
thermal-engine-config {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
cpu2_emerg: cpu2-emerg-cfg {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
};
};
cooling-maps {
cpu02_cdev {
trip = <&cpu2_emerg>;
cooling-device = <&cpu2_pause 1 1>;
};
};
};
cpu-0-3 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 4>;
trips {
thermal-engine-config {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
cpu3_emerg: cpu3-emerg-cfg {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
};
};
cooling-maps {
cpu03_cdev {
trip = <&cpu3_emerg>;
cooling-device = <&cpu3_pause 1 1>;
};
};
};
cpu-0-4 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 5>;
trips {
thermal-engine-config {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
cpu4_emerg: cpu4-emerg-cfg {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
};
};
cooling-maps {
cpu04_cdev {
trip = <&cpu4_emerg>;
cooling-device = <&cpu4_pause 1 1>;
};
};
};
cpu-0-5 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 6>;
trips {
thermal-engine-config {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
cpu5_emerg: cpu5-emerg-cfg {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
};
};
cooling-maps {
cpu05_cdev {
trip = <&cpu5_emerg>;
cooling-device = <&cpu5_pause 1 1>;
};
};
};
cpuss-0 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 7>;
trips {
thermal-engine-config {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
};
};
cpuss-1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 8>;
trips {
thermal-engine-config {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
};
};
cpu-1-0 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 9>;
trips {
thermal-engine-config {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
cpu6_emerg0: cpu6-emerg0-cfg {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
};
};
cooling-maps {
cpu10_cdev {
trip = <&cpu6_emerg0>;
cooling-device = <&cpu6_pause 1 1>;
};
};
};
cpu-1-1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 10>;
trips {
thermal-engine-config {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
cpu6_emerg1: cpu6-emerg1-cfg {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
};
};
cooling-maps {
cpu11_cdev {
trip = <&cpu6_emerg1>;
cooling-device = <&cpu6_pause 1 1>;
};
};
};
cpu-1-2 {
polling-delay-passive = <10>;
polling-delay = <0>;
thermal-sensors = <&tsens0 11>;
trips {
thermal-engine-config {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
cpu7_emerg0: cpu7-emerg0-cfg {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
};
};
cooling-maps {
cpu12_cdev {
trip = <&cpu7_emerg0>;
cooling-device = <&cpu7_pause 1 1>;
};
};
};
cpu-1-3 {
polling-delay-passive = <10>;
polling-delay = <0>;
thermal-sensors = <&tsens0 12>;
trips {
thermal-engine-config {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
cpu7_emerg1: cpu7-emerg1-cfg {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
};
};
cooling-maps {
cpu13_cdev {
trip = <&cpu7_emerg1>;
cooling-device = <&cpu7_pause 1 1>;
};
};
};
gpuss {
polling-delay-passive = <10>;
polling-delay = <0>;
thermal-sensors = <&tsens0 13>;
trips {
thermal-engine-config {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
gpu_tj_cfg: tj_cfg {
temperature = <95000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
gpu_cdev {
trip = <&gpu_tj_cfg>;
cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>;
};
};
};
camera {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 14>;
trips {
thermal-engine-config {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
};
};
video {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 15>;
trips {
thermal-engine-config {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
};
};
aoss-1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens1 0>;
trips {
thermal-engine-config {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
};
};
ddr {
polling-delay-passive = <10>;
polling-delay = <0>;
thermal-sensors = <&tsens1 1>;
trips {
thermal-engine-config {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
ddr_config0: ddr0-config {
temperature = <90000>;
hysteresis = <5000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
ddr_cdev {
trip = <&ddr_config0>;
cooling-device = <&ddr_cdev 1 1>;
};
};
};
mdmss-0 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens1 2>;
trips {
thermal-engine-config {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
};
};
mdmss-1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens1 3>;
trips {
thermal-engine-config {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
};
};
mdmss-2 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens1 4>;
trips {
thermal-engine-config {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
};
};
mdmss-3 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens1 5>;
trips {
thermal-engine-config {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
};
};
zeroc-0-step {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 128>;
trips {
thermal-engine-config {
temperature = <1>;
hysteresis = <1>;
type = "passive";
};
min_temp_0_trip: cold-trip {
temperature = <1>;
hysteresis = <1>;
type = "passive";
};
};
};
zeroc-1-step {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens1 128>;
trips {
thermal-engine-config {
temperature = <1>;
hysteresis = <1>;
type = "passive";
};
min_temp_1_trip: cold-trip {
temperature = <1>;
hysteresis = <1>;
type = "passive";
};
};
};
cx-pe {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&cx_pe>;
trips {
cx_pe_config1: cx-pe-config1 {
temperature = <1>;
hysteresis = <1>;
type = "passive";
};
};
cooling-maps {
gpu_cdev {
trip = <&cx_pe_config1>;
cooling-device = <&msm_gpu 3 3>;
};
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,sm4450-gcc.h>
#include <dt-bindings/phy/qcom,usb3-5nm-qmp-combo.h>
&soc {
usb0: ssusb@a600000 {
compatible = "qcom,dwc-usb3-msm";
reg = <0xa600000 0x100000>;
reg-names = "core_base";
#address-cells = <1>;
#size-cells = <1>;
ranges;
USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_PRIM_SLEEP_CLK>;
clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
"utmi_clk", "sleep_clk";
resets = <&gcc GCC_USB30_PRIM_BCR>;
reset-names = "core_reset";
interrupts-extended = <&pdc 14 IRQ_TYPE_EDGE_RISING>,
<&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 15 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
"ss_phy_irq", "dm_hs_phy_irq";
qcom,use-pdc-interrupts;
qcom,core-clk-rate = <133333333>;
qcom,core-clk-rate-hs = <66666667>;
qcom,pm-qos-latency = <2>;
qcom,num-gsi-evt-buffs = <0x3>;
qcom,gsi-reg-offset =
<0x0fc /* GSI_GENERAL_CFG */
0x110 /* GSI_DBL_ADDR_L */
0x120 /* GSI_DBL_ADDR_H */
0x130 /* GSI_RING_BASE_ADDR_L */
0x144 /* GSI_RING_BASE_ADDR_H */
0x1a4>; /* GSI_IF_STS */
usb-role-switch;
interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb";
interconnects = <&aggre2_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_USB3_0 &cnoc2 SLAVE_IPA_CFG>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_USB3_0>;
extcon = <&eud>;
dwc3@a600000 {
compatible = "snps,dwc3";
reg = <0xa600000 0xd800>;
iommus = <&apps_smmu 0x540 0x0>;
qcom,iommu-dma = "atomic";
qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
dma-coherent;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy>;
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x0>;
snps,is-utmi-l1-suspend;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
tx-fifo-resize;
dr_mode = "otg";
maximum-speed = "super-speed";
usb-role-switch;
};
port {
usb_port0: endpoint {
remote-endpoint = <&usb_port0_connector>;
};
};
};
/* USB port related High Speed PHY */
usb2_phy0: hsphy@88e3000 {
compatible = "qcom,usb-hsphy-snps-femto";
reg = <0x88e3000 0x11c>,
<0x088e2000 0x4>;
reg-names = "hsusb_phy_base",
"eud_enable_reg";
vdd-supply = <&L5B>;
vdda18-supply = <&L23B>;
vdda33-supply = <&L25B>;
qcom,vdd-voltage-level = <0 880000 920000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_EUSB3_0_CLKREF_EN>;
clock-names = "ref_clk_src", "ref_clk";
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
reset-names = "phy_reset";
};
usb_nop_phy: usb_nop_phy {
compatible = "usb-nop-xceiv";
};
/* USB port related QMP USB DP Combo PHY */
usb_qmp_dp_phy: ssphy@88e8000 {
compatible = "qcom,usb-ssphy-qmp-dp-combo";
reg = <0x88e8000 0x3000>;
reg-names = "qmp_phy_base";
vdd-supply = <&L7B>;
qcom,vdd-voltage-level = <0 912000 912000>;
qcom,vdd-max-load-uA = <47000>;
core-supply = <&L16B>;
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>,
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
<&gcc GCC_USB3_0_CLKREF_EN>;
clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
"pipe_clk_ext_src", "ref_clk_src",
"com_aux_clk", "ref_clk";
resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
<&gcc GCC_USB3_PHY_PRIM_BCR>;
reset-names = "global_phy_reset", "phy_reset";
pinctrl-names = "default";
pinctrl-0 = <&usb3phy_portselect_default>;
qcom,qmp-phy-reg-offset =
<USB3_DP_PCS_PCS_STATUS1
USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL
USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
USB3_DP_PCS_POWER_DOWN_CONTROL
USB3_DP_PCS_SW_RESET
USB3_DP_PCS_START_CONTROL
0xffff /* USB3_PHY_PCS_MISC_TYPEC_CTRL */
USB3_DP_COM_POWER_DOWN_CTRL
USB3_DP_COM_SW_RESET
USB3_DP_COM_RESET_OVRD_CTRL
USB3_DP_COM_PHY_MODE_CTRL
USB3_DP_COM_TYPEC_CTRL
USB3_DP_PCS_CLAMP_ENABLE>;
qcom,qmp-phy-init-seq =
/* <reg_offset, value>*/
<USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01
USB3_DP_QSERDES_COM_SSC_PER1 0x31
USB3_DP_QSERDES_COM_SSC_PER2 0x01
USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE
USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07
USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE
USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07
USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A
USB3_DP_QSERDES_COM_CMN_IPTRIM 0x20
USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x06
USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x06
USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16
USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x16
USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36
USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x36
USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1A
USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x04
USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x14
USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x34
USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x34
USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x82
USB3_DP_QSERDES_COM_DEC_START_MODE0 0x82
USB3_DP_QSERDES_COM_DEC_START_MODE1 0x82
USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB
USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA
USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02
USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB
USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA
USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02
USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x02
USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x24
USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x24
USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02
USB3_DP_QSERDES_COM_HSCLK_SEL 0x01
USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x08
USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA
USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E
USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA
USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E
USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11
USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x00
USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x00
USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x16
USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x0E
USB3_DP_QSERDES_TXA_LANE_MODE_1 0x35
USB3_DP_QSERDES_TXA_LANE_MODE_3 0x3F
USB3_DP_QSERDES_TXA_LANE_MODE_4 0x7F
USB3_DP_QSERDES_TXA_LANE_MODE_5 0x3F
USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12
USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x21
USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x09
USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x04
USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F
USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F
USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF
USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0F
USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99
USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x08
USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08
USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x00
USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x04
USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54
USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0F
USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0F
USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A
USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A
USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0xC0
USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00
USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47
USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04
USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E
USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0xBB
USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x7B
USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0xBB
USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x3D
USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0xDB
USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0x64
USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x24
USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0xD2
USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x13
USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xA9
USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04
USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38
USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0
USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C
USB3_DP_QSERDES_RXA_GM_CAL 0x00
USB3_DP_QSERDES_RXA_VTH_CODE 0x10
USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x00
USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x00
USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x16
USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x0E
USB3_DP_QSERDES_TXB_LANE_MODE_1 0x35
USB3_DP_QSERDES_TXB_LANE_MODE_3 0x3F
USB3_DP_QSERDES_TXB_LANE_MODE_4 0x7F
USB3_DP_QSERDES_TXB_LANE_MODE_5 0x3F
USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12
USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x21
USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x09
USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x04
USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F
USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F
USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF
USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0F
USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99
USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x08
USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08
USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x00
USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x04
USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54
USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0F
USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0F
USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A
USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A
USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0xC0
USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00
USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47
USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04
USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E
USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0xBB
USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0x7B
USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0xBB
USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x3C
USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xDB
USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0x64
USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x24
USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0xD2
USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x13
USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xA9
USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04
USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38
USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0
USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C
USB3_DP_QSERDES_RXB_GM_CAL 0x00
USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40
USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x00
USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7
USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H 0x03
USB3_DP_QSERDES_RXB_VTH_CODE 0x10
USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xC4
USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x89
USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20
USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13
USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21
USB3_DP_PCS_RX_SIGDET_LVL 0xAA
USB3_DP_PCS_CDR_RESET_TIME 0x0A
USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88
USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13
USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C
USB3_DP_PCS_EQ_CONFIG1 0x4B
USB3_DP_PCS_EQ_CONFIG5 0x10
USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8
USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07>;
};
usb_audio_qmi_dev {
compatible = "qcom,usb-audio-qmi-dev";
iommus = <&apps_smmu 0x100f 0x0>;
qcom,iommu-dma = "disabled";
qcom,usb-audio-stream-id = <0xf>;
qcom,usb-audio-intr-num = <2>;
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
&soc {
qcom,smp2p-wpss {
smp2p_wlan_2_in: qcom,smp2p-wlan-2-in {
qcom,entry-name = "wlan_soc_wake";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_wlan_2_out: qcom,smp2p-wlan-2-out {
qcom,entry-name = "wlan_soc_wake";
#qcom,smem-state-cells = <1>;
};
smp2p_wlan_3_out: qcom,smp2p-wlan-3-out {
qcom,entry-name = "wlan_ep_power_save";
#qcom,smem-state-cells = <1>;
};
};
wpss_pas: remoteproc-wpss@8a00000 {
firmware-name = "qca6750/wpss.mdt";
};
icnss2: qcom,wcn6750 {
status = "disabled";
compatible = "qcom,wcn6750";
reg = <0x17210040 0x0>,
<0xb0000000 0x10000>;
reg-names = "msi_addr", "smmu_iova_ipa";
qcom,rproc-handle = <&wpss_pas>;
iommus = <&apps_smmu 0x1400 0x1>;
interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
qcom,iommu-dma = "fastmap";
qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal";
qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
qcom,iommu-geometry = <0xa0000000 0x10010000>;
dma-coherent;
qcom,fw-prefix;
qcom,wlan;
tsens = "quiet-therm";
qcom,wlan-msa-fixed-region = <&wlan_msa_mem>;
vdd-cx-mx-supply = <&S7B>;
qcom,vdd-cx-mx-config = <1010000 1120000 0 0 1>;
vdd-1.8-xo-supply = <&S9B>;
qcom,vdd-1.8-xo-config = <1856000 2040000 0 0 0>;
vdd-1.3-rfa-supply = <&S8B>;
qcom,vdd-1.3-rfa-config = <1250000 1352000 0 0 0>;
qcom,smem-states = <&smp2p_wlan_1_out 0>,
<&smp2p_wlan_2_out 0>,
<&smp2p_wlan_3_out 0>;
qcom,smem-state-names = "wlan-smp2p-out",
"wlan-soc-wake-smp2p-out",
"wlan-ep-powersave-smp2p-out";
icnss_cdev_apss: qcom,icnss_cdev1 {
#cooling-cells = <2>;
};
icnss_cdev_wpss: qcom,icnss_cdev2 {
#cooling-cells = <2>;
};
qcom,smp2p_map_wlan_1_in {
interrupts-extended = <&smp2p_wlan_1_in 0 0>,
<&smp2p_wlan_1_in 1 0>;
interrupt-names = "qcom,smp2p-force-fatal-error",
"qcom,smp2p-early-crash-ind";
};
qcom,smp2p_map_wlan_2_in {
interrupts-extended = <&smp2p_wlan_2_in 0 0>;
interrupt-names = "qcom,smp2p-soc-wake-ack";
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "ravelin.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Ravelin SoC";
compatible = "qcom,ravelin";
qcom,board-id = <0 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "ravelinp-4gb.dtsi"
/ {
model = "Qualcomm Technologies, Inc. RavelinP 4Gb SoC";
compatible = "qcom,ravelinp";
qcom,board-id = <0 0x600>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "ravelinp.dtsi"
#include "ravelin-low-memory.dtsi"
/ {
};
&soc {
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "ravelinp.dtsi"
#include "ravelinp-atp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. RavelinP ATP";
compatible = "qcom,ravelinp-atp", "qcom,ravelinp", "qcom,atp";
qcom,board-id = <33 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "ravelin-atp.dtsi"

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "ravelinp.dtsi"
#include "ravelinp-idp-wcn3950-amoled-rcm.dtsi"
/ {
model = "Qualcomm Technologies, Inc. RavelinP WCN3950 IDP + AMOLED + RCM";
compatible = "qcom,ravelinp-idp", "qcom,ravelinp", "qcom,idp";
qcom,board-id = <34 2>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "ravelin-idp-wcn3950-amoled-rcm.dtsi"

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "ravelinp-4gb.dtsi"
#include "ravelinp-idp-wcn3988-4gb.dtsi"
/ {
model = "Qualcomm Technologies, Inc. RavelinP IDP 4GB DDR + WCN3988";
compatible = "qcom,ravelinp-idp", "qcom,ravelinp", "qcom,idp";
qcom,board-id = <34 0x601>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "ravelin-idp-wcn3988-4gb.dtsi"

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "ravelinp.dtsi"
#include "ravelinp-idp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. RavelinP IDP";
compatible = "qcom,ravelinp-idp", "qcom,ravelinp", "qcom,idp";
qcom,board-id = <34 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "ravelin-idp.dtsi"

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "ravelinp-4gb.dtsi"
#include "ravelinp-qrd-4gb.dtsi"
/ {
model = "Qualcomm Technologies, Inc. RavelinP QRD 4GB DDR";
compatible = "qcom,ravelinp-qrd", "qcom,ravelinp", "qcom,qrd";
qcom,board-id = <0x1000B 0x600>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "ravelin-qrd.dtsi"

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "ravelinp.dtsi"
#include "ravelinp-qrd.dtsi"
/ {
model = "Qualcomm Technologies, Inc. RavelinP QRD";
compatible = "qcom,ravelinp-qrd", "qcom,ravelinp", "qcom,qrd";
qcom,board-id = <0x1000B 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "ravelin-qrd.dtsi"

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "ravelinp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. RavelinP SoC";
compatible = "qcom,ravelinp";
qcom,board-id = <0 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "ravelin.dtsi"
/ {
model = "Qualcomm Technologies, Inc. RavelinP";
compatible = "qcom,ravelinp";
qcom,msm-id = <602 0x10000>;
};