ARM: dts: qcom: Add PMIC die temp alarm, socd, bcl support for Tuna

Add PMIC die temp mitigation, socd mitigation, bcl support for
tuna.

Change-Id: I5d6fc37c0b9f4e137510abb1ee4aa3b47cae6005
Signed-off-by: Nitesh Kumar <quic_nitekuma@quicinc.com>

qcom/pm7550ba.dtsi

@@ -156,7 +156,7 @@
 			pm7550ba_trip1: trip1 {
 				temperature = <115000>;
 				hysteresis = <0>;
-				type = "critical";
+				type = "hot";
 			};
 
 			pm7550ba_trip2: trip2 {
@@ -196,7 +196,7 @@
 	};
 
 	pm7550ba-bcl-lvl0 {
-		polling-delay-passive = <100>;
+		polling-delay-passive = <50>;
 		polling-delay = <0>;
 		thermal-sensors = <&pm7550ba_bcl 5>;
 
@@ -222,7 +222,7 @@
 	};
 
 	pm7550ba-bcl-lvl1 {
-		polling-delay-passive = <100>;
+		polling-delay-passive = <50>;
 		polling-delay = <0>;
 		thermal-sensors = <&pm7550ba_bcl 6>;
 
@@ -248,7 +248,7 @@
 	};
 
 	pm7550ba-bcl-lvl2 {
-		polling-delay-passive = <100>;
+		polling-delay-passive = <50>;
 		polling-delay = <0>;
 		thermal-sensors = <&pm7550ba_bcl 7>;
 

qcom/pmk8550.dtsi

@@ -30,6 +30,11 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
+			sm1510_present: sm1510_present@5d {
+				reg = <0x5d 0x1>;
+				bits = <5 5>;
+			};
+
 			ocp_log: ocp-log@76 {
 				reg = <0x76 0x6>;
 			};

qcom/tuna-mtp.dtsi

@@ -4,6 +4,8 @@
  */
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/qcom,gcc-sun.h>
+#include "tuna-thermal-overlay.dtsi"
 
 &qupv3_se4_i2c {
 	#address-cells = <1>;

qcom/tuna-pm7550ba.dtsi

@@ -224,3 +224,38 @@
 		};
 	};
 };
+
+&pm7550ba_bcl {
+	nvmem-cells = <&sm1510_present>;
+	nvmem-cell-names = "sm1510_present";
+};
+
+&thermal_zones {
+	pm7550ba-2s-ibat-lvl0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pm7550ba_bcl 8>;
+
+		trips {
+			ibat_2s_lvl0: ibat-2s-lvl0 {
+				temperature = <5000>;
+				hysteresis = <200>;
+				type = "passive";
+			};
+		};
+	};
+
+	pm7550ba-2s-ibat-lvl1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pm7550ba_bcl 9>;
+
+		trips {
+			ibat_2s_lvl1: ibat-2s-lvl1 {
+				temperature = <7000>;
+				hysteresis = <200>;
+				type = "passive";
+			};
+		};
+	};
+};

qcom/tuna-pmic-overlay.dtsi

@@ -124,7 +124,7 @@
 
 &thermal_zones {
 	sys-therm-0 {
-		polling-delay-passive = <0>;
+		polling-delay-passive = <5000>;
 		polling-delay = <0>;
 		thermal-sensors = <&pmk8550_vadc PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU>;
 		trips {
@@ -139,6 +139,48 @@
 				hysteresis = <1000>;
 				type = "passive";
 			};
+
+			trip_config0: trip-config0 {
+				temperature = <78000>;
+				hysteresis = <8000>;
+				type = "passive";
+			};
+
+			trip_config1: trip-config1 {
+				temperature = <80000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+
+			display_test_config1: display-test-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			display_test_config2: display-test-config2 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			display_test_config3: display-test-config3 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			display_test_config4: display-test-config4 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			display_test_config5: display-test-config5 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
 		};
 	};
 

qcom/tuna-qrd.dtsi

@@ -4,6 +4,7 @@
  */
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include "tuna-thermal-overlay.dtsi"
 
 &qupv3_se4_spi {
 	#address-cells = <1>;

qcom/tuna-thermal-overlay.dtsi

@@ -0,0 +1,252 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/thermal/thermal_qti.h>
+
+&thermal_zones {
+	socd {
+		cooling-maps {
+			socd_apc1 {
+				trip = <&socd_trip>;
+				cooling-device = <&APC1_MX_CX_PAUSE 1 1>;
+			};
+
+			socd_cdsp1 {
+				trip = <&socd_trip>;
+				cooling-device = <&cdsp_sw 4 4>;
+			};
+
+			socd_gpu0 {
+				trip = <&socd_trip>;
+				cooling-device = <&msm_gpu 4 4>;
+			};
+		};
+	};
+
+	pmih010x-bcl-lvl0 {
+		cooling-maps {
+			lbat_modem0 {
+				trip = <&b_bcl_lvl0>;
+				cooling-device = <&modem_bcl 1 1>;
+			};
+
+			lbat_gpu0 {
+				trip = <&b_bcl_lvl0>;
+				cooling-device = <&msm_gpu 1 1>;
+			};
+		};
+	};
+
+	pmih010x-bcl-lvl1 {
+		cooling-maps {
+			lbat_modem1 {
+				trip = <&b_bcl_lvl1>;
+				cooling-device = <&modem_bcl 2 2>;
+			};
+
+			lbat_gpu1 {
+				trip = <&b_bcl_lvl1>;
+				cooling-device = <&msm_gpu 2 2>;
+			};
+		};
+	};
+
+	pmih010x-bcl-lvl2 {
+		cooling-maps {
+			lbat_gpu2 {
+				trip = <&b_bcl_lvl2>;
+				cooling-device = <&msm_gpu 3 3>;
+			};
+		};
+	};
+
+	pm7550ba-bcl-lvl0 {
+		cooling-maps {
+			vph_0_nr_scg {
+				trip = <&bcl_lvl0>;
+				cooling-device = <&modem_nr_scg_dsc 3 3>;
+			};
+
+			vph_0_nr {
+				trip = <&bcl_lvl0>;
+				cooling-device = <&modem_nr_dsc 6 6>;
+			};
+
+			vph_0_mdm_lte {
+				trip = <&bcl_lvl0>;
+				cooling-device = <&modem_lte_dsc 8 8>;
+			};
+
+			vph_gpu0 {
+				trip = <&bcl_lvl0>;
+				cooling-device = <&msm_gpu 2 2>;
+			};
+		};
+	};
+
+	pm7550ba-bcl-lvl1 {
+		cooling-maps {
+			vph_1_nr_scg {
+				trip = <&bcl_lvl1>;
+				cooling-device = <&modem_nr_scg_dsc 10 10>;
+			};
+
+			vph_1_nr {
+				trip = <&bcl_lvl1>;
+				cooling-device = <&modem_nr_dsc 9 9>;
+			};
+
+			vph_1_mdm_lte {
+				trip = <&bcl_lvl1>;
+				cooling-device = <&modem_lte_dsc 10 10>;
+			};
+
+			vph_gpu1 {
+				trip = <&bcl_lvl1>;
+				cooling-device = <&msm_gpu 3 3>;
+			};
+		};
+	};
+
+	pm7550ba-bcl-lvl2 {
+		cooling-maps {
+			vph_gpu2 {
+				trip = <&bcl_lvl2>;
+				cooling-device = <&msm_gpu 7 7>;
+			};
+		};
+	};
+
+	pmxr2230-bcl-lvl0 {
+		cooling-maps {
+			lbat_0_nr_scg {
+				trip = <&bcl_lvl0>;
+				cooling-device = <&modem_nr_scg_dsc 3 3>;
+			};
+
+			lbat_0_nr {
+				trip = <&bcl_lvl0>;
+				cooling-device = <&modem_nr_dsc 6 6>;
+			};
+
+			lbat_0_mdm_lte {
+				trip = <&bcl_lvl0>;
+				cooling-device = <&modem_lte_dsc 8 8>;
+			};
+
+			lbat_gpu0 {
+				trip = <&bcl_lvl0>;
+				cooling-device = <&msm_gpu 2 2>;
+			};
+		};
+	};
+
+	pmxr2230-bcl-lvl1 {
+		cooling-maps {
+			lbat_1_nr_scg {
+				trip = <&bcl_lvl1>;
+				cooling-device = <&modem_nr_scg_dsc 10 10>;
+			};
+
+			lbat_1_nr {
+				trip = <&bcl_lvl1>;
+				cooling-device = <&modem_nr_dsc 9 9>;
+			};
+
+			lbat_1_mdm_lte {
+				trip = <&bcl_lvl1>;
+				cooling-device = <&modem_lte_dsc 10 10>;
+			};
+
+			lbat_gpu1 {
+				trip = <&bcl_lvl1>;
+				cooling-device = <&msm_gpu 3 3>;
+			};
+		};
+	};
+
+	pmxr2230-bcl-lvl2 {
+		cooling-maps {
+			lbat_gpu2 {
+				trip = <&bcl_lvl2>;
+				cooling-device = <&msm_gpu 7 7>;
+			};
+		};
+	};
+
+	sys-therm-0 {
+		cooling-maps {
+			apc1_cdev {
+				trip = <&trip_config0>;
+				cooling-device = <&APC1_MX_CX_PAUSE 1 1>;
+			};
+
+			apc0_cdev {
+				trip = <&trip_config0>;
+				cooling-device = <&APC0_MX_CX_PAUSE 1 1>;
+			};
+
+			cdsp_cdev {
+				trip = <&trip_config0>;
+				cooling-device = <&cdsp_sw 5 THERMAL_NO_LIMIT>;
+			};
+
+			gpu_cdev {
+				trip = <&trip_config0>;
+				cooling-device = <&msm_gpu 5 THERMAL_NO_LIMIT>;
+			};
+
+			cpu3_hot_cdev {
+				trip = <&trip_config1>;
+				cooling-device = <&cpu3_hotplug 1 1>;
+			};
+
+			cpu4_hot_cdev {
+				trip = <&trip_config1>;
+				cooling-device = <&cpu4_hotplug 1 1>;
+			};
+
+			cpu5_hot_cdev {
+				trip = <&trip_config1>;
+				cooling-device = <&cpu5_hotplug 1 1>;
+			};
+
+			cpu6_hot_cdev {
+				trip = <&trip_config1>;
+				cooling-device = <&cpu6_hotplug 1 1>;
+			};
+
+			cpu7_hot_cdev {
+				trip = <&trip_config1>;
+				cooling-device = <&cpu7_hotplug 1 1>;
+			};
+
+			lte_cdev {
+				trip = <&trip_config1>;
+				cooling-device = <&modem_lte_dsc 255 255>;
+			};
+
+			nr_cdev {
+				trip = <&trip_config1>;
+				cooling-device = <&modem_nr_scg_dsc 255 255>;
+			};
+
+			display_cdev1 {
+				trip = <&display_test_config1>;
+				cooling-device = <&display_fps 1 1>;
+			};
+
+			display_cdev2 {
+				trip = <&display_test_config2>;
+				cooling-device = <&display_fps 2 2>;
+			};
+
+			display_cdev3 {
+				trip = <&display_test_config3>;
+				cooling-device = <&display_fps 3 3>;
+			};
+		};
+	};
+};

qcom/tuna-thermal.dtsi

@@ -5,6 +5,10 @@
 
 #include <dt-bindings/thermal/thermal_qti.h>
 
+&msm_gpu {
+	#cooling-cells = <2>;
+};
+
 &soc {
 	tsens0: tsens0@c228000 {
 		compatible = "qcom,tsens-v2";
@@ -207,6 +211,11 @@
 		};
 	};
 
+	qcom,devfreq-cdev {
+		compatible = "qcom,devfreq-cdev";
+		qcom,devfreq = <&msm_gpu>;
+	};
+
 	qcom,cpufreq-cdev {
 		compatible = "qcom,cpufreq-cdev";
 
@@ -236,16 +245,6 @@
 				#cooling-cells = <2>;
 			};
 
-			cdsp_sw_hvx: cdsp_sw_hvx {
-				qcom,qmi-dev-name = "cdsp_sw_hvx";
-				#cooling-cells = <2>;
-			};
-
-			cdsp_sw_hmx: cdsp_sw_hmx {
-				qcom,qmi-dev-name = "cdsp_sw_hmx";
-				#cooling-cells = <2>;
-			};
-
 			cdsp_hw: cdsp_hw {
 				qcom,qmi-dev-name = "cdsp_hw";
 				#cooling-cells = <2>;
@@ -1241,6 +1240,13 @@
 				type = "hot";
 			};
 		};
+
+		cooling-maps {
+			gpu0_cdev {
+				trip = <&gpu0_tj_cfg>;
+				cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>;
+			};
+		};
 	};
 
 	gpu-1 {
@@ -1273,6 +1279,13 @@
 				type = "hot";
 			};
 		};
+
+		cooling-maps {
+			gpu1_cdev {
+				trip = <&gpu1_tj_cfg>;
+				cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>;
+			};
+		};
 	};
 
 	gpu-2 {
@@ -1305,6 +1318,13 @@
 				type = "hot";
 			};
 		};
+
+		cooling-maps {
+			gpu2_cdev {
+				trip = <&gpu2_tj_cfg>;
+				cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>;
+			};
+		};
 	};
 
 	gpu-3 {
@@ -1337,6 +1357,13 @@
 				type = "hot";
 			};
 		};
+
+		cooling-maps {
+			gpu3_cdev {
+				trip = <&gpu3_tj_cfg>;
+				cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>;
+			};
+		};
 	};
 
 	gpu-4 {
@@ -1369,6 +1396,13 @@
 				type = "hot";
 			};
 		};
+
+		cooling-maps {
+			gpu4_cdev {
+				trip = <&gpu4_tj_cfg>;
+				cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>;
+			};
+		};
 	};
 
 	gpu-5 {
@@ -1401,6 +1435,13 @@
 				type = "hot";
 			};
 		};
+
+		cooling-maps {
+			gpu5_cdev {
+				trip = <&gpu5_tj_cfg>;
+				cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>;
+			};
+		};
 	};
 
 	nsphvx-0 {