ARM: dts: msm: Add LLCC node for sdxkova SoC
Add LLCC node for sdxkova to enable last level cache controller. Change-Id: Ief1651c1bb72a4c8f170b2fc40e9879ab4781b3d Signed-off-by: Sayan Dey <quic_sayand@quicinc.com>
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@@ -398,6 +398,14 @@
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#interrupt-cells = <3>;
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#mbox-cells = <2>;
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};
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llcc_device: cache-controller@19200000 {
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compatible = "qcom,sdxpinn-llcc";
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reg = <0x0 0x19200000 0x0 0x200000>;
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reg-names = "llcc0_base";
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interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
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cap-based-alloc-and-pwr-collapse;
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};
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};
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&gcc {
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