From 160a80d44a5ba8c00e7c726495dc71ae7e79fb70 Mon Sep 17 00:00:00 2001
From: Sayan Dey <quic_sayand@quicinc.com>
Date: Mon, 5 Aug 2024 12:39:46 +0530
Subject: [PATCH] ARM: dts: msm: Add LLCC node for sdxkova SoC

Add LLCC node for sdxkova to enable last level cache controller.

Change-Id: Ief1651c1bb72a4c8f170b2fc40e9879ab4781b3d
Signed-off-by: Sayan Dey <quic_sayand@quicinc.com>
---
 qcom/sdxkova.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/qcom/sdxkova.dtsi b/qcom/sdxkova.dtsi
index 4f44f0c2..a78a5def 100644
--- a/qcom/sdxkova.dtsi
+++ b/qcom/sdxkova.dtsi
@@ -398,6 +398,14 @@
 		#interrupt-cells = <3>;
 		#mbox-cells = <2>;
 	};
+
+	llcc_device: cache-controller@19200000 {
+		compatible = "qcom,sdxpinn-llcc";
+		reg = <0x0 0x19200000 0x0 0x200000>;
+		reg-names = "llcc0_base";
+		interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
+		cap-based-alloc-and-pwr-collapse;
+	};
 };
 
 &gcc {