ARM: dts: msm: Add LLCC node for sdxkova SoC

Add LLCC node for sdxkova to enable last level cache controller.

Change-Id: Ief1651c1bb72a4c8f170b2fc40e9879ab4781b3d
Signed-off-by: Sayan Dey <quic_sayand@quicinc.com>
This commit is contained in:
Sayan Dey
2024-08-05 12:39:46 +05:30
parent cc13f7536b
commit 160a80d44a

View File

@@ -398,6 +398,14 @@
#interrupt-cells = <3>; #interrupt-cells = <3>;
#mbox-cells = <2>; #mbox-cells = <2>;
}; };
llcc_device: cache-controller@19200000 {
compatible = "qcom,sdxpinn-llcc";
reg = <0x0 0x19200000 0x0 0x200000>;
reg-names = "llcc0_base";
interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
cap-based-alloc-and-pwr-collapse;
};
}; };
&gcc { &gcc {