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ARM: dts: qcom: Add cooling-cells for cpu in monaco

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Add cooling-cells for the CPU sensors in monaco.

Change-Id: I6ef6acac51952effd6de820b6384401feeb610b4
Signed-off-by: Nitesh Kumar <quic_nitekuma@quicinc.com>
This commit is contained in:
Nitesh Kumar
2024-10-11 16:55:17 +05:30
parent 3c86c8cc2a
commit 1402955d21
1 changed files with 3 additions and 0 deletions
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3
qcom/monaco.dtsi
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@@ -84,6 +84,7 @@
qcom,freq-domain = <&cpufreq_hw 0>; qcom,freq-domain = <&cpufreq_hw 0>;
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
qcom,lmh-dcvs = <&lmh_dcvs0>; qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L1_I_1: l1-icache { L1_I_1: l1-icache {
compatible = "cache"; compatible = "cache";
@@ -109,6 +110,7 @@
qcom,freq-domain = <&cpufreq_hw 0>; qcom,freq-domain = <&cpufreq_hw 0>;
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
qcom,lmh-dcvs = <&lmh_dcvs0>; qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L1_I_2: l1-icache { L1_I_2: l1-icache {
compatible = "cache"; compatible = "cache";
@@ -134,6 +136,7 @@
qcom,freq-domain = <&cpufreq_hw 0>; qcom,freq-domain = <&cpufreq_hw 0>;
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
qcom,lmh-dcvs = <&lmh_dcvs0>; qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L1_I_3: l1-icache { L1_I_3: l1-icache {
compatible = "cache"; compatible = "cache";