Merge d279e8fa55 on remote branch

Change-Id: I45fa07a1785a4ccd339eb754a0c362825ecb0ced

bindings/adreno-gmu.txt

@@ -66,6 +66,7 @@ GMU GDSC/regulators:
 			baseAddr - base address of the IPC region
 			size     - size of the IPC region
 
+- qcom,soccp-controller: Phandle of the soccp controller
 
 Example:
 

gpu/sun-gpu-pwrlevels.dtsi

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: BSD-3-Clause
 /*
- * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 &msm_gpu {
@@ -15,6 +15,136 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 
+			qcom,initial-pwrlevel = <10>;
+			qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_AB)
+					SKU_CODE(PCODE_UNKNOWN, FC_AC)>;
+
+			/* NOM_L1 */
+			qcom,gpu-pwrlevel@0 {
+				reg = <0>;
+				qcom,gpu-freq = <900000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+
+				qcom,bus-freq = <11>;
+				qcom,bus-min = <11>;
+				qcom,bus-max = <11>;
+			};
+
+			/* NOM */
+			qcom,gpu-pwrlevel@1 {
+				reg = <1>;
+				qcom,gpu-freq = <832000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
+
+				qcom,bus-freq = <10>;
+				qcom,bus-min = <7>;
+				qcom,bus-max = <10>;
+			};
+
+			/* SVS_L2 */
+			qcom,gpu-pwrlevel@2 {
+				reg = <2>;
+				qcom,gpu-freq = <779000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+
+				qcom,bus-freq = <9>;
+				qcom,bus-min = <7>;
+				qcom,bus-max = <10>;
+			};
+
+			/* SVS_L1 */
+			qcom,gpu-pwrlevel@3 {
+				reg = <3>;
+				qcom,gpu-freq = <734000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+
+				qcom,bus-freq = <8>;
+				qcom,bus-min = <6>;
+				qcom,bus-max = <10>;
+			};
+
+			/* SVS_L0 */
+			qcom,gpu-pwrlevel@4 {
+				reg = <4>;
+				qcom,gpu-freq = <660000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
+
+				qcom,bus-freq = <6>;
+				qcom,bus-min = <4>;
+				qcom,bus-max = <7>;
+			};
+
+			/* SVS */
+			qcom,gpu-pwrlevel@5 {
+				reg = <5>;
+				qcom,gpu-freq = <607000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
+
+				qcom,bus-freq = <6>;
+				qcom,bus-min = <4>;
+				qcom,bus-max = <7>;
+			};
+
+			/* Low_SVS_L1 */
+			qcom,gpu-pwrlevel@6 {
+				reg = <6>;
+				qcom,gpu-freq = <525000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
+
+				qcom,bus-freq = <4>;
+				qcom,bus-min = <2>;
+				qcom,bus-max = <6>;
+			};
+
+			/* Low_SVS */
+			qcom,gpu-pwrlevel@7 {
+				reg = <7>;
+				qcom,gpu-freq = <443000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+
+				qcom,bus-freq = <4>;
+				qcom,bus-min = <2>;
+				qcom,bus-max = <6>;
+			};
+
+			/* Low_SVS_D0 */
+			qcom,gpu-pwrlevel@8 {
+				reg = <8>;
+				qcom,gpu-freq = <389000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
+
+				qcom,bus-freq = <4>;
+				qcom,bus-min = <2>;
+				qcom,bus-max = <6>;
+			};
+
+			/* Low_SVS_D1 */
+			qcom,gpu-pwrlevel@9 {
+				reg = <9>;
+				qcom,gpu-freq = <342000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+
+				qcom,bus-freq = <3>;
+				qcom,bus-min = <2>;
+				qcom,bus-max = <6>;
+			};
+
+			/* Low_SVS_D2 */
+			qcom,gpu-pwrlevel@10 {
+				reg = <10>;
+				qcom,gpu-freq = <222000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
+
+				qcom,bus-freq = <3>;
+				qcom,bus-min = <2>;
+				qcom,bus-max = <3>;
+			};
+		};
+
+		qcom,gpu-pwrlevels-1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
 			qcom,initial-pwrlevel = <11>;
 			qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_UNKNOWN)>;
 

gpu/sun-gpu.dts

@@ -21,6 +21,6 @@
 / {
 	model = "Qualcomm Technologies, Inc. sun";
 	compatible = "qcom,sun";
-	qcom,msm-id = <618 0x10000>;
+	qcom,msm-id = <618 0x10000>, <639 0x10000>;
 	qcom,board-id = <0 0>;
 };

gpu/sun-gpu.dtsi

@@ -1,15 +1,31 @@
 // SPDX-License-Identifier: BSD-3-Clause
 /*
- * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
 
 /* External feature codes */
 #define FC_UNKNOWN 0x0
+#define FC_AA 0x1
+#define FC_AB 0x2
+#define FC_AC 0x3
+#define FC_AD 0x4
+
+/* Internal feature codes */
+#define FC_Y0 0x00f1
+#define FC_Y1 0x00f2
 
 /* Pcodes */
 #define PCODE_UNKNOWN 0
+#define PCODE_0 1
+#define PCODE_1 2
+#define PCODE_2 3
+#define PCODE_3 4
+#define PCODE_4 5
+#define PCODE_5 6
+#define PCODE_6 7
+#define PCODE_7 8
 
 #define SKU_CODE(pcode, featurecode) ((pcode << 16) + featurecode)
 
@@ -23,8 +39,8 @@
 	reg-names = "kgsl_3d0_reg_memory", "rscc", "cx_dbgc", "cx_misc",
 		"qdss_gfx", "qdss_etr", "qdss_tmc";
 
-	interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
+	interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>, <0 80 IRQ_TYPE_LEVEL_HIGH>;
-	interrupt-names = "kgsl_3d0_irq";
+	interrupt-names = "kgsl_3d0_irq", "cx_host_irq";
 
 	clocks = <&gcc GCC_GPU_GEMNOC_GFX_CLK>,
 		<&gpucc GPU_CC_AHB_CLK>,
@@ -145,10 +161,9 @@
 		compatible = "qcom,gen8-gmu";
 
 		reg = <0x3d37000 0x68000>,
-		      <0xb5d0000 0x24000>,
 		      <0x3d40000 0x10000>;
 
-		reg-names = "gmu", "gmu_pdc", "gmu_ao_blk_dec0";
+		reg-names = "gmu", "gmu_ao_blk_dec0";
 
 		interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
 			<0 305 IRQ_TYPE_LEVEL_HIGH>;
@@ -171,11 +186,12 @@
 
 		qcom,gmu-freq-table = <500000000 RPMH_REGULATOR_LEVEL_LOW_SVS>,
 					<650000000 RPMH_REGULATOR_LEVEL_SVS>;
-		qcom,gmu-perf-ddr-bw = <MHZ_TO_KBPS(1353, 4)>;
+		qcom,gmu-perf-ddr-bw = <MHZ_TO_KBPS(1555, 4)>;
 
 		iommus = <&kgsl_smmu 0x5 0x000>;
 		qcom,iommu-dma = "disabled";
 
 		qcom,ipc-core = <0x00400000 0x140000>;
+		qcom,soccp-controller = <&soccp_pas>;
 	};
 };