From 87ec4506c6e933834918d21aee907b696c2a6653 Mon Sep 17 00:00:00 2001 From: Carter Cooper Date: Mon, 18 Dec 2023 10:05:57 -0700 Subject: [PATCH 1/7] ARM: dts: msm: Add sunp msm-id support for GPU Add support for sunp variant msm-id. Change-Id: I3dee70f03e360330636290ef665aced0b4f31542 Signed-off-by: Carter Cooper Signed-off-by: Hareesh Gundu --- gpu/sun-gpu.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gpu/sun-gpu.dts b/gpu/sun-gpu.dts index 98f76718..eda85863 100644 --- a/gpu/sun-gpu.dts +++ b/gpu/sun-gpu.dts @@ -21,6 +21,6 @@ / { model = "Qualcomm Technologies, Inc. sun"; compatible = "qcom,sun"; - qcom,msm-id = <618 0x10000>; + qcom,msm-id = <618 0x10000>, <639 0x10000>; qcom,board-id = <0 0>; }; From 0d12082da370c5a504bc76ffbbbfeabcc1d7a221 Mon Sep 17 00:00:00 2001 From: Kamal Agrawal Date: Fri, 15 Dec 2023 12:57:16 +0530 Subject: [PATCH 2/7] ARM: dts: msm: Remove gmu_pdc register for sun GPU KGSL driver doesn't program PDC registers anymore. Thus, remove the register information from device tree for sun GPU. Change-Id: I60c78e00942bb68e311b4c4632e5a3e2ed30dcd6 Signed-off-by: Kamal Agrawal --- gpu/sun-gpu.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/gpu/sun-gpu.dtsi b/gpu/sun-gpu.dtsi index 46db9ce5..9672d772 100644 --- a/gpu/sun-gpu.dtsi +++ b/gpu/sun-gpu.dtsi @@ -145,10 +145,9 @@ compatible = "qcom,gen8-gmu"; reg = <0x3d37000 0x68000>, - <0xb5d0000 0x24000>, <0x3d40000 0x10000>; - reg-names = "gmu", "gmu_pdc", "gmu_ao_blk_dec0"; + reg-names = "gmu", "gmu_ao_blk_dec0"; interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>, <0 305 IRQ_TYPE_LEVEL_HIGH>; From 88a17ffa07b25e06184a0011b4b41fac4b7a070f Mon Sep 17 00:00:00 2001 From: Harshdeep Dhatt Date: Fri, 5 Jan 2024 15:58:06 -0700 Subject: [PATCH 3/7] dt-bindings: Add soccp controller property This is needed to vote for soccp boot/slumber sequence for hardware fence feature. Change-Id: I169d83ed9d5acf66027194bf5fee0825bb5602d2 Signed-off-by: Harshdeep Dhatt --- bindings/adreno-gmu.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/adreno-gmu.txt b/bindings/adreno-gmu.txt index a5544793..08173ede 100644 --- a/bindings/adreno-gmu.txt +++ b/bindings/adreno-gmu.txt @@ -66,6 +66,7 @@ GMU GDSC/regulators: baseAddr - base address of the IPC region size - size of the IPC region +- qcom,soccp-controller: Phandle of the soccp controller Example: From 65f3e20c5fc25d88740f398962aaa322dd5ee725 Mon Sep 17 00:00:00 2001 From: Harshdeep Dhatt Date: Fri, 5 Jan 2024 15:59:46 -0700 Subject: [PATCH 4/7] ARM: dts: msm: Add soccp controller phandle for sun Hardware fence feature requires that we keep soccp from power collapsing as long as GMU is active. Change-Id: I3721aefd8cb34edfeba846115132002defa8f385 Signed-off-by: Harshdeep Dhatt --- gpu/sun-gpu.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/gpu/sun-gpu.dtsi b/gpu/sun-gpu.dtsi index 46db9ce5..4d34e4e4 100644 --- a/gpu/sun-gpu.dtsi +++ b/gpu/sun-gpu.dtsi @@ -177,5 +177,6 @@ qcom,iommu-dma = "disabled"; qcom,ipc-core = <0x00400000 0x140000>; + qcom,soccp-controller = <&soccp_pas>; }; }; From f535a812cb347c800d19c579c4167ff95e017a2b Mon Sep 17 00:00:00 2001 From: Kamal Agrawal Date: Mon, 11 Dec 2023 23:48:09 +0530 Subject: [PATCH 5/7] ARM: dts: msm: Add CX host interrupt for sun GPU For gen8 targets, frequency limiter violations are published through cx_host_irq interrupt. Thus, add cx_host_irq for sun GPU. Change-Id: Ie7e0c7fc53bdc002261ee05339c3e4c49da83ea0 Signed-off-by: Kamal Agrawal --- gpu/sun-gpu.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gpu/sun-gpu.dtsi b/gpu/sun-gpu.dtsi index 46db9ce5..04c9ab4c 100644 --- a/gpu/sun-gpu.dtsi +++ b/gpu/sun-gpu.dtsi @@ -23,8 +23,8 @@ reg-names = "kgsl_3d0_reg_memory", "rscc", "cx_dbgc", "cx_misc", "qdss_gfx", "qdss_etr", "qdss_tmc"; - interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "kgsl_3d0_irq"; + interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>, <0 80 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq", "cx_host_irq"; clocks = <&gcc GCC_GPU_GEMNOC_GFX_CLK>, <&gpucc GPU_CC_AHB_CLK>, From 40c568a6d182095de26452c239be8bf3b0c88aea Mon Sep 17 00:00:00 2001 From: Kamal Agrawal Date: Sat, 3 Feb 2024 16:22:37 +0530 Subject: [PATCH 6/7] ARM: dts: msm: Update DDR bandwidth for sun GMU scaling SVS is the highest voltage corner for GMU. The lowest DDR BW that puts CX at SVS corner is 1555 MHz. This DDR vote puts CX at a corner high enough such that GMU can run at 650 MHz. This is to get better GMU performance at no extra power cost. Change-Id: I919476577e9b2e69161142c93d47e91505ffc222 Signed-off-by: Kamal Agrawal --- gpu/sun-gpu.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gpu/sun-gpu.dtsi b/gpu/sun-gpu.dtsi index 46db9ce5..9d7d3cb1 100644 --- a/gpu/sun-gpu.dtsi +++ b/gpu/sun-gpu.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024)) @@ -171,7 +171,7 @@ qcom,gmu-freq-table = <500000000 RPMH_REGULATOR_LEVEL_LOW_SVS>, <650000000 RPMH_REGULATOR_LEVEL_SVS>; - qcom,gmu-perf-ddr-bw = ; + qcom,gmu-perf-ddr-bw = ; iommus = <&kgsl_smmu 0x5 0x000>; qcom,iommu-dma = "disabled"; From a17c326b0edba92fa3690da7ef45a13e1b7cfe5b Mon Sep 17 00:00:00 2001 From: Mohammed Mirza Mandayappurath Manzoor Date: Fri, 19 Jan 2024 16:03:19 -0800 Subject: [PATCH 7/7] ARM: dts: msm: Add powerlevels for AB and AC sku for sun gpu Add supporting power levels for AB and AC sku devices. Change-Id: I233a5779a78cdc22883e1ed8b9b02c73aa0f576d Signed-off-by: Mohammed Mirza Mandayappurath Manzoor --- gpu/sun-gpu-pwrlevels.dtsi | 132 ++++++++++++++++++++++++++++++++++++- gpu/sun-gpu.dtsi | 18 ++++- 2 files changed, 148 insertions(+), 2 deletions(-) diff --git a/gpu/sun-gpu-pwrlevels.dtsi b/gpu/sun-gpu-pwrlevels.dtsi index 77be73e5..9592390c 100644 --- a/gpu/sun-gpu-pwrlevels.dtsi +++ b/gpu/sun-gpu-pwrlevels.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ &msm_gpu { @@ -15,6 +15,136 @@ #address-cells = <1>; #size-cells = <0>; + qcom,initial-pwrlevel = <10>; + qcom,sku-codes = ; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <900000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <832000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <779000000>; + qcom,level = ; + + qcom,bus-freq = <9>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <734000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <6>; + qcom,bus-max = <10>; + }; + + /* SVS_L0 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <660000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <607000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + }; + + /* Low_SVS_L1 */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <525000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + }; + + /* Low_SVS_D0 */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <389000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <342000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + }; + + /* Low_SVS_D2 */ + qcom,gpu-pwrlevel@10 { + reg = <10>; + qcom,gpu-freq = <222000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <3>; + }; + }; + + qcom,gpu-pwrlevels-1 { + #address-cells = <1>; + #size-cells = <0>; + qcom,initial-pwrlevel = <11>; qcom,sku-codes = ; diff --git a/gpu/sun-gpu.dtsi b/gpu/sun-gpu.dtsi index 46db9ce5..a1a75788 100644 --- a/gpu/sun-gpu.dtsi +++ b/gpu/sun-gpu.dtsi @@ -1,15 +1,31 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024)) /* External feature codes */ #define FC_UNKNOWN 0x0 +#define FC_AA 0x1 +#define FC_AB 0x2 +#define FC_AC 0x3 +#define FC_AD 0x4 + +/* Internal feature codes */ +#define FC_Y0 0x00f1 +#define FC_Y1 0x00f2 /* Pcodes */ #define PCODE_UNKNOWN 0 +#define PCODE_0 1 +#define PCODE_1 2 +#define PCODE_2 3 +#define PCODE_3 4 +#define PCODE_4 5 +#define PCODE_5 6 +#define PCODE_6 7 +#define PCODE_7 8 #define SKU_CODE(pcode, featurecode) ((pcode << 16) + featurecode)