Merge "ARM: dts: msm: Add spi, i2c, gpi nodes for SVM tuna"
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Gerrit - the friendly Code Review server
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0a06c817f5
@@ -47,7 +47,8 @@
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<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
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qcom,gpii-mask = <0x1f>;
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qcom,static-gpii-mask = <0x1>;
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qcom,gpii-mask = <0x1e>;
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qcom,ev-factor = <1>;
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memory-region = <&qup1_gpi_iommu_region>;
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qcom,gpi-ee-offset = <0x10000>;
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@@ -255,8 +256,8 @@
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se4_i2c_sda_active>, <&qupv3_se4_i2c_scl_active>;
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pinctrl-1 = <&qupv3_se4_i2c_sleep>;
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dmas = <&gpi_dma1 0 4 3 64 0>,
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<&gpi_dma1 1 4 3 64 0>;
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dmas = <&gpi_dma1 0 4 3 64 2>,
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<&gpi_dma1 1 4 3 64 2>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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@@ -279,8 +280,8 @@
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pinctrl-0 = <&qupv3_se4_spi_mosi_active>, <&qupv3_se4_spi_miso_active>,
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<&qupv3_se4_spi_clk_active>, <&qupv3_se4_spi_cs_active>;
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pinctrl-1 = <&qupv3_se4_spi_sleep>;
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dmas = <&gpi_dma1 0 4 1 64 0>,
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<&gpi_dma1 1 4 1 64 0>;
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dmas = <&gpi_dma1 0 4 1 64 2>,
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<&gpi_dma1 1 4 1 64 2>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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status = "disabled";
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@@ -419,7 +420,8 @@
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<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
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qcom,gpii-mask = <0x1f>;
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qcom,static-gpii-mask = <0x1>;
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qcom,gpii-mask = <0x1e>;
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qcom,ev-factor = <1>;
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memory-region = <&qup2_gpi_iommu_region>;
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qcom,gpi-ee-offset = <0x10000>;
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@@ -749,8 +751,8 @@
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se15_i2c_sda_active>, <&qupv3_se15_i2c_scl_active>;
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pinctrl-1 = <&qupv3_se15_i2c_sleep>;
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dmas = <&gpi_dma2 0 7 3 64 0>,
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<&gpi_dma2 1 7 3 64 0>;
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dmas = <&gpi_dma2 0 7 3 64 2>,
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<&gpi_dma2 1 7 3 64 2>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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@@ -773,8 +775,8 @@
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pinctrl-0 = <&qupv3_se15_spi_mosi_active>, <&qupv3_se15_spi_miso_active>,
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<&qupv3_se15_spi_clk_active>, <&qupv3_se15_spi_cs_active>;
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pinctrl-1 = <&qupv3_se15_spi_sleep>;
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dmas = <&gpi_dma2 0 7 1 64 0>,
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<&gpi_dma2 1 7 1 64 0>;
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dmas = <&gpi_dma2 0 7 1 64 2>,
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<&gpi_dma2 1 7 1 64 2>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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status = "disabled";
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@@ -71,6 +71,9 @@
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vm-attrs = "context-dump", "crash-restart";
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iomemory-ranges = <0x0 0xa24000 0x0 0xa24000 0x0 0x4000 0x0
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0x0 0x824000 0x0 0x824000 0x0 0x4000 0x0>;
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/* For LEVM por usecases is QUP1_SE4 and QUP2_SE7.
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* QUP1_SE4: GPII5 : IRQ_316
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* QUP2_SE7: GPII5 : IRQ_625
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@@ -362,6 +365,165 @@
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qcom,block-size = <0x400000>;
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qcom,initial-movable-zone-size = <0x2000000>;
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};
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/*
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* QUP1 : SE4 - Primary touch
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* QUP2 : SE7 - Secondary touch
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*/
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qup_iommu_group: qup_common_iommu_group {
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iommu-addresses = <&gpi_dma1 0x00000000 0x00020000>,
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<&qupv3_1 0x00000000 0x00020000>,
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<&gpi_dma2 0x00000000 0x00020000>,
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<&qupv3_2 0x00000000 0x00020000>;
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};
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/* QUPv3_1 GPI Instance */
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gpi_dma1: qcom,gpi-dma@a00000 {
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compatible = "qcom,gpi-dma";
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#dma-cells = <5>;
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reg = <0xa00000 0x60000>;
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reg-names = "gpi-top";
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iommus = <&apps_smmu 0xb8 0x0>;
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qcom,iommu-group = <&qup_iommu_group>;
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dma-coherent;
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interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
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qcom,max-num-gpii = <12>;
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qcom,static-gpii-mask = <0x20>;
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qcom,gpii-mask = <0x0>;
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qcom,ev-factor = <1>;
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qcom,gpi-ee-offset = <0x10000>;
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qcom,le-vm;
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status = "ok";
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};
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/* QUPv3_1 wrapper instance */
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qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0xac0000 0x2000>;
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#address-cells = <1>;
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#size-cells = <1>;
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clock-names = "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
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iommus = <&apps_smmu 0xb8 0x0>;
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qcom,iommu-group = <&qup_iommu_group>;
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dma-coherent;
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ranges;
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status = "ok";
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/* Touchscreen I2C Instance */
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qupv3_se4_i2c: i2c@a90000 {
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compatible = "qcom,i2c-geni";
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reg = <0xa90000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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dmas = <&gpi_dma1 0 4 3 64 0xc>,
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<&gpi_dma1 1 4 3 64 0xc>;
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dma-names = "tx", "rx";
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qcom,le-vm;
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status = "disabled";
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};
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/* Touchscreen SPI Instance */
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qupv3_se4_spi: spi@a90000 {
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compatible = "qcom,spi-geni";
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reg = <0xa90000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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dmas = <&gpi_dma1 0 4 1 64 0xc>,
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<&gpi_dma1 1 4 1 64 0xc>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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qcom,le-vm;
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status = "disabled";
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};
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};
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/* QUPv3_2 GPI Instance */
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gpi_dma2: qcom,gpi-dma@800000 {
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compatible = "qcom,gpi-dma";
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#dma-cells = <5>;
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reg = <0x800000 0x60000>;
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reg-names = "gpi-top";
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iommus = <&apps_smmu 0x438 0x0>;
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qcom,iommu-group = <&qup_iommu_group>;
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dma-coherent;
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interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
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qcom,max-num-gpii = <12>;
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qcom,static-gpii-mask = <0x20>;
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qcom,gpii-mask = <0x0>;
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qcom,ev-factor = <1>;
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qcom,gpi-ee-offset = <0x10000>;
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qcom,le-vm;
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status = "ok";
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};
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/* QUPv3_2 wrapper instance */
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qupv3_2: qcom,qupv3_2_geni_se@8c0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x8c0000 0x2000>;
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#address-cells = <1>;
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#size-cells = <1>;
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clock-names = "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
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iommus = <&apps_smmu 0x438 0x0>;
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qcom,iommu-group = <&qup_iommu_group>;
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dma-coherent;
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ranges;
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status = "ok";
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/* Secondary Tounch */
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qupv3_se15_i2c: i2c@89c000 {
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compatible = "qcom,i2c-geni";
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reg = <0x89c000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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dmas = <&gpi_dma2 0 7 3 64 0xc>,
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<&gpi_dma2 1 7 3 64 0xc>;
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dma-names = "tx", "rx";
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qcom,le-vm;
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status = "disabled";
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};
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/* Secondary Tounch */
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qupv3_se15_spi: spi@89c000 {
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compatible = "qcom,spi-geni";
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reg = <0x89c000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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dmas = <&gpi_dma2 0 7 1 64 0xc>,
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<&gpi_dma2 1 7 1 64 0xc>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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qcom,le-vm;
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status = "disabled";
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};
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};
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};
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#include "msm-arm-smmu-tuna-vm.dtsi"
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