ARM: dts: msm: Add smem nodes for sdxkova

Add smem nodes for sdxkova SoC.

Change-Id: I489aa0d9341cc48350a37c244135909d1686b0b5
Signed-off-by: Vishnu Santhosh <quic_vishsant@quicinc.com>
This commit is contained in:
Vishnu Santhosh
2024-08-29 21:24:31 +05:30
parent 160a80d44a
commit 04904d20a8
2 changed files with 14 additions and 0 deletions

View File

@@ -64,6 +64,8 @@
}; };
smem_mem: smem_region@87e20000 { smem_mem: smem_region@87e20000 {
compatible = "qcom,smem";
hwlocks = <&tcsr_mutex 3>;
no-map; no-map;
reg = <0x0 0x87e20000 0x0 0xc0000>; reg = <0x0 0x87e20000 0x0 0xc0000>;
}; };

View File

@@ -6,6 +6,7 @@
#include <dt-bindings/soc/qcom,ipcc.h> #include <dt-bindings/soc/qcom,ipcc.h>
#include "sdx75.dtsi" #include "sdx75.dtsi"
/delete-node/ &apps_smmu; /delete-node/ &apps_smmu;
/delete-node/ &tcsr_mutex;
#include "msm-arm-smmu-sdxkova.dtsi" #include "msm-arm-smmu-sdxkova.dtsi"
/{ /{
qcom_tzlog: tz-log@14680720 { qcom_tzlog: tz-log@14680720 {
@@ -406,6 +407,17 @@
interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
cap-based-alloc-and-pwr-collapse; cap-based-alloc-and-pwr-collapse;
}; };
tcsr_mutex_block: syscon@1f40000 {
compatible = "syscon";
reg = <0x0 0x1f40000 0x0 0x20000>;
};
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_block 0 0x1000>;
#hwlock-cells = <1>;
};
}; };
&gcc { &gcc {