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Change-Id: I1067e54cb3778763fdc0e24df61a3ec5fe5ebcc8
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Linux Build Service Account
2024-04-16 23:27:45 -07:00
parent bcf7659cfa 598a26d450
commit 02b4589f9a
58 changed files with 6754 additions and 3125 deletions
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4
Kbuild
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@@ -21,7 +21,9 @@ dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \
display/sun-sde-display-rcm-kiwi-v8-overlay.dtbo \
display/sun-sde-display-rcm-v8-overlay.dtbo \
display/sun-sde-display-mtp-qmp1000-overlay.dtbo \
display/sun-sde-display-mtp-qmp1000-v8-overlay.dtbo
display/sun-sde-display-mtp-qmp1000-v8-overlay.dtbo \
display/sun-sde-display-hdk-overlay.dtbo \
display/sun-sde-display-cdp-no-display-overlay.dtbo
else
dtbo-$(CONFIG_ARCH_SUN) += display/trustedvm-sun-sde-display-cdp-overlay.dtbo \
display/trustedvm-sun-sde-display-mtp-overlay.dtbo \

278
bindings/dsi.txt
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@@ -1,278 +0,0 @@
Qualcomm Technologies Inc. snapdragon DSI output
DSI Controller:
Required properties:
- compatible:
* "qcom,mdss-dsi-ctrl"
- reg: Physical base address and length of the registers of controller
- reg-names: The names of register regions. The following regions are required:
* "dsi_ctrl"
- interrupts: The interrupt signal from the DSI block.
- power-domains: Should be <&mmcc MDSS_GDSC>.
- clocks: Phandles to device clocks.
- clock-names: the following clocks are required:
* "mdp_core"
* "iface"
* "bus"
* "core_mmss"
* "byte"
* "pixel"
* "core"
For DSIv2, we need an additional clock:
* "src"
For DSI6G v2.0 onwards, we need also need the clock:
* "byte_intf"
- assigned-clocks: Parents of "byte" and "pixel" for the given platform.
- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
by a DSI PHY block. See [1] for details on clock bindings.
- vdd-supply: phandle to vdd regulator device node
- vddio-supply: phandle to vdd-io regulator device node
- vdda-supply: phandle to vdda regulator device node
- phys: phandle to DSI PHY device node
- phy-names: the name of the corresponding PHY device
- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2)
- ports: Contains 2 DSI controller ports as child nodes. Each port contains
an endpoint subnode as defined in [2] and [3].
Optional properties:
- panel@0: Node of panel connected to this DSI controller.
See files in [4] for each supported panel.
- qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is
driving a panel which needs 2 DSI links.
- qcom,master-dsi: Boolean value indicating if the DSI controller is driving
the master link of the 2-DSI panel.
- qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is
driving a 2-DSI panel whose 2 links need receive command simultaneously.
- pinctrl-names: the pin control state names; should contain "default"
- pinctrl-0: the default pinctrl state (active)
- pinctrl-n: the "sleep" pinctrl state
- ports: contains DSI controller input and output ports as children, each
containing one endpoint subnode.
- qcom,dsi-ctrl-shared: Boolean value indicating if the DSI controller is
shared between dual displays.
DSI Endpoint properties:
- remote-endpoint: For port@0, set to phandle of the connected panel/bridge's
input endpoint. For port@1, set to the MDP interface output. See [2] for
device graph info.
- data-lanes: this describes how the physical DSI data lanes are mapped
to the logical lanes on the given platform. The value contained in
index n describes what physical lane is mapped to the logical lane n
(DATAn, where n lies between 0 and 3). The clock lane position is fixed
and can't be changed. Hence, they aren't a part of the DT bindings. See
[3] for more info on the data-lanes property.
For example:
data-lanes = <3 0 1 2>;
The above mapping describes that the logical data lane DATA0 is mapped to
the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2
to phys DATA1 and logic DATA3 to phys DATA2.
There are only a limited number of physical to logical mappings possible:
<0 1 2 3>
<1 2 3 0>
<2 3 0 1>
<3 0 1 2>
<0 3 2 1>
<1 0 3 2>
<2 1 0 3>
<3 2 1 0>
DSI PHY:
Required properties:
- compatible: Could be the following
* "qcom,dsi-phy-28nm-hpm"
* "qcom,dsi-phy-28nm-lp"
* "qcom,dsi-phy-20nm"
* "qcom,dsi-phy-28nm-8960"
* "qcom,dsi-phy-14nm"
* "qcom,dsi-phy-10nm"
- reg: Physical base address and length of the registers of PLL, PHY. Some
revisions require the PHY regulator base address, whereas others require the
PHY lane base address. See below for each PHY revision.
- reg-names: The names of register regions. The following regions are required:
For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY:
* "dsi_pll"
* "dsi_phy"
* "dsi_phy_regulator"
For DSI 14nm and 10nm PHYs:
* "dsi_pll"
* "dsi_phy"
* "dsi_phy_lane"
- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating
2 clocks: A byte clock (index 0), and a pixel clock (index 1).
- power-domains: Should be <&mmcc MDSS_GDSC>.
- clocks: Phandles to device clocks. See [1] for details on clock bindings.
- clock-names: the following clocks are required:
* "iface"
For 28nm HPM/LP, 28nm 8960 PHYs:
- vddio-supply: phandle to vdd-io regulator device node
For 20nm PHY:
- vddio-supply: phandle to vdd-io regulator device node
- vcca-supply: phandle to vcca regulator device node
For 14nm PHY:
- vcca-supply: phandle to vcca regulator device node
For 10nm PHY:
- vdds-supply: phandle to vdds regulator device node
Optional properties:
- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
regulator is wanted.
- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode
panels in microseconds. Driver uses this number to adjust
the clock rate according to the expected transfer time.
Increasing this value would slow down the mdp processing
and can result in slower performance.
Decreasing this value can speed up the mdp processing,
but this can also impact power consumption.
As a rule this time should not be higher than the time
that would be expected with the processing at the
dsi link rate since anyways this would be the maximum
transfer time that could be achieved.
If ping pong split is enabled, this time should not be higher
than two times the dsi link rate time.
If the property is not specified, then the default value is 14000 us.
- frame-threshold-time-us: For command mode panels, this specifies the idle
time for dsi controller where no active data is
send to the panel, as controller is done sending
active pixels. If there is no desired DSI clocks
specified, then clocks will be derived from this
threshold time, which has a default value in chipset
based on the CPU processing power.
- dsi_pll_codes: Contain an u32 array data to store dsi pll codes which were passed
from UEFI.
- qcom,dsi-phy-shared: Boolean value indicating if the DSI phy is shared
between dual displays.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/graph.txt
[3] Documentation/devicetree/bindings/media/video-interfaces.txt
[4] Documentation/devicetree/bindings/display/panel/
Example:
dsi0: dsi@fd922800 {
compatible = "qcom,mdss-dsi-ctrl";
qcom,dsi-host-index = <0>;
interrupt-parent = <&mdp>;
interrupts = <4 0>;
reg-names = "dsi_ctrl";
reg = <0xfd922800 0x200>;
power-domains = <&mmcc MDSS_GDSC>;
clock-names =
"bus",
"byte",
"core",
"core_mmss",
"iface",
"mdp_core",
"pixel";
clocks =
<&mmcc MDSS_AXI_CLK>,
<&mmcc MDSS_BYTE0_CLK>,
<&mmcc MDSS_ESC0_CLK>,
<&mmcc MMSS_MISC_AHB_CLK>,
<&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_MDP_CLK>,
<&mmcc MDSS_PCLK0_CLK>;
assigned-clocks =
<&mmcc BYTE0_CLK_SRC>,
<&mmcc PCLK0_CLK_SRC>;
assigned-clock-parents =
<&dsi_phy0 0>,
<&dsi_phy0 1>;
vdda-supply = <&pma8084_l2>;
vdd-supply = <&pma8084_l22>;
vddio-supply = <&pma8084_l12>;
phys = <&dsi_phy0>;
phy-names ="dsi-phy";
qcom,dual-dsi-mode;
qcom,master-dsi;
qcom,sync-dual-dsi;
qcom,dsi-ctrl-shared;
qcom,mdss-mdp-transfer-time-us = <12000>;
frame-threshold-time-us = <800>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&dsi_active>;
pinctrl-1 = <&dsi_suspend>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&mdp_intf1_out>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
remote-endpoint = <&panel_in>;
data-lanes = <0 1 2 3>;
};
};
};
panel: panel@0 {
compatible = "sharp,lq101r1sx01";
reg = <0>;
link2 = <&secondary>;
power-supply = <...>;
backlight = <...>;
port {
panel_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
};
dsi_phy0: dsi-phy@fd922a00 {
compatible = "qcom,dsi-phy-28nm-hpm";
qcom,dsi-phy-index = <0>;
reg-names =
"dsi_pll",
"dsi_phy",
"dsi_phy_regulator";
reg = <0xfd922a00 0xd4>,
<0xfd922b00 0x2b0>,
<0xfd922d80 0x7b>;
clock-names = "iface";
clocks = <&mmcc MDSS_AHB_CLK>;
#clock-cells = <1>;
vddio-supply = <&pma8084_l12>;
qcom,dsi-phy-regulator-ldo-mode;
qcom,panel-allow-phy-poweroff;
qcom,dsi-phy-regulator-min-datarate-bps = <1200000000>;
qcom,panel-force-clock-lane-hs;
pll_codes_region = <&dsi_pll_codes_data>;
qcom,dsi-phy-shared;
};
dsi_pll_codes_data:dsi_pll_codes {
reg = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
label = "dsi_pll_codes";
};

226
bindings/dsi.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dsi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies Inc. Snapdragon DSI Controller output
description: >
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/graph.txt
[3] Documentation/devicetree/bindings/media/video-interfaces.txt
[4] Documentation/devicetree/bindings/display/panel/
maintainers:
- Vara Reddy <quic_varar@quicinc.com>
- Vishnuvardhan Prodduturi <quic_vproddut@quicinc.com>
properties:
compatible:
const: qcom,mdss-dsi-ctrl
reg:
description: Physical base address and length of the registers of controller
reg-names:
description: The names of register regions.
required:
- "dsi_ctrl"
interrupts:
description: The interrupt signal from the DSI block.
power-domains:
const: <&mmcc MDSS_GDSC>
clocks:
description: Phandles to device clocks.
$ref: /schemas/types.yaml#/definitions/phandle
clock-names:
description: >
Clocks necessary for DSI operation. For DSIv2, we need an additional clock "src" and for
DSI6G v2.0 onwards, we also need the clock "byte_intf".
required:
- "mdp_core"
- "iface"
- "bus"
- "core_mmss"
- "byte"
- "pixel"
- "core"
assigned-clocks:
description: Parents of "byte" and "pixel" for the given platform.
assigned-clock-parents:
description: >
The Byte clock and Pixel clock PLL outputs provided
by a DSI PHY block. See [1] for details on clock bindings.
vdd-supply:
description: phandle to vdd regulator device node
$ref: /schemas/types.yaml#/definitions/phandle
vddio-supply:
description: phandle to vdd-io regulator device node
$ref: /schemas/types.yaml#/definitions/phandle
vdda-supply:
description: phandle to vdda regulator device node
$ref: /schemas/types.yaml#/definitions/phandle
phys:
description: phandle to DSI PHY device node
$ref: /schemas/types.yaml#/definitions/phandle
phy-names:
description: the name of the corresponding PHY device
$ref: /schemas/types.yaml#/definitions/string-array
syscon-sfpb:
description: A phandle to mmss_sfpb syscon node (only for DSIv2)
$ref: /schemas/types.yaml#/definitions/phandle
panel@0:
description: >
Node of panel connected to this DSI controller.
See files in [4] for each supported panel.
qcom,dual-dsi-mode:
description: >
Boolean value indicating if the DSI controller is
driving a panel which needs 2 DSI links.
qcom,master-dsi:
description: >
Boolean value indicating if the DSI controller is driving
the master link of the 2-DSI panel.
qcom,sync-dual-dsi:
description: >
Boolean value indicating if the DSI controller is
driving a 2-DSI panel whose 2 links need receive command simultaneously.
pinctrl-names:
description: the pin control state names; should contain "default"
pinctrl-0:
description: the default pinctrl state (active)
pinctrl-n:
description: the "sleep" pinctrl state
qcom,dsi-ctrl-shared:
description: >
Boolean value indicating if the DSI controller is
shared between dual displays.
required:
- compatible
- reg
- reg-names
- interrupts
- power-domains
- clocks
- clock-names
- assigned-clocks
- assigned-clock-parents
- vdd-supply
- vddio-supply
- vdda-supply
- phys
- phy-names
- syscon-sfpb
- ports
examples:
- |
dsi0: dsi@fd922800 {
compatible = "qcom,mdss-dsi-ctrl";
qcom,dsi-host-index = <0>;
interrupt-parent = <&mdp>;
interrupts = <4 0>;
reg-names = "dsi_ctrl";
reg = <0xfd922800 0x200>;
power-domains = <&mmcc MDSS_GDSC>;
clock-names =
"bus",
"byte",
"core",
"core_mmss",
"iface",
"mdp_core",
"pixel";
clocks =
<&mmcc MDSS_AXI_CLK>,
<&mmcc MDSS_BYTE0_CLK>,
<&mmcc MDSS_ESC0_CLK>,
<&mmcc MMSS_MISC_AHB_CLK>,
<&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_MDP_CLK>,
<&mmcc MDSS_PCLK0_CLK>;
assigned-clocks =
<&mmcc BYTE0_CLK_SRC>,
<&mmcc PCLK0_CLK_SRC>;
assigned-clock-parents =
<&dsi_phy0 0>,
<&dsi_phy0 1>;
vdda-supply = <&pma8084_l2>;
vdd-supply = <&pma8084_l22>;
vddio-supply = <&pma8084_l12>;
phys = <&dsi_phy0>;
phy-names ="dsi-phy";
qcom,dual-dsi-mode;
qcom,master-dsi;
qcom,sync-dual-dsi;
qcom,dsi-ctrl-shared;
qcom,mdss-mdp-transfer-time-us = <12000>;
frame-threshold-time-us = <800>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&dsi_active>;
pinctrl-1 = <&dsi_suspend>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&mdp_intf1_out>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
remote-endpoint = <&panel_in>;
data-lanes = <0 1 2 3>;
};
};
};
panel: panel@0 {
compatible = "sharp,lq101r1sx01";
reg = <0>;
link2 = <&secondary>;
power-supply = <...>;
backlight = <...>;
port {
panel_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
};
...

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dsi_phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies Inc. Snapdragon DSI PHY output
description: >
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/graph.txt
[3] Documentation/devicetree/bindings/media/video-interfaces.txt
[4] Documentation/devicetree/bindings/display/panel/
maintainers:
- Vara Reddy <quic_varar@quicinc.com>
- Vishnuvardhan Prodduturi <quic_vproddut@quicinc.com>
properties:
compatible:
enum:
- qcom,dsi-phy-28nm-hpm
- qcom,dsi-phy-28nm-lp
- qcom,dsi-phy-20nm
- qcom,dsi-phy-28nm-8960
- qcom,dsi-phy-14nm
- qcom,dsi-phy-10nm
reg:
description: >
Physical base address and length of the registers of PLL, PHY. Some
revisions require the PHY regulator base address, whereas others require the
PHY lane base address. See below for each PHY revision.
reg-names:
description: >
The names of register regions. For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY "dsi_phy_regulator"
is needed and for DSI 14nm and 10nm PHYs "dsi_phy_lane" is needed.
required:
- "dsi_pll"
- "dsi_phy"
clock-cells:
description: >
Must be 1. The DSI PHY block acts as a clock provider, creating
2 clocks: A byte clock (index 0), and a pixel clock (index 1).
const: 1
power-domains:
const: <&mmcc MDSS_GDSC>
clocks:
description: Phandles to device clocks. See [1] for details on clock bindings.
$ref: /schemas/types.yaml#/definitions/phandle
clock-names:
const: iface
$ref: /schemas/types.yaml#/definitions/string-array
vddio-supply:
description: >
For 28nm HPM/LP, 28nm 8960 PHYs and 20nm PHY, this is phandle to vdd-io regulator
device node
$ref: /schemas/types.yaml#/definitions/phandle
vcca-supply:
description: For 14nm PHY and 20nm PHY this is phandle to vcca regulator device node
$ref: /schemas/types.yaml#/definitions/phandle
vdds-supply:
description: For 10nm PHY , phandle to vdds regulator device node
$ref: /schemas/types.yaml#/definitions/phandle
qcom,dsi-phy-regulator-ldo-mode:
description: Boolean value indicating if the LDO mode PHY regulator is wanted.
qcom,mdss-mdp-transfer-time-us:
description: >
Specifies the dsi transfer time for command mode
panels in microseconds. Driver uses this number to adjust
the clock rate according to the expected transfer time.
Increasing this value would slow down the mdp processing
and can result in slower performance.
Decreasing this value can speed up the mdp processing,
but this can also impact power consumption.
As a rule this time should not be higher than the time
that would be expected with the processing at the
dsi link rate since anyways this would be the maximum
transfer time that could be achieved.
If ping pong split is enabled, this time should not be higher
than two times the dsi link rate time.
If the property is not specified, then the default value is 14000 us.
$ref: /schemas/types.yaml#/definitions/uint32
frame-threshold-time-us:
description: >
For command mode panels, this specifies the idle
time for dsi controller where no active data is
send to the panel, as controller is done sending
active pixels. If there is no desired DSI clocks
specified, then clocks will be derived from this
threshold time, which has a default value in chipset
based on the CPU processing power.
$ref: /schemas/types.yaml#/definitions/uint32
dsi_pll_codes:
description: Contain an u32 array data to store dsi pll codes which were passed from UEFI.
$ref: /schemas/types.yaml#/definitions/uint32-array
qcom,dsi-phy-shared:
description: Boolean value indicating if the DSI phy is shared between dual displays.
required:
- compatible
- reg
- reg-names
- clock-cells
- power-domains
- clocks
- clock-names
- vddio-supply
- vcca-supply
- vdds-supply
examples:
- |
dsi_phy0: dsi-phy@fd922a00 {
compatible = "qcom,dsi-phy-28nm-hpm";
qcom,dsi-phy-index = <0>;
reg-names =
"dsi_pll",
"dsi_phy",
"dsi_phy_regulator";
reg = <0xfd922a00 0xd4>,
<0xfd922b00 0x2b0>,
<0xfd922d80 0x7b>;
clock-names = "iface";
clocks = <&mmcc MDSS_AHB_CLK>;
#clock-cells = <1>;
vddio-supply = <&pma8084_l12>;
qcom,dsi-phy-regulator-ldo-mode;
qcom,panel-allow-phy-poweroff;
qcom,dsi-phy-regulator-min-datarate-bps = <1200000000>;
qcom,panel-force-clock-lane-hs;
pll_codes_region = <&dsi_pll_codes_data>;
qcom,dsi-phy-shared;
};
dsi_pll_codes_data:dsi_pll_codes {
reg = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
label = "dsi_pll_codes";
};
...

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MSM HDCP driver
Standalone driver managing HDCP related communications
between TZ and HLOS for MSM chipset.
Required properties:
compatible = "qcom,msm-hdcp";
Example:
qcom_msmhdcp: qcom,msm_hdcp {
compatible = "qcom,msm-hdcp";
};

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bindings/msm_hdcp.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/msm_hdcp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MSM HDCP driver
description: |
Standalone driver managing HDCP related communications between TZ and HLOS for MSM chipset.
maintainers:
- Rajkumar Subbiah <quic_rsubbia@quicinc.com>
- Vishnuvardhan Prodduturi <quic_vproddut@quicinc.com>
properties:
compatible:
const: qcom,msm-hdcp
required:
- compatible
examples:
- |
qcom_msmhdcp: qcom,msm_hdcp {
compatible = "qcom,msm-hdcp";
};
...

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bindings/sde-dp.txt
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Qualcomm Technologies, Inc.
sde-dp is the master Display Port device which supports DP host controllers that are compatible with VESA Display Port interface specification.
DP Controller: Required properties:
- compatible: Should be "qcom,dp-display".
- reg: Base address and length of DP hardware's memory mapped regions.
- reg-names: A list of strings that name the list of regs. "dp_ctrl" - DP controller memory region.
"dp_ahb" - AHB memory region.
"dp_aux" - AUX memory region.
"dp_link" - LINK memory region.
"dp_p0" - PCLK0 memory region.
"dp_phy" - PHY memory region.
"dp_ln_tx0" - USB3 DP PHY combo TX-0 lane memory region.
"dp_ln_tx1" - USB3 DP PHY combo TX-1 lane memory region.
"dp_mmss_cc" - Display Clock Control memory region.
"dp_pll" - USB3 DP combo PLL memory region.
"usb3_dp_com" - USB3 DP PHY combo memory region.
"hdcp_physical" - DP HDCP memory region.
"dp_p1" - DP PCLK1 memory region.
"gdsc" - DISPCC GDSC memory region.
- cell-index: Specifies the controller instance.
- #clock-cells: Denotes the DP driver as a clock producer (has one or more clock outputs)
- clocks: Clocks required for Display Port operation.
- clock-names: Names of the clocks corresponding to handles. Following clocks are required:
"core_aux_clk", "core_usb_ref_clk_src", "core_usb_pipe_clk", "link_clk",
"link_clk_src", "link_iface_clk", "pixel_clk_rcg", "pixel_parent",
"pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk".
- vdda-1p2-supply: phandle to vdda 1.2V regulator node.
- vdda-0p9-supply: phandle to vdda 0.9V regulator node.
- interrupt-parent phandle to the interrupt parent device node.
- interrupts: The interrupt signal from the DSI block.
- qcom,aux-cfg0-settings: Specifies the DP AUX configuration 0 settings. The first
entry in this array corresponds to the register offset
within DP AUX, while the remaining entries indicate the
programmable values.
- qcom,aux-cfg1-settings: Specifies the DP AUX configuration 1 settings. The first
entry in this array corresponds to the register offset
within DP AUX, while the remaining entries indicate the
programmable values.
- qcom,aux-cfg2-settings: Specifies the DP AUX configuration 2 settings. The first
entry in this array corresponds to the register offset
within DP AUX, while the remaining entries indicate the
programmable values.
- qcom,aux-cfg3-settings: Specifies the DP AUX configuration 3 settings. The first
entry in this array corresponds to the register offset
within DP AUX, while the remaining entries indicate the
programmable values.
- qcom,aux-cfg4-settings: Specifies the DP AUX configuration 4 settings. The first
entry in this array corresponds to the register offset
within DP AUX, while the remaining entries indicate the
programmable values.
- qcom,aux-cfg5-settings: Specifies the DP AUX configuration 5 settings. The first
entry in this array corresponds to the register offset
within DP AUX, while the remaining entries indicate the
programmable values.
- qcom,aux-cfg6-settings: Specifies the DP AUX configuration 6 settings. The first
entry in this array corresponds to the register offset
within DP AUX, while the remaining entries indicate the
programmable values.
- qcom,aux-cfg7-settings: Specifies the DP AUX configuration 7 settings. The first
entry in this array corresponds to the register offset
within DP AUX, while the remaining entries indicate the
programmable values.
- qcom,aux-cfg8-settings: Specifies the DP AUX configuration 8 settings. The first
entry in this array corresponds to the register offset
within DP AUX, while the remaining entries indicate the
programmable values.
- qcom,aux-cfg9-settings: Specifies the DP AUX configuration 9 settings. The first
entry in this array corresponds to the register offset
within DP AUX, while the remaining entries indicate the
programmable values.
- qcom,max-pclk-frequency-khz: An integer specifying the max. pixel clock in KHz supported by Display Port.
- qcom,mst-enable: MST feature enable control node.
- qcom,dsc-feature-enable: DSC feature enable control node.
- qcom,fec-feature-enable: FEC feature enable control node.
- qcom,qos-cpu-mask: A u32 value indicating desired PM QoS CPU affine mask
- qcom,qos-cpu-latency-us: A u32 value indicating desired PM QoS CPU latency in usec
- qcom,altmode-dev: Phandle for the AltMode GLink driver.
- usb-controller: Phandle for the USB controller.
- qcom,pll-revision: PLL hardware revision.
- usb-phy: Phandle for USB PHY driver. This is used to register for USB cable events.
- qcom,dsc-continuous-pps: Control node for sending PPS every frame in hardware for DSC over DP.
This is needed by certain bridge chips where there is such a requirement to do so.
- qcom,dp-aux-switch: Phandle for the driver used to program the AUX switch for Display Port orientation.
- qcom,dp-hpd-gpio: HPD gpio for direct DP connector without USB PHY or AUX switch.
- qcom,dp-gpio-aux-switch: Gpio DP AUX switch chipset support.
- qcom,<type>-supply-entries: A node that lists the elements of the supply used by the a particular "type" of DP module. The module "types"
can be "core", "ctrl", "pll" and "phy". Within the same type,
there can be more than one instance of this binding,
in which case the entry would be appended with the
supply entry index.
e.g. qcom,ctrl-supply-entry@0
-- qcom,supply-name: name of the supply (vdd/vdda/vddio)
-- qcom,supply-min-voltage: minimum voltage level (uV)
-- qcom,supply-max-voltage: maximum voltage level (uV)
-- qcom,supply-enable-load: load drawn (uA) from enabled supply
-- qcom,supply-disable-load: load drawn (uA) from disabled supply
-- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on
-- qcom,supply-post-on-sleep: time to sleep (ms) after turning on
-- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off
-- qcom,supply-post-off-sleep: time to sleep (ms) after turning off
msm_ext_disp is a device which manages the interaction between external
display interfaces, e.g. Display Port, and the audio subsystem.
Optional properties:
- clock-mmrm: List of the clocks that enable setting the clk rate through MMRM driver.
The order of the list must match the 'clocks' and 'clock-names'
properties. The 'DISP_CC' ID of the clock must be used to enable
the property for the respective clock, whereas a value of zero
disables the property.
- vdd_mx-supply: phandle to vdda MX regulator node
- qcom,aux-en-gpio: Specifies the aux-channel enable gpio.
- qcom,aux-sel-gpio: Specifies the aux-channel select gpio.
- qcom,usbplug-cc-gpio: Specifies the usbplug orientation gpio.
- qcom,ext-disp: phandle for msm-ext-display module
- compatible: Must be "qcom,msm-ext-disp"
- qcom,dp-low-power-hw-hpd: Low power hardware HPD feature enable control node
- qcom,phy-version: Phy version
- qcom,pn-swap-lane-map: P/N swap configuration of each lane
- pinctrl-names: List of names to assign mdss pin states defined in pinctrl device node
Refer to pinctrl-bindings.txt
- pinctrl-<0..n>: Lists phandles each pointing to the pin configuration node within a pin
controller. These pin configurations are installed in the pinctrl
device node. Refer to pinctrl-bindings.txt
- qcom,max-lclk-frequency-khz: An integer specifying the max. link clock in KHz supported by Display Port.
- qcom,mst-fixed-topology-ports: u32 values of which MST output port to reserve, start from one
- qcom,hbr-rbr-voltage-swing: Specifies the voltage swing levels for HBR and RBR rates.
- qcom,hbr-rbr-pre-emphasis: Specifies the pre-emphasis levels for HBR and RBR rates.
- qcom,hbr2-3-voltage-swing: Specifies the voltage swing levels for HBR2 and HBR3 rates.
- qcom,hbr2-3-pre-emphasis: Specifies the pre-emphasis levels for HBR2 and HBR3 rates.
[Optional child nodes]: These nodes are for devices which are
dependent on msm_ext_disp. If msm_ext_disp is disabled then
these devices will be disabled as well. Ex. Audio Codec device.
- ext_disp_audio_codec: Node for Audio Codec.
- compatible : "qcom,msm-ext-disp-audio-codec-rx";
Example:
ext_disp: qcom,msm-ext-disp {
compatible = "qcom,msm-ext-disp";
ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
compatible = "qcom,msm-ext-disp-audio-codec-rx";
};
};
sde_dp: qcom,dp_display@0 {
cell-index = <0>;
compatible = "qcom,dp-display";
qcom,dp-aux-switch = <&fsa4480>;
qcom,ext-disp = <&ext_disp>;
qcom,altmode-dev = <&altmode 0>;
usb-controller = <&usb0>;
reg = <0xae90000 0x0dc>,
<0xae90200 0x0c0>,
<0xae90400 0x508>,
<0xae91000 0x094>,
<0x88eaa00 0x200>,
<0x88ea200 0x200>,
<0x88ea600 0x200>,
<0xaf02000 0x1a0>,
<0x88ea000 0x200>,
<0x88e8000 0x20>,
<0x0aee1000 0x034>,
<0xae91400 0x094>,
<0xaf03000 0x8>;
reg-names = "dp_ahb", "dp_aux", "dp_link",
"dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
"dp_mmss_cc", "dp_pll", "usb3_dp_com",
"hdcp_physical", "dp_p1", "gdsc";
interrupt-parent = <&mdss_mdp>;
interrupts = <12 0>;
#clock-cells = <1>;
clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>,
<&clock_rpmh RPMH_CXO_CLK>,
<&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
<&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>,
<&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
<&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
<&sde_dp DP_PHY_PLL_VCO_DIV_CLK>,
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>,
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
clock-names = "core_aux_clk", "core_usb_ref_clk_src",
"core_usb_pipe_clk", "link_clk", "link_clk_src",
"link_iface_clk", "pixel_clk_rcg", "pixel_parent",
"pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk";
clock-mmrm = <0 0 0 0 DISP_CC_MDSS_DP_LINK_CLK_SRC 0 0 0 0 0 0>;
qcom,pll-revision = "5nm-v1";
qcom,phy-version = <0x420>;
qcom,dp-aux-switch = <&fsa4480>;
qcom,aux-cfg0-settings = [1c 00];
qcom,aux-cfg1-settings = [20 13 23 1d];
qcom,aux-cfg2-settings = [24 00];
qcom,aux-cfg3-settings = [28 00];
qcom,aux-cfg4-settings = [2c 0a];
qcom,aux-cfg5-settings = [30 26];
qcom,aux-cfg6-settings = [34 0a];
qcom,aux-cfg7-settings = [38 03];
qcom,aux-cfg8-settings = [3c bb];
qcom,aux-cfg9-settings = [40 03];
qcom,max-pclk-frequency-khz = <593470>;
qcom,mst-enable;
qcom,dsc-feature-enable;
qcom,fec-feature-enable;
qcom,dsc-continuous-pps;
qcom,qos-cpu-mask = <0xf>;
qcom,qos-cpu-latency-us = <300>;
vdda-1p2-supply = <&L6B>;
vdda-0p9-supply = <&L1B>;
vdd_mx-supply = <&VDD_MXA_LEVEL>;
qcom,hbr-rbr-voltage-swing = <0x07 0x0f 0x16 0x1f>,
<0x11 0x1e 0x1f 0xff>,
<0x16 0x1f 0xff 0xff>,
<0x1f 0xff 0xff 0xff>;
qcom,hbr-rbr-pre-emphasis = <0x00 0x0d 0x14 0x1a>,
<0x00 0x0e 0x15 0xff>,
<0x00 0x0e 0xff 0xff>,
<0x02 0xff 0xff 0xff>;
qcom,hbr2-3-voltage-swing = <0x02 0x12 0x16 0x1a>,
<0x09 0x19 0x1f 0xff>,
<0x10 0x1f 0xff 0xff>,
<0x1f 0xff 0xff 0xff>;
qcom,hbr2-3-pre-emphasis = <0x00 0x0c 0x15 0x1b>,
<0x02 0x0e 0x16 0xff>,
<0x02 0x11 0xff 0xff>,
<0x04 0xff 0xff 0xff>;
qcom,ctrl-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,ctrl-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdda-1p2";
qcom,supply-min-voltage = <1200000>;
qcom,supply-max-voltage = <1200000>;
qcom,supply-enable-load = <21700>;
qcom,supply-disable-load = <0>;
};
};
qcom,phy-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,phy-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdda-0p9";
qcom,supply-min-voltage = <912000>;
qcom,supply-max-voltage = <912000>;
qcom,supply-enable-load = <115000>;
qcom,supply-disable-load = <0>;
};
};
qcom,core-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,core-supply-entry@0 {
reg = <0>;
qcom,supply-name = "refgen";
qcom,supply-min-voltage = <0>;
qcom,supply-max-voltage = <0>;
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
};
};
qcom,pll-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,pll-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdd_mx";
qcom,supply-min-voltage =
<RPMH_REGULATOR_LEVEL_TURBO>;
qcom,supply-max-voltage =
<RPMH_REGULATOR_LEVEL_MAX>;
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
};
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sde-dp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SDE DP
description: |
sde-dp is the master Display Port device which supports DP host controllers that are compatible
with VESA Display Port interface specification.
msm_ext_disp is a device which manages the interaction between external
display interfaces, e.g. Display Port, and the audio subsystem.
[Optional child nodes]: These nodes are for devices which are
dependent on msm_ext_disp. If msm_ext_disp is disabled then
these devices will be disabled as well. Ex. Audio Codec device.
maintainers:
- Rajkumar Subbiah <quic_rsubbia@quicinc.com>
- Vishnuvardhan Prodduturi <quic_vproddut@quicinc.com>
properties:
compatible:
const: qcom,dp-display
reg:
description: |
Base address and length of DP hardware's memory mapped regions.
reg-names:
description: |
A list of strings that name the list of regs. "dp_ctrl" - DP controller memory region.
"dp_ahb" - AHB memory region.
"dp_aux" - AUX memory region.
"dp_link" - LINK memory region.
"dp_p0" - PCLK0 memory region.
"dp_phy" - PHY memory region.
"dp_ln_tx0" - USB3 DP PHY combo TX-0 lane memory region.
"dp_ln_tx1" - USB3 DP PHY combo TX-1 lane memory region.
"dp_mmss_cc" - Display Clock Control memory region.
"dp_pll" - USB3 DP combo PLL memory region.
"usb3_dp_com" - USB3 DP PHY combo memory region.
"hdcp_physical" - DP HDCP memory region.
"dp_p1" - DP PCLK1 memory region.
"gdsc" - DISPCC GDSC memory region.
cell-index:
description: Specifies the controller instance.
'#clock-cells':
description: Denotes the DP driver as a clock producer (has one or more clock outputs)
clocks:
description: Clocks required for Display Port operation.
clock-names:
items:
- const: core_aux_clk
- const: core_usb_ref_clk_src
- const: core_usb_pipe_clk
- const: link_clk
- const: link_clk_src
- const: link_iface_clk
- const: pixel_clk_rcg
- const: pixel_parent
- const: pixel1_clk_rcg
- const: strm0_pixel_clk
- const: strm1_pixel_clk
vdda-1p2-supply:
description: phandle to vdda 1.2V regulator node.
$ref: /schemas/types.yaml#/definitions/phandle
vdda-0p9-supply:
description: phandle to vdda 0.9V regulator node.
$ref: /schemas/types.yaml#/definitions/phandle
interrupt-parent:
description: phandle to the interrupt parent device node.
$ref: /schemas/types.yaml#/definitions/phandle
interrupts:
description: The interrupt signal from the DSI block.
qcom,aux-cfg0-settings:
description: |
Specifies the DP AUX configuration 0 settings. The first
entry in this array corresponds to the register offset
within DP AUX, while the remaining entries indicate the
programmable values.
qcom,aux-cfg1-settings:
description: |
Specifies the DP AUX configuration 1 settings. The first
entry in this array corresponds to the register offset
within DP AUX, while the remaining entries indicate the
programmable values.
qcom,aux-cfg2-settings:
description: |
Specifies the DP AUX configuration 2 settings. The first
entry in this array corresponds to the register offset
within DP AUX, while the remaining entries indicate the
programmable values.
qcom,aux-cfg3-settings:
description: |
Specifies the DP AUX configuration 3 settings. The first
entry in this array corresponds to the register offset
within DP AUX, while the remaining entries indicate the
programmable values.
qcom,aux-cfg4-settings:
description: |
Specifies the DP AUX configuration 4 settings. The first
entry in this array corresponds to the register offset
within DP AUX, while the remaining entries indicate the
programmable values.
qcom,aux-cfg5-settings:
description: |
Specifies the DP AUX configuration 5 settings. The first
entry in this array corresponds to the register offset
within DP AUX, while the remaining entries indicate the
programmable values.
qcom,aux-cfg6-settings:
description: |
Specifies the DP AUX configuration 6 settings. The first
entry in this array corresponds to the register offset
within DP AUX, while the remaining entries indicate the
programmable values.
qcom,aux-cfg7-settings:
description: |
Specifies the DP AUX configuration 7 settings. The first
entry in this array corresponds to the register offset
within DP AUX, while the remaining entries indicate the
programmable values.
qcom,aux-cfg8-settings:
description: |
Specifies the DP AUX configuration 8 settings. The first
entry in this array corresponds to the register offset
within DP AUX, while the remaining entries indicate the
programmable values.
qcom,aux-cfg9-settings:
description: |
Specifies the DP AUX configuration 9 settings. The first
entry in this array corresponds to the register offset
within DP AUX, while the remaining entries indicate the
programmable values.
qcom,max-pclk-frequency-khz:
description: An integer specifying the max. pixel clock in KHz supported by Display Port.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,mst-enable:
description: MST feature enable control node.
qcom,dsc-feature-enable:
description: DSC feature enable control node.
qcom,fec-feature-enable:
description: FEC feature enable control node.
qcom,qos-cpu-mask:
description: A u32 value indicating desired PM QoS CPU affine mask
$ref: /schemas/types.yaml#/definitions/uint32
qcom,qos-cpu-latency-us:
description: A u32 value indicating desired PM QoS CPU latency in usec
$ref: /schemas/types.yaml#/definitions/uint32
qcom,altmode-dev:
description: Phandle for the AltMode GLink driver.
$ref: /schemas/types.yaml#/definitions/phandle
usb-controller:
description: Phandle for the USB controller.
$ref: /schemas/types.yaml#/definitions/phandle
qcom,pll-revision:
description: PLL hardware revision.
usb-phy:
description: Phandle for USB PHY driver. This is used to register for USB cable events.
$ref: /schemas/types.yaml#/definitions/phandle
qcom,dsc-continuous-pps:
description: |
Control node for sending PPS every frame in hardware for DSC over DP.
This is needed by certain bridge chips where there is such a requirement to do so.
qcom,dp-aux-switch:
description: Phandle for the driver used to program the AUX switch for Display Port orientation.
$ref: /schemas/types.yaml#/definitions/phandle
qcom,dp-hpd-gpio:
description: HPD gpio for direct DP connector without USB PHY or AUX switch.
qcom,dp-gpio-aux-switch:
description: Gpio DP AUX switch chipset support.
clock-mmrm:
description: |
List of the clocks that enable setting the clk rate through MMRM driver.
The order of the list must match the 'clocks' and 'clock-names'
properties. The 'DISP_CC' ID of the clock must be used to enable
the property for the respective clock, whereas a value of zero
disables the property.
vdd_mx-supply:
description: phandle to vdda MX regulator node
$ref: /schemas/types.yaml#/definitions/phandle
qcom,aux-en-gpio:
description: Specifies the aux-channel enable gpio.
qcom,aux-sel-gpio:
description: Specifies the aux-channel select gpio.
qcom,usbplug-cc-gpio:
description: Specifies the usbplug orientation gpio.
qcom,ext-disp:
description: phandle for msm-ext-display module
$ref: /schemas/types.yaml#/definitions/phandle
compatible:
const: qcom,msm-ext-disp
qcom,dp-low-power-hw-hpd:
description: Low power hardware HPD feature enable control node
qcom,phy-version:
description: Phy version
pinctrl-names:
description: |
List of names to assign mdss pin states defined in pinctrl device node
Refer to pinctrl-bindings.txt
pinctrl-<0..n>:
description: |
Lists phandles each pointing to the pin configuration node within a pin
controller. These pin configurations are installed in the pinctrl
device node. Refer to pinctrl-bindings.txt
qcom,max-lclk-frequency-khz:
description: An integer specifying the max. link clock in KHz supported by Display Port.
qcom,mst-fixed-topology-ports:
description: u32 values of which MST output port to reserve, start from one
$ref: /schemas/types.yaml#/definitions/uint32
qcom,hbr-rbr-voltage-swing:
description: Specifies the voltage swing levels for HBR and RBR rates.
qcom,hbr-rbr-pre-emphasis:
description: Specifies the pre-emphasis levels for HBR and RBR rates.
qcom,hbr2-3-voltage-swing:
description: Specifies the voltage swing levels for HBR2 and HBR3 rates.
qcom,hbr2-3-pre-emphasis:
description: Specifies the pre-emphasis levels for HBR2 and HBR3 rates.
compatible:
const: qcom,msm-ext-disp-audio-codec-rx
ext_disp_audio_codec:
description: Node for Audio Codec.
pattern properties:
"qcom,+\w+\-supply\-entries":
description: |
A node that lists the elements of the supply used by the
a particular "type" of DSI module. The module "types"
can be "core", "ctrl", and "phy". Within the same type,
there can be more than one instance of this binding,
in which case the entry would be appended with the
supply entry index.
e.g. qcom,ctrl-supply-entry@0
type: object
patternProperties:
"qcom,ctrl\-supply\-entry\@+\w":
properties:
reg:
description: offset and length of the register set for the device.
qcom,supply-name:
description: name of the supply (vdd/vdda/vddio)
$ref: /schemas/types.yaml#/definitions/string-array
qcom,supply-min-voltage:
description: minimum voltage level (uV)
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-max-voltage:
description: maximum voltage level (uV)
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-enable-load:
description: load drawn (uA) from enabled supply
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-disable-load:
description: load drawn (uA) from disabled supply
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-pre-on-sleep:
description: time to sleep (ms) before turning on
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-post-on-sleep:
description: time to sleep (ms) after turning on
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-pre-off-sleep:
description: time to sleep (ms) before turning off
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-post-off-sleep:
description: time to sleep (ms) after turning off
$ref: /schemas/types.yaml#/definitions/uint32
"qcom,core\-supply\-entry\@+\w":
properties:
reg:
description: offset and length of the register set for the device.
qcom,supply-name:
description: name of the supply (vdd/vdda/vddio)
$ref: /schemas/types.yaml#/definitions/string-array
qcom,supply-min-voltage:
description: minimum voltage level (uV)
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-max-voltage:
description: maximum voltage level (uV)
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-enable-load:
description: load drawn (uA) from enabled supply
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-disable-load:
description: load drawn (uA) from disabled supply
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-pre-on-sleep:
description: time to sleep (ms) before turning on
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-post-on-sleep:
description: time to sleep (ms) after turning on
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-pre-off-sleep:
description: time to sleep (ms) before turning off
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-post-off-sleep:
description: time to sleep (ms) after turning off
$ref: /schemas/types.yaml#/definitions/uint32
"qcom,phy\-supply\-entry\@+\w":
properties:
reg:
description: offset and length of the register set for the device.
qcom,supply-name:
description: name of the supply (vdd/vdda/vddio)
$ref: /schemas/types.yaml#/definitions/string-array
qcom,supply-min-voltage:
description: minimum voltage level (uV)
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-max-voltage:
description: maximum voltage level (uV)
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-enable-load:
description: load drawn (uA) from enabled supply
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-disable-load:
description: load drawn (uA) from disabled supply
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-pre-on-sleep:
description: time to sleep (ms) before turning on
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-post-on-sleep:
description: time to sleep (ms) after turning on
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-pre-off-sleep:
description: time to sleep (ms) before turning off
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-post-off-sleep:
description: time to sleep (ms) after turning off
$ref: /schemas/types.yaml#/definitions/uint32
required:
- compatible
- reg
- reg-names
- cell-index
- '#clock-cells'
- clocks
- clock-names
- vdda-1p2-supply
- vdda-0p9-supply
- interrupt-parent
- interrupts
- qcom,aux-cfg0-settings
- qcom,aux-cfg1-settings
- qcom,aux-cfg2-settings
- qcom,aux-cfg3-settings
- qcom,aux-cfg4-settings
- qcom,aux-cfg5-settings
- qcom,aux-cfg6-settings
- qcom,aux-cfg7-settings
- qcom,aux-cfg8-settings
- qcom,aux-cfg9-settings
- qcom,max-pclk-frequency-khz
- qcom,mst-enable
- qcom,dsc-feature-enable
- qcom,fec-feature-enable
- qcom,qos-cpu-mask
- qcom,qos-cpu-latency-us
- qcom,altmode-dev
- usb-controller
- qcom,pll-revision
- usb-phy
- qcom,dp-aux-switch
- qcom,dp-hpd-gpio
- qcom,dp-gpio-aux-switch
- qcom,<type>-supply-entries
examples:
- |
ext_disp: qcom,msm-ext-disp {
compatible = "qcom,msm-ext-disp";
ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
compatible = "qcom,msm-ext-disp-audio-codec-rx";
};
};
- |
sde_dp: qcom,dp_display@0 {
cell-index = <0>;
compatible = "qcom,dp-display";
qcom,dp-aux-switch = <&fsa4480>;
qcom,ext-disp = <&ext_disp>;
qcom,altmode-dev = <&altmode 0>;
usb-controller = <&usb0>;
reg = <0xae90000 0x0dc>,
<0xae90200 0x0c0>,
<0xae90400 0x508>,
<0xae91000 0x094>,
<0x88eaa00 0x200>,
<0x88ea200 0x200>,
<0x88ea600 0x200>,
<0xaf02000 0x1a0>,
<0x88ea000 0x200>,
<0x88e8000 0x20>,
<0x0aee1000 0x034>,
<0xae91400 0x094>,
<0xaf03000 0x8>;
reg-names = "dp_ahb", "dp_aux", "dp_link",
"dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
"dp_mmss_cc", "dp_pll", "usb3_dp_com",
"hdcp_physical", "dp_p1", "gdsc";
interrupt-parent = <&mdss_mdp>;
interrupts = <12 0>;
#clock-cells = <1>;
clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>,
<&clock_rpmh RPMH_CXO_CLK>,
<&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
<&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>,
<&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
<&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
<&sde_dp DP_PHY_PLL_VCO_DIV_CLK>,
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>,
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
clock-names = "core_aux_clk", "core_usb_ref_clk_src",
"core_usb_pipe_clk", "link_clk", "link_clk_src",
"link_iface_clk", "pixel_clk_rcg", "pixel_parent",
"pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk";
clock-mmrm = <0 0 0 0 DISP_CC_MDSS_DP_LINK_CLK_SRC 0 0 0 0 0 0>;
qcom,pll-revision = "5nm-v1";
qcom,phy-version = <0x420>;
qcom,dp-aux-switch = <&fsa4480>;
qcom,aux-cfg0-settings = [1c 00];
qcom,aux-cfg1-settings = [20 13 23 1d];
qcom,aux-cfg2-settings = [24 00];
qcom,aux-cfg3-settings = [28 00];
qcom,aux-cfg4-settings = [2c 0a];
qcom,aux-cfg5-settings = [30 26];
qcom,aux-cfg6-settings = [34 0a];
qcom,aux-cfg7-settings = [38 03];
qcom,aux-cfg8-settings = [3c bb];
qcom,aux-cfg9-settings = [40 03];
qcom,max-pclk-frequency-khz = <593470>;
qcom,mst-enable;
qcom,dsc-feature-enable;
qcom,fec-feature-enable;
qcom,dsc-continuous-pps;
qcom,qos-cpu-mask = <0xf>;
qcom,qos-cpu-latency-us = <300>;
vdda-1p2-supply = <&L6B>;
vdda-0p9-supply = <&L1B>;
vdd_mx-supply = <&VDD_MXA_LEVEL>;
qcom,hbr-rbr-voltage-swing = <0x07 0x0f 0x16 0x1f>,
<0x11 0x1e 0x1f 0xff>,
<0x16 0x1f 0xff 0xff>,
<0x1f 0xff 0xff 0xff>;
qcom,hbr-rbr-pre-emphasis = <0x00 0x0d 0x14 0x1a>,
<0x00 0x0e 0x15 0xff>,
<0x00 0x0e 0xff 0xff>,
<0x02 0xff 0xff 0xff>;
qcom,hbr2-3-voltage-swing = <0x02 0x12 0x16 0x1a>,
<0x09 0x19 0x1f 0xff>,
<0x10 0x1f 0xff 0xff>,
<0x1f 0xff 0xff 0xff>;
qcom,hbr2-3-pre-emphasis = <0x00 0x0c 0x15 0x1b>,
<0x02 0x0e 0x16 0xff>,
<0x02 0x11 0xff 0xff>,
<0x04 0xff 0xff 0xff>;
qcom,ctrl-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,ctrl-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdda-1p2";
qcom,supply-min-voltage = <1200000>;
qcom,supply-max-voltage = <1200000>;
qcom,supply-enable-load = <21700>;
qcom,supply-disable-load = <0>;
};
};
qcom,phy-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,phy-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdda-0p9";
qcom,supply-min-voltage = <912000>;
qcom,supply-max-voltage = <912000>;
qcom,supply-enable-load = <115000>;
qcom,supply-disable-load = <0>;
};
};
qcom,core-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,core-supply-entry@0 {
reg = <0>;
qcom,supply-name = "refgen";
qcom,supply-min-voltage = <0>;
qcom,supply-max-voltage = <0>;
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
};
};
qcom,pll-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,pll-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdd_mx";
qcom,supply-min-voltage =
<RPMH_REGULATOR_LEVEL_TURBO>;
qcom,supply-max-voltage =
<RPMH_REGULATOR_LEVEL_MAX>;
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
};
};
};
...

130
bindings/sde-dsi.txt
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@@ -1,130 +0,0 @@
Qualcomm Technologies, Inc.
mdss-dsi is the master DSI device which supports multiple DSI host controllers
that are compatible with MIPI display serial interface specification.
DSI Controller and PHY:
Required properties:
- compatible: Should be "qcom,dsi-ctrl-hw-v<version>". Supported
versions include 2.4, 2.5, and 2.6.
eg: qcom,dsi-ctrl-hw-v2.2, qcom,dsi-ctrl-hw-v2.3,
qcom,dsi-ctrl-hw-v2.4, qcom,dsi-ctrl-hw-v2.5,
qcom,dsi-ctrl-hw-v2.6
And for dsi phy driver:
qcom,dsi-phy-v3.0, qcom,dsi-phy-v4.0,
qcom,dsi-phy-v4.1, qcom,dsi-phy-v4.2
- reg: List of base address and length of memory mapped
regions of DSI controller, disp_cc and mdp_intf.
- reg-names: A list of strings that name the list of regs.
"dsi_ctrl" - DSI controller memory region.
"disp_cc_base" - Base address of disp_cc memory region.
"mdp_intf_base" - Base address of mdp_intf memory region.
- cell-index: Specifies the controller instance.
- clocks: Clocks required for DSI controller operation.
- clock-names: Names of the clocks corresponding to handles. Following
clocks are required:
"mdp_core_clk"
"iface_clk"
"core_mmss_clk"
"bus_clk"
"byte_clk"
"pixel_clk"
"core_clk"
"byte_clk_rcg"
"pixel_clk_rcg"
- pll-label Supported versions of DSI PLL:
dsi_pll_5nm
- gdsc-supply: phandle to gdsc regulator node.
- vdda-supply: phandle to vdda regulator node.
- vcca-supply: phandle to vcca regulator node.
- interrupt-parent phandle to the interrupt parent device node.
- interrupts: The interrupt signal from the DSI block.
- qcom,dsi-default-panel: Specifies the default panel.
- qcom,mdp: Specifies the mdp node which can find panel node from this.
- qcom,demura-panel-id: Specifies the u64 demura panel ID as an array <2>
If demura is not used this node must be set to <0,0>.
Bus Scaling Data:
- qcom,msm-bus,name: String property describing MDSS client.
- qcom,msm-bus,num-cases: This is the number of bus scaling use cases
defined in the vectors property. This must be
set to <2> for MDSS DSI driver where use-case 0
is used to remove BW votes from the system. Use
case 1 is used to generate bandwidth requestes
when sending command packets.
- qcom,msm-bus,num-paths: This represents number of paths in each bus
scaling usecase. This value depends on number of
AXI master ports dedicated to MDSS for
particular chipset.
- qcom,msm-bus,vectors-KBps: A series of 4 cell properties, with a format
of (src, dst, ab, ib) which is defined at
Documentation/devicetree/bindings/arm/msm/msm_bus.txt.
DSI driver should always set average bandwidth
(ab) to 0 and always use instantaneous
bandwidth(ib) values.
Optional properties:
- label: String to describe controller.
- qcom,platform-te-gpio: Specifies the gpio used for TE.
- qcom,panel-te-source: Specifies the source pin for Vsync from panel or WD Timer.
- qcom,dsi-ctrl: handle to dsi controller device
- qcom,dsi-phy: handle to dsi phy device
- qcom,dsi-ctrl-num: Specifies the DSI controllers to use for primary panel
- qcom,dsi-sec-ctrl-num: Specifies the DSI controllers to use for secondary panel
- qcom,dsi-phy-num: Specifies the DSI PHYs to use for primary panel
- qcom,dsi-sec-phy-num: Specifies the DSI PHYs to use for secondary panel
- qcom,dsi-select-clocks: Specifies the required clocks to use for primary panel
- qcom,dsi-select-sec-clocks: Specifies the required clocks to use for secondary panel
- qcom,dsi-display-list: Specifies the list of supported displays.
- qcom,dsi-manager: Specifies dsi manager is present
- qcom,dsi-display: Specifies dsi display is present
- qcom,hdmi-display: Specifies hdmi is present
- qcom,dp-display: Specified dp is present
- qcom,<type>-supply-entries: A node that lists the elements of the supply used by the
a particular "type" of DSI module. The module "types"
can be "core", "ctrl", and "phy". Within the same type,
there can be more than one instance of this binding,
in which case the entry would be appended with the
supply entry index.
e.g. qcom,ctrl-supply-entry@0
-- qcom,supply-name: name of the supply (vdd/vdda/vddio)
-- qcom,supply-min-voltage: minimum voltage level (uV)
-- qcom,supply-max-voltage: maximum voltage level (uV)
-- qcom,supply-enable-load: load drawn (uA) from enabled supply
-- qcom,supply-disable-load: load drawn (uA) from disabled supply
-- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on
-- qcom,supply-post-on-sleep: time to sleep (ms) after turning on
-- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off
-- qcom,supply-post-off-sleep: time to sleep (ms) after turning off
- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode
panels in microseconds. Driver uses this number to adjust
the clock rate according to the expected transfer time.
Increasing this value would slow down the mdp processing
and can result in slower performance.
Decreasing this value can speed up the mdp processing,
but this can also impact power consumption.
As a rule this time should not be higher than the time
that would be expected with the processing at the
dsi link rate since anyways this would be the maximum
transfer time that could be achieved.
If ping pong split enabled, this time should not be higher
than two times the dsi link rate time.
If the property is not specified, then the default value is 14000 us.
- qcom,dsi-phy-pll-bypass: A boolean property that enables bypassing hardware access in DSI
PHY/PLL drivers to allow the DSI driver to run on emulation platforms
that might be missing those modules.
- - qcom,null-insertion-enabled: A boolean to enable NULL packet insertion feature for DSI controller.
- ports: This video port is used when external bridge is present.
The connection is modeled using the OF graph bindings
specified in Documentation/devicetree/bindings/graph.txt.
Video port 0 reg 0 is for the bridge output. The remote
endpoint phandle should be mipi_dsi_device device node.
- qcom,dsi-pll-ssc-en: Boolean property to indicate that ssc is enabled.
- qcom,dsi-pll-ssc-mode: Spread-spectrum clocking. It can be either "down-spread"
or "center-spread". Default is "down-spread" if it is not specified.
- qcom,ssc-frequency-hz: Integer property to specify the spread frequency
to be programmed for the SSC.
- qcom,ssc-ppm: Integer property to specify the Parts per Million
value of SSC.
- qcom,avdd-regulator-gpio: Specifies the gpio pin used for avdd
power supply regulator.

360
bindings/sde-dsi.yaml Normal file
View File

@@ -0,0 +1,360 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sde-dsi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MDSS DSI
description: |
mdss-dsi is the master DSI device which supports multiple DSI host controllers
that are compatible with MIPI display serial interface specification.
maintainers:
- Vara Reddy <quic_varar@quicinc.com>
- Vishnuvardhan Prodduturi <quic_vproddut@quicinc.com>
pattern properties:
"qcom,+\w+\-supply\-entries":
description: |
A node that lists the elements of the supply used by the
a particular "type" of DSI module. The module "types"
can be "core", "ctrl", and "phy". Within the same type,
there can be more than one instance of this binding,
in which case the entry would be appended with the
supply entry index.
e.g. qcom,ctrl-supply-entry@0
type: object
patternProperties:
"qcom,ctrl\-supply\-entry\@+\w":
properties:
reg:
description: offset and length of the register set for the device.
qcom,supply-name:
description: name of the supply (vdd/vdda/vddio)
$ref: /schemas/types.yaml#/definitions/string-array
qcom,supply-min-voltage:
description: minimum voltage level (uV)
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-max-voltage:
description: maximum voltage level (uV)
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-enable-load:
description: load drawn (uA) from enabled supply
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-disable-load:
description: load drawn (uA) from disabled supply
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-pre-on-sleep:
description: time to sleep (ms) before turning on
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-post-on-sleep:
description: time to sleep (ms) after turning on
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-pre-off-sleep:
description: time to sleep (ms) before turning off
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-post-off-sleep:
description: time to sleep (ms) after turning off
$ref: /schemas/types.yaml#/definitions/uint32
"qcom,core\-supply\-entry\@+\w":
properties:
reg:
description: offset and length of the register set for the device.
qcom,supply-name:
description: name of the supply (vdd/vdda/vddio)
$ref: /schemas/types.yaml#/definitions/string-array
qcom,supply-min-voltage:
description: minimum voltage level (uV)
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-max-voltage:
description: maximum voltage level (uV)
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-enable-load:
description: load drawn (uA) from enabled supply
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-disable-load:
description: load drawn (uA) from disabled supply
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-pre-on-sleep:
description: time to sleep (ms) before turning on
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-post-on-sleep:
description: time to sleep (ms) after turning on
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-pre-off-sleep:
description: time to sleep (ms) before turning off
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-post-off-sleep:
description: time to sleep (ms) after turning off
$ref: /schemas/types.yaml#/definitions/uint32
"qcom,phy\-supply\-entry\@+\w":
properties:
reg:
description: offset and length of the register set for the device.
qcom,supply-name:
description: name of the supply (vdd/vdda/vddio)
$ref: /schemas/types.yaml#/definitions/string-array
qcom,supply-min-voltage:
description: minimum voltage level (uV)
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-max-voltage:
description: maximum voltage level (uV)
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-enable-load:
description: load drawn (uA) from enabled supply
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-disable-load:
description: load drawn (uA) from disabled supply
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-pre-on-sleep:
description: time to sleep (ms) before turning on
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-post-on-sleep:
description: time to sleep (ms) after turning on
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-pre-off-sleep:
description: time to sleep (ms) before turning off
$ref: /schemas/types.yaml#/definitions/uint32
qcom,supply-post-off-sleep:
description: time to sleep (ms) after turning off
$ref: /schemas/types.yaml#/definitions/uint32
properties:
compatible:
enum:
- qcom,dsi-ctrl-hw-v2.4
- qcom,dsi-ctrl-hw-v2.5
- qcom,dsi-ctrl-hw-v2.6
- qcom,dsi-ctrl-hw-v2.7
- qcom,dsi-ctrl-hw-v2.8
- qcom,dsi-ctrl-hw-v2.9
- qcom,dsi-phy-v3.0
- qcom,dsi-phy-v4.0
- qcom,dsi-phy-v4.1
- qcom,dsi-phy-v4.2
- qcom,dsi-phy-v4.3
- qcom,dsi-phy-v4.3.2
- qcom,dsi-phy-v5.2
- qcom,dsi-phy-v7.2
reg:
description: |
List of base address and length of memory mapped
regions of DSI controller, disp_cc and mdp_intf.
reg-names:
items:
- const: dsi_ctrl
- const: disp_cc_base
- const: mdp_intf_base
cell-index:
description: Specifies the controller instance.
clocks:
items:
- const: mdp_core_clk
- const: iface_clk
- const: core_mmss_clk
- const: bus_clk
- const: byte_clk
- const: pixel_clk
- const: core_clk
- const: byte_clk_rcg
- const: pixel_clk_rcg
pll-label:
description: Supported versions of DSI PLL.
$ref: /schemas/types.yaml#/definitions/string-array
enum: [dsi_pll_5nm, dsi_pll_4nm, dsi_pll_3nm]
gdsc-supply:
description: phandle to gdsc regulator node.
$ref: /schemas/types.yaml#/definitions/phandle
vdda-supply:
description: phandle to vdda regulator node.
$ref: /schemas/types.yaml#/definitions/phandle
vcca-supply:
description: phandle to vcca regulator node.
$ref: /schemas/types.yaml#/definitions/phandle
interrupt-parent:
description: phandle to the interrupt parent device node.
$ref: /schemas/types.yaml#/definitions/phandle
interrupts:
description: The interrupt signal from the DSI block.
qcom,dsi-default-panel:
description: Specifies the default panel.
qcom,mdp:
description: Specifies the mdp node which can find panel node from this.
qcom,demura-panel-id:
description: |
Specifies the u64 demura panel ID as an array <2>
If demura is not used this node must be set to <0,0>.
$ref: /schemas/types.yaml#/definitions/uint64
qcom,msm-bus,name:
description: String property describing MDSS client.
$ref: /schemas/types.yaml#/definitions/string-array
qcom,msm-bus,num-cases:
description: |
This is the number of bus scaling use cases
defined in the vectors property. This must be
set to <2> for MDSS DSI driver where use-case 0
is used to remove BW votes from the system. Use
case 1 is used to generate bandwidth requestes
when sending command packets.
qcom,msm-bus,num-paths:
description: |
This represents number of paths in each bus
scaling usecase. This value depends on number of
AXI master ports dedicated to MDSS for
particular chipset.
qcom,msm-bus,vectors-KBps:
description: |
A series of 4 cell properties, with a format
of (src, dst, ab, ib) which is defined at
Documentation/devicetree/bindings/arm/msm/msm_bus.txt.
DSI driver should always set average bandwidth
(ab) to 0 and always use instantaneous
bandwidth(ib) values.
label:
description: String to describe controller.
$ref: /schemas/types.yaml#/definitions/string-array
qcom,platform-te-gpio:
description: Specifies the gpio used for TE.
qcom,panel-te-source:
description: Specifies the source pin for Vsync from panel or WD Timer.
qcom,dsi-ctrl:
description: handle to dsi controller device
qcom,dsi-phy:
description: handle to dsi phy device
qcom,dsi-ctrl-num:
description: Specifies the DSI controllers to use for primary panel
qcom,dsi-sec-ctrl-num:
description: Specifies the DSI controllers to use for secondary panel
qcom,dsi-phy-num:
description: Specifies the DSI PHYs to use for primary panel
qcom,dsi-sec-phy-num:
description: Specifies the DSI PHYs to use for secondary panel
qcom,dsi-select-clocks:
description: Specifies the required clocks to use for primary panel
qcom,dsi-select-sec-clocks:
description: Specifies the required clocks to use for secondary panel
qcom,dsi-display-list:
description: Specifies the list of supported displays.
$ref: /schemas/types.yaml#/definitions/string-array
qcom,dsi-manager:
description: Specifies dsi manager is present
qcom,dsi-display:
description: Specifies dsi display is present
qcom,hdmi-display:
description: Specifies hdmi is present
qcom,dp-display:
description: Specified dp is present
qcom,mdss-mdp-transfer-time-us:
description: |
Specifies the dsi transfer time for command mode
panels in microseconds. Driver uses this number to adjust
the clock rate according to the expected transfer time.
Increasing this value would slow down the mdp processing
and can result in slower performance.
Decreasing this value can speed up the mdp processing,
but this can also impact power consumption.
As a rule this time should not be higher than the time
that would be expected with the processing at the
dsi link rate since anyways this would be the maximum
transfer time that could be achieved.
If ping pong split enabled, this time should not be higher
than two times the dsi link rate time.
If the property is not specified, then the default value is 14000 us.
qcom,dsi-phy-pll-bypass:
description: |
A boolean property that enables bypassing hardware access in DSI
PHY/PLL drivers to allow the DSI driver to run on emulation platforms
that might be missing those modules.
qcom,null-insertion-enabled:
description: A boolean to enable NULL packet insertion feature for DSI controller.
ports:
description: |
This video port is used when external bridge is present.
The connection is modeled using the OF graph bindings
specified in Documentation/devicetree/bindings/graph.txt.
Video port 0 reg 0 is for the bridge output. The remote
endpoint phandle should be mipi_dsi_device device node.
qcom,dsi-pll-ssc-en:
description: Boolean property to indicate that ssc is enabled.
qcom,dsi-pll-ssc-mode:
description: |
Spread-spectrum clocking. It can be either "down-spread"
or "center-spread". Default is "down-spread" if it is not specified.
$ref: /schemas/types.yaml#/definitions/string-array
default: down-spread
enum: [down-spread, center-spread]
qcom,ssc-frequency-hz:
description: |
Integer property to specify the spread frequency
to be programmed for the SSC.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,ssc-ppm:
description: Integer property to specify the Parts per Million value of SSC.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,avdd-regulator-gpio:
description: Specifies the gpio pin used for avdd power supply regulator.
required:
- compatible
- reg
- reg-names
- cell-index
- clocks
- clock-names
- pll-label
- gdsc-supply
- vdda-supply
- vcca-supply
- interrupt-parent
- qcom,dsi-default-panel
- qcom,mdp
- qcom,demura-panel-id
- qcom,msm-bus,name
- qcom,msm-bus,num-cases
- qcom,msm-bus,num-paths
- qcom,msm-bus,vectors-KBps
...

23
bindings/sde-wb.txt
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@@ -1,23 +0,0 @@
Qualcomm Technologies, Inc. Snapdragon Display Engine (SDE) writeback display
Required properties:
- compatible: "qcom,wb-display"
Optional properties:
- cell-index: Index of writeback device instance.
Default to 0 if not specified.
- label: String to describe this writeback display.
Default to "unknown" if not specified.
Example:
/ {
...
sde_wb: qcom,wb-display {
compatible = "qcom,wb-display";
cell-index = <2>;
label = "wb_display";
};
};

36
bindings/sde-wb.yaml Normal file
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@@ -0,0 +1,36 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sde-wb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Snapdragon Display Engine (SDE) writeback display
maintainers:
- Veera Sundaram Sankaran <quic_veeras@quicinc.com>
- Kalyan Thota <quic_kalyant@quicinc.com>
- Ravi Teja Tamatam <quic_travitej@quicinc.com>
properties:
compatible:
const: qcom,wb-display
cell-index:
description: Index of writeback device instance. Default to 0 if not specified.
default: 0
label:
description: String to describe this writeback display. Default to "unknown" if not specified.
default: "unknown"
required:
- compatible
examples:
- |
sde_wb: qcom,wb-display {
compatible = "qcom,wb-display";
cell-index = <2>;
label = "wb_display";
};
...

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bindings/sde.txt
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51
display/dsi-panel-ext-bridge-1080p.dtsi Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&mdss_mdp {
dsi_ext_bridge_1080p: qcom,mdss_dsi_ext_bridge_1080p {
qcom,mdss-dsi-panel-name = "ext video mode dsi bridge";
qcom,mdss-dsi-panel-type = "dsi_video_mode";
qcom,dsi-ctrl-num = <0>;
qcom,dsi-phy-num = <0>;
qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
qcom,mdss-dsi-virtual-channel-id = <0>;
qcom,mdss-dsi-stream = <0>;
qcom,mdss-dsi-bpp = <24>;
qcom,mdss-dsi-border-color = <0>;
qcom,mdss-dsi-traffic-mode = "non_burst_sync_pulse";
qcom,mdss-dsi-bllp-eof-power-mode;
qcom,mdss-dsi-bllp-power-mode;
qcom,mdss-dsi-lane-0-state;
qcom,mdss-dsi-lane-1-state;
qcom,mdss-dsi-lane-2-state;
qcom,mdss-dsi-lane-3-state;
qcom,mdss-dsi-dma-trigger = "trigger_sw";
qcom,mdss-dsi-mdp-trigger = "none";
qcom,mdss-dsi-t-clk-post = <0x03>;
qcom,mdss-dsi-t-clk-pre = <0x24>;
qcom,mdss-dsi-force-clock-lane-hs;
qcom,mdss-dsi-ext-bridge-mode;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-width = <1920>;
qcom,mdss-dsi-panel-height = <1080>;
qcom,mdss-dsi-h-front-porch = <88>;
qcom,mdss-dsi-h-back-porch = <148>;
qcom,mdss-dsi-h-pulse-width = <44>;
qcom,mdss-dsi-h-sync-skew = <0>;
qcom,mdss-dsi-v-back-porch = <36>;
qcom,mdss-dsi-v-front-porch = <4>;
qcom,mdss-dsi-v-pulse-width = <5>;
qcom,mdss-dsi-h-sync-pulse = <0>;
qcom,mdss-dsi-panel-framerate = <60>;
qcom,display-topology = <1 0 1>;
qcom,default-topology-index = <0>;
};
};
};
};

574
display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&mdss_mdp {
dsi_nt37801_amoled_fhd_plus_cmd: qcom,mdss_dsi_nt37801_fhd_plus_cmd {
qcom,mdss-dsi-panel-name =
"nt37801 amoled fhd plus cmd mode dsi csot panel with DSC";
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
qcom,mdss-dsi-panel-physical-type = "oled";
qcom,mdss-dsi-virtual-channel-id = <0>;
qcom,mdss-dsi-stream = <0>;
qcom,mdss-dsi-bpp = <24>;
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
qcom,mdss-dsi-underflow-color = <0xff>;
qcom,mdss-dsi-border-color = <0>;
qcom,dsi-ctrl-num = <0>;
qcom,dsi-phy-num = <0>;
qcom,dsi-sec-ctrl-num = <1>;
qcom,dsi-sec-phy-num = <1>;
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
qcom,mdss-dsi-lane-map = "lane_map_0123";
qcom,mdss-dsi-bllp-eof-power-mode;
qcom,mdss-dsi-bllp-power-mode;
qcom,mdss-dsi-lane-0-state;
qcom,mdss-dsi-lane-1-state;
qcom,mdss-dsi-lane-2-state;
qcom,mdss-dsi-lane-3-state;
qcom,mdss-dsi-dma-trigger = "trigger_sw";
qcom,mdss-dsi-mdp-trigger = "none";
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
qcom,mdss-dsi-te-pin-select = <1>;
qcom,mdss-dsi-wr-mem-start = <0x2c>;
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
qcom,mdss-dsi-te-dcs-command = <1>;
qcom,mdss-dsi-te-check-enable;
qcom,mdss-dsi-te-using-te-pin;
qcom,spr-pack-type = "pentile";
qcom,mdss-dsi-display-timings {
timing@0 {
cell-index = <0>;
qcom,mdss-dsi-panel-framerate = <120>;
qcom,mdss-dsi-panel-width = <1080>;
qcom,mdss-dsi-panel-height = <2400>;
qcom,mdss-dsi-h-front-porch = <20>;
qcom,mdss-dsi-h-back-porch = <20>;
qcom,mdss-dsi-h-pulse-width = <4>;
qcom,mdss-dsi-h-sync-skew = <0>;
qcom,mdss-dsi-v-back-porch = <18>;
qcom,mdss-dsi-v-front-porch = <20>;
qcom,mdss-dsi-v-pulse-width = <2>;
qcom,mdss-dsi-h-left-border = <0>;
qcom,mdss-dsi-h-right-border = <0>;
qcom,mdss-dsi-v-top-border = <0>;
qcom,mdss-dsi-v-bottom-border = <0>;
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
qcom,mdss-dsi-timing-switch-command = [
39 01 00 00 00 00 05 2A 00 00 04 37
39 01 00 00 00 00 05 2B 00 00 09 5F
39 01 00 00 00 00 02 8F 01
39 01 00 00 00 00 02 2f 00
39 01 00 00 00 00 02 26 00
39 01 00 00 00 00 06 f0 55 aa 52 08 00
39 01 00 00 00 00 06 c0 54 c0 00 21 43
39 01 00 00 00 00 06 f0 55 aa 52 08 02
39 01 00 00 00 00 02 cc 30
39 01 00 00 00 00 02 ce 01
39 01 00 00 20 00 02 cc 00
];
qcom,mdss-dsi-on-command = [
39 01 00 00 00 00 06 F0 55 AA 52 08 01
39 01 00 00 00 00 02 6F 01
39 01 00 00 00 00 04 C5 0B 0B 0B
39 01 00 00 00 00 05 FF AA 55 A5 80
39 01 00 00 00 00 02 6F 02
39 01 00 00 00 00 02 F5 10
39 01 00 00 00 00 02 6F 1B
39 01 00 00 00 00 02 F4 55
39 01 00 00 00 00 02 6F 18
39 01 00 00 00 00 02 F8 19
39 01 00 00 00 00 02 6F 0F
39 01 00 00 00 00 02 FC 00
39 01 00 00 00 00 05 2A 00 00 04 37
39 01 00 00 00 00 05 2B 00 00 09 5F
39 01 00 00 00 00 02 90 03
39 01 00 00 00 00 13 91 89 28 00 28 c2
00 02 0e 03 dd 00 07 02 77 02 8B 10
f0
39 01 00 00 00 00 05 ff aa 55 a5 81
39 01 00 00 00 00 02 6f 23
39 01 00 00 00 00 15 fb 00 01 00 11 33
33 33 55 57 d0 00 00 44 56 77 78 9a
bc dd f0
39 01 00 00 00 00 13 93 89 28 00 28 D2 00 02 25 03 B6 00 07 02 AB 02 8B 10 F0
39 01 00 00 00 00 13 95 89 28 00 28 D2 00 01 C3 02 FC 00 05 02 AB 03 D1 10 F0
39 01 00 00 00 00 02 03 00
39 01 00 00 00 00 02 8F 01
39 01 00 00 00 00 02 6F 06
39 01 00 00 00 00 02 F3 DC
39 01 00 00 00 00 02 26 00
39 01 00 00 00 00 02 35 00
39 01 00 00 00 00 05 3B 00 18 00 10
39 01 00 00 00 00 02 53 20
39 01 00 00 00 00 07 51 07 FF 07 FF 0F FF
39 01 00 00 00 00 02 5A 01
39 01 00 00 00 00 02 5F 00
39 01 00 00 00 00 02 9C 01
05 01 00 00 00 00 01 2C
39 01 00 00 00 00 02 2F 00
05 01 00 00 78 00 01 11
05 01 00 00 14 00 01 29
];
qcom,mdss-dsi-off-command = [
05 01 00 00 14 00 02 28 00
05 01 00 00 78 00 02 10 00];
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
qcom,mdss-dsi-timing-switch-command-state =
"dsi_lp_mode";
qcom,mdss-dsi-h-sync-pulse = <0>;
qcom,compression-mode = "dsc";
qcom,mdss-dsc-slice-height = <40>;
qcom,mdss-dsc-slice-width = <540>;
qcom,mdss-dsc-slice-per-pkt = <1>;
qcom,mdss-dsc-bit-per-component = <8>;
qcom,mdss-dsc-bit-per-pixel = <8>;
qcom,mdss-dsc-block-prediction-enable;
};
timing@1 {
cell-index = <1>;
qcom,mdss-dsi-panel-framerate = <90>;
qcom,mdss-dsi-panel-width = <1080>;
qcom,mdss-dsi-panel-height = <2400>;
qcom,mdss-dsi-h-front-porch = <20>;
qcom,mdss-dsi-h-back-porch = <20>;
qcom,mdss-dsi-h-pulse-width = <4>;
qcom,mdss-dsi-h-sync-skew = <0>;
qcom,mdss-dsi-v-back-porch = <18>;
qcom,mdss-dsi-v-front-porch = <20>;
qcom,mdss-dsi-v-pulse-width = <2>;
qcom,mdss-dsi-h-left-border = <0>;
qcom,mdss-dsi-h-right-border = <0>;
qcom,mdss-dsi-v-top-border = <0>;
qcom,mdss-dsi-v-bottom-border = <0>;
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
qcom,mdss-dsi-panel-clockrate = <680000000>;
qcom,mdss-dsi-timing-switch-command = [
39 01 00 00 00 00 05 2a 00 00 04 37
39 01 00 00 00 00 05 2b 00 00 09 5f
39 01 00 00 00 00 02 8f 01
39 01 00 00 00 00 02 2f 01
39 01 00 00 00 00 02 26 01
39 01 00 00 00 00 06 f0 55 aa 52 08 00
39 01 00 00 00 00 06 c0 54 c0 00 24 45
39 01 00 00 00 00 06 f0 55 aa 52 08 02
39 01 00 00 00 00 02 cc 30
39 01 00 00 00 00 02 ce 01
39 01 00 00 20 00 02 cc 00
];
qcom,mdss-dsi-on-command = [
39 01 00 00 00 00 06 F0 55 AA 52 08 01
39 01 00 00 00 00 02 6F 01
39 01 00 00 00 00 04 C5 0B 0B 0B
39 01 00 00 00 00 05 FF AA 55 A5 80
39 01 00 00 00 00 02 6F 06
39 01 00 00 00 00 02 F3 DC
39 01 00 00 00 00 02 6F 02
39 01 00 00 00 00 02 F5 10
39 01 00 00 00 00 02 6F 1B
39 01 00 00 00 00 02 F4 55
39 01 00 00 00 00 02 6F 18
39 01 00 00 00 00 02 F8 19
39 01 00 00 00 00 02 6F 0F
39 01 00 00 00 00 02 FC 00
39 01 00 00 00 00 05 2a 00 00 04 37
39 01 00 00 00 00 05 2b 00 00 09 5f
39 01 00 00 00 00 02 90 03
39 01 00 00 00 00 13 91 89 28 00 28 c2
00 02 0e 03 dd 00 07 02 77 02 8B 10
f0
39 01 00 00 00 00 05 ff aa 55 a5 81
39 01 00 00 00 00 02 6f 23
39 01 00 00 00 00 15 fb 00 01 00 11 33
33 33 55 57 d0 00 00 44 56 77 78 9a
bc dd f0
39 01 00 00 00 00 02 35 00
39 01 00 00 00 00 05 3B 00 18 00 10
39 01 00 00 00 00 02 53 20
39 01 00 00 00 00 07 51 07 FF 07 FF 0F
FF
39 01 00 00 00 00 02 5A 01
39 01 00 00 00 00 02 5F 00
39 01 00 00 00 00 02 9C 01
05 01 00 00 00 00 01 2C
39 01 00 00 00 00 02 2f 01
39 01 00 00 00 00 02 26 01
39 01 00 00 00 00 06 f0 55 aa 52 08 00
39 01 00 00 00 00 06 c0 54 c0 00 24 45
39 01 00 00 00 00 06 f0 55 aa 52 08 02
39 01 00 00 00 00 02 cc 30
39 01 00 00 00 00 02 ce 01
39 01 00 00 20 00 02 cc 00
39 01 00 00 00 00 06 F0 55 AA 52 08 01
39 01 00 00 00 00 05 B2 55 01 FF 03
05 01 00 00 78 00 01 11
05 01 00 00 14 00 01 29
];
qcom,mdss-dsi-off-command = [
05 01 00 00 14 00 02 28 00
05 01 00 00 78 00 02 10 00];
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
qcom,mdss-dsi-timing-switch-command-state =
"dsi_lp_mode";
qcom,mdss-dsi-h-sync-pulse = <0>;
qcom,compression-mode = "dsc";
qcom,mdss-dsc-slice-height = <40>;
qcom,mdss-dsc-slice-width = <540>;
qcom,mdss-dsc-slice-per-pkt = <1>;
qcom,mdss-dsc-bit-per-component = <8>;
qcom,mdss-dsc-bit-per-pixel = <8>;
qcom,mdss-dsc-block-prediction-enable;
};
timing@2 {
cell-index = <2>;
qcom,mdss-dsi-panel-framerate = <60>;
qcom,mdss-dsi-panel-width = <1080>;
qcom,mdss-dsi-panel-height = <2400>;
qcom,mdss-dsi-h-front-porch = <20>;
qcom,mdss-dsi-h-back-porch = <20>;
qcom,mdss-dsi-h-pulse-width = <4>;
qcom,mdss-dsi-h-sync-skew = <0>;
qcom,mdss-dsi-v-back-porch = <18>;
qcom,mdss-dsi-v-front-porch = <20>;
qcom,mdss-dsi-v-pulse-width = <2>;
qcom,mdss-dsi-h-left-border = <0>;
qcom,mdss-dsi-h-right-border = <0>;
qcom,mdss-dsi-v-top-border = <0>;
qcom,mdss-dsi-v-bottom-border = <0>;
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
qcom,mdss-dsi-panel-clockrate = <680000000>;
qcom,mdss-dsi-timing-switch-command = [
39 01 00 00 00 00 05 2a 00 00 04 37
39 01 00 00 00 00 05 2b 00 00 09 5f
39 01 00 00 00 00 02 8f 01
39 01 00 00 00 00 02 2f 00
39 01 00 00 00 00 02 26 01
39 01 00 00 00 00 02 5a 01
39 01 00 00 00 00 02 2f 30
39 01 00 00 00 00 06 f0 55 aa 52 08 00
39 01 00 00 00 00 02 6f 1c
39 01 00 00 00 00 09 ba 91 01 01 00 01
01 01 00
39 01 00 00 00 00 06 f0 55 aa 52 08 00
39 01 00 00 00 00 06 c0 54 c0 00 21 43
39 01 00 00 00 00 06 f0 55 aa 52 08 02
39 01 00 00 00 00 02 cc 30
39 01 00 00 00 00 02 ce 01
39 01 00 00 20 00 02 cc 00
];
qcom,mdss-dsi-on-command = [
39 01 00 00 00 00 06 F0 55 AA 52 08 01
39 01 00 00 00 00 02 6F 01
39 01 00 00 00 00 04 C5 0B 0B 0B
39 01 00 00 00 00 05 FF AA 55 A5 80
39 01 00 00 00 00 02 6F 02
39 01 00 00 00 00 02 F5 10
39 01 00 00 00 00 02 6F 1B
39 01 00 00 00 00 02 F4 55
39 01 00 00 00 00 02 6F 18
39 01 00 00 00 00 02 F8 19
39 01 00 00 00 00 02 6F 0F
39 01 00 00 00 00 02 FC 00
39 01 00 00 00 00 05 2a 00 00 04 37
39 01 00 00 00 00 05 2b 00 00 09 5f
39 01 00 00 00 00 02 90 03
39 01 00 00 00 00 13 91 89 28 00 28 c2
00 02 0e 03 dd 00 07 02 77 02 8B 10
f0
39 01 00 00 00 00 05 ff aa 55 a5 81
39 01 00 00 00 00 02 6f 23
39 01 00 00 00 00 15 fb 00 01 00 11 33
33 33 55 57 d0 00 00 44 56 77 78 9a
bc dd f0
39 01 00 00 00 00 02 6F 06
39 01 00 00 00 00 02 F3 DC
39 01 00 00 00 00 02 26 00
39 01 00 00 00 00 02 35 00
39 01 00 00 00 00 05 3B 00 18 00 10
39 01 00 00 00 00 02 53 20
39 01 00 00 00 00 07 51 07 FF 07 FF 0F
FF
39 01 00 00 00 00 02 5A 01
39 01 00 00 00 00 02 5F 00
39 01 00 00 00 00 02 9C 01
05 01 00 00 00 00 01 2C
39 01 00 00 00 00 02 2f 00
39 01 00 00 00 00 02 26 01
39 01 00 00 00 00 02 5a 01
39 01 00 00 00 00 02 2f 30
39 01 00 00 00 00 06 f0 55 aa 52 08 00
39 01 00 00 00 00 02 6f 1c
39 01 00 00 00 00 09 ba 91 01 01 00 01
01 01 00
39 01 00 00 00 00 06 f0 55 aa 52 08 00
39 01 00 00 00 00 06 c0 54 c0 00 21 43
39 01 00 00 00 00 06 f0 55 aa 52 08 02
39 01 00 00 00 00 02 cc 30
39 01 00 00 00 00 02 ce 01
39 01 00 00 20 00 02 cc 00
39 01 00 00 00 00 06 F0 55 AA 52 08 01
39 01 00 00 00 00 05 B2 55 01 FF 03
05 01 00 00 78 00 01 11
05 01 00 00 14 00 01 29
];
qcom,mdss-dsi-off-command = [
05 01 00 00 14 00 02 28 00
05 01 00 00 78 00 02 10 00];
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
qcom,mdss-dsi-timing-switch-command-state =
"dsi_lp_mode";
qcom,mdss-dsi-h-sync-pulse = <0>;
qcom,compression-mode = "dsc";
qcom,mdss-dsc-slice-height = <40>;
qcom,mdss-dsc-slice-width = <540>;
qcom,mdss-dsc-slice-per-pkt = <1>;
qcom,mdss-dsc-bit-per-component = <8>;
qcom,mdss-dsc-bit-per-pixel = <8>;
qcom,mdss-dsc-block-prediction-enable;
};
timing@3 {
cell-index = <3>;
qcom,mdss-dsi-panel-framerate = <40>;
qcom,mdss-dsi-panel-width = <1080>;
qcom,mdss-dsi-panel-height = <2400>;
qcom,mdss-dsi-h-front-porch = <20>;
qcom,mdss-dsi-h-back-porch = <20>;
qcom,mdss-dsi-h-pulse-width = <4>;
qcom,mdss-dsi-h-sync-skew = <0>;
qcom,mdss-dsi-v-back-porch = <18>;
qcom,mdss-dsi-v-front-porch = <20>;
qcom,mdss-dsi-v-pulse-width = <2>;
qcom,mdss-dsi-h-left-border = <0>;
qcom,mdss-dsi-h-right-border = <0>;
qcom,mdss-dsi-v-top-border = <0>;
qcom,mdss-dsi-v-bottom-border = <0>;
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
qcom,mdss-dsi-panel-clockrate = <680000000>;
qcom,mdss-dsi-timing-switch-command = [
39 01 00 00 00 00 05 2a 00 00 04 37
39 01 00 00 00 00 05 2b 00 00 09 5f
39 01 00 00 00 00 02 8f 01
39 01 00 00 00 00 02 2f 00
39 01 00 00 00 00 02 26 01
39 01 00 00 00 00 02 5a 01
39 01 00 00 00 00 02 2f 30
39 01 00 00 00 00 06 f0 55 aa 52 08 00
39 01 00 00 00 00 02 6f 1c
39 01 00 00 00 00 09 ba 91 02 02 00 01
02 02 00
39 01 00 00 00 00 06 f0 55 aa 52 08 00
39 01 00 00 00 00 06 c0 54 c0 00 21 43
39 01 00 00 00 00 06 f0 55 aa 52 08 02
39 01 00 00 00 00 02 cc 30
39 01 00 00 00 00 02 ce 01
39 01 00 00 20 00 02 cc 00
];
qcom,mdss-dsi-on-command = [
39 01 00 00 00 00 06 F0 55 AA 52 08 01
39 01 00 00 00 00 02 6F 01
39 01 00 00 00 00 04 C5 0B 0B 0B
39 01 00 00 00 00 05 FF AA 55 A5 80
39 01 00 00 00 00 02 6F 02
39 01 00 00 00 00 02 F5 10
39 01 00 00 00 00 02 6F 1B
39 01 00 00 00 00 02 F4 55
39 01 00 00 00 00 02 6F 18
39 01 00 00 00 00 02 F8 19
39 01 00 00 00 00 02 6F 0F
39 01 00 00 00 00 02 FC 00
39 01 00 00 00 00 05 2a 00 00 04 37
39 01 00 00 00 00 05 2b 00 00 09 5f
39 01 00 00 00 00 02 90 03
39 01 00 00 00 00 13 91 89 28 00 28 c2
00 02 0e 03 dd 00 07 02 77 02 8B 10
f0
39 01 00 00 00 00 05 ff aa 55 a5 81
39 01 00 00 00 00 02 6f 23
39 01 00 00 00 00 15 fb 00 01 00 11 33
33 33 55 57 d0 00 00 44 56 77 78 9a
bc dd f0
39 01 00 00 00 00 02 6F 06
39 01 00 00 00 00 02 F3 DC
39 01 00 00 00 00 02 26 00
39 01 00 00 00 00 02 35 00
39 01 00 00 00 00 05 3B 00 18 00 10
39 01 00 00 00 00 02 53 20
39 01 00 00 00 00 07 51 07 FF 07 FF 0F
FF
39 01 00 00 00 00 02 5A 01
39 01 00 00 00 00 02 5F 00
39 01 00 00 00 00 02 9C 01
05 01 00 00 00 00 01 2C
39 01 00 00 00 00 02 2f 00
39 01 00 00 00 00 02 26 01
39 01 00 00 00 00 02 5a 01
39 01 00 00 00 00 02 2f 30
39 01 00 00 00 00 06 f0 55 aa 52 08 00
39 01 00 00 00 00 02 6f 1c
39 01 00 00 00 00 09 ba 91 02 02 00 01
02 02 00
39 01 00 00 00 00 06 f0 55 aa 52 08 00
39 01 00 00 00 00 06 c0 54 c0 00 21 43
39 01 00 00 00 00 06 f0 55 aa 52 08 02
39 01 00 00 00 00 02 cc 30
39 01 00 00 00 00 02 ce 01
39 01 00 00 20 00 02 cc 00
39 01 00 00 00 00 06 F0 55 AA 52 08 01
39 01 00 00 00 00 05 B2 55 01 FF 03
05 01 00 00 78 00 01 11
05 01 00 00 14 00 01 29
];
qcom,mdss-dsi-off-command = [
05 01 00 00 14 00 02 28 00
05 01 00 00 78 00 02 10 00];
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
qcom,mdss-dsi-timing-switch-command-state =
"dsi_lp_mode";
qcom,mdss-dsi-h-sync-pulse = <0>;
qcom,compression-mode = "dsc";
qcom,mdss-dsc-slice-height = <40>;
qcom,mdss-dsc-slice-width = <540>;
qcom,mdss-dsc-slice-per-pkt = <1>;
qcom,mdss-dsc-bit-per-component = <8>;
qcom,mdss-dsc-bit-per-pixel = <8>;
qcom,mdss-dsc-block-prediction-enable;
};
timing@4 {
cell-index = <4>;
qcom,mdss-dsi-panel-framerate = <30>;
qcom,mdss-dsi-panel-width = <1080>;
qcom,mdss-dsi-panel-height = <2400>;
qcom,mdss-dsi-h-front-porch = <20>;
qcom,mdss-dsi-h-back-porch = <20>;
qcom,mdss-dsi-h-pulse-width = <4>;
qcom,mdss-dsi-h-sync-skew = <0>;
qcom,mdss-dsi-v-back-porch = <18>;
qcom,mdss-dsi-v-front-porch = <20>;
qcom,mdss-dsi-v-pulse-width = <2>;
qcom,mdss-dsi-h-left-border = <0>;
qcom,mdss-dsi-h-right-border = <0>;
qcom,mdss-dsi-v-top-border = <0>;
qcom,mdss-dsi-v-bottom-border = <0>;
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
qcom,mdss-dsi-panel-clockrate = <680000000>;
qcom,mdss-dsi-timing-switch-command = [
39 01 00 00 00 00 05 2a 00 00 04 37
39 01 00 00 00 00 05 2b 00 00 09 5f
39 01 00 00 00 00 02 8f 01
39 01 00 00 00 00 02 2f 00
39 01 00 00 00 00 02 26 01
39 01 00 00 00 00 02 5a 01
39 01 00 00 00 00 02 2f 30
39 01 00 00 00 00 06 f0 55 aa 52 08 00
39 01 00 00 00 00 02 6f 1c
39 01 00 00 00 00 09 ba 91 03 03 00 01
03 03 00
39 01 00 00 00 00 06 f0 55 aa 52 08 00
39 01 00 00 00 00 06 c0 54 c0 00 21 43
39 01 00 00 00 00 06 f0 55 aa 52 08 02
39 01 00 00 00 00 02 cc 30
39 01 00 00 00 00 02 ce 01
39 01 00 00 20 00 02 cc 00
];
qcom,mdss-dsi-on-command = [
39 01 00 00 00 00 06 F0 55 AA 52 08 01
39 01 00 00 00 00 02 6F 01
39 01 00 00 00 00 04 C5 0B 0B 0B
39 01 00 00 00 00 05 FF AA 55 A5 80
39 01 00 00 00 00 02 6F 02
39 01 00 00 00 00 02 F5 10
39 01 00 00 00 00 02 6F 1B
39 01 00 00 00 00 02 F4 55
39 01 00 00 00 00 02 6F 18
39 01 00 00 00 00 02 F8 19
39 01 00 00 00 00 02 6F 0F
39 01 00 00 00 00 02 FC 00
39 01 00 00 00 00 05 2a 00 00 04 37
39 01 00 00 00 00 05 2b 00 00 09 5f
39 01 00 00 00 00 02 90 03
39 01 00 00 00 00 13 91 89 28 00 28 c2
00 02 0e 03 dd 00 07 02 77 02 8B 10
f0
39 01 00 00 00 00 05 ff aa 55 a5 81
39 01 00 00 00 00 02 6f 23
39 01 00 00 00 00 15 fb 00 01 00 11 33
33 33 55 57 d0 00 00 44 56 77 78 9a
bc dd f0
39 01 00 00 00 00 02 6F 06
39 01 00 00 00 00 02 F3 DC
39 01 00 00 00 00 02 26 00
39 01 00 00 00 00 02 35 00
39 01 00 00 00 00 05 3B 00 18 00 10
39 01 00 00 00 00 02 53 20
39 01 00 00 00 00 07 51 07 FF 07 FF 0F
FF
39 01 00 00 00 00 02 5A 01
39 01 00 00 00 00 02 5F 00
39 01 00 00 00 00 02 9C 01
05 01 00 00 00 00 01 2C
39 01 00 00 00 00 02 2f 00
39 01 00 00 00 00 02 26 01
39 01 00 00 00 00 02 5a 01
39 01 00 00 00 00 02 2f 30
39 01 00 00 00 00 06 f0 55 aa 52 08 00
39 01 00 00 00 00 02 6f 1c
39 01 00 00 00 00 09 ba 91 03 03 00 01
03 03 00
39 01 00 00 00 00 06 f0 55 aa 52 08 00
39 01 00 00 00 00 06 c0 54 c0 00 21 43
39 01 00 00 00 00 06 f0 55 aa 52 08 02
39 01 00 00 00 00 02 cc 30
39 01 00 00 00 00 02 ce 01
39 01 00 00 20 00 02 cc 00
39 01 00 00 00 00 06 F0 55 AA 52 08 01
39 01 00 00 00 00 05 B2 55 01 FF 03
05 01 00 00 78 00 01 11
05 01 00 00 14 00 01 29
];
qcom,mdss-dsi-off-command = [
05 01 00 00 14 00 02 28 00
05 01 00 00 78 00 02 10 00];
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
qcom,mdss-dsi-timing-switch-command-state =
"dsi_lp_mode";
qcom,mdss-dsi-h-sync-pulse = <0>;
qcom,compression-mode = "dsc";
qcom,mdss-dsc-slice-height = <40>;
qcom,mdss-dsc-slice-width = <540>;
qcom,mdss-dsc-slice-per-pkt = <1>;
qcom,mdss-dsc-bit-per-component = <8>;
qcom,mdss-dsc-bit-per-pixel = <8>;
qcom,mdss-dsc-block-prediction-enable;
};
};
};
};

33
display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi
View File

@@ -85,9 +85,14 @@
39 01 00 00 00 00 05 2A 00 00 05 9F
39 01 00 00 00 00 05 2B 00 00 0C 7F
39 01 00 00 00 00 03 90 03 03
39 01 00 00 00 00 13 91 89 28 00 28 D2
00 02 86 04 3A 00 0A 02 AB 01 E9 10
F0
39 01 00 00 00 00 13 91 89 28 00 28 c2
00 02 68 04 6c 00 0a 02 77 01 e9 10
f0
39 01 00 00 00 00 05 ff aa 55 a5 81
39 01 00 00 00 00 02 6f 23
39 01 00 00 00 00 15 fb 00 01 00 11 33
33 33 55 57 d0 00 00 44 56 77 78 9a
bc dd f0
39 01 00 00 00 00 02 6F 06
39 01 00 00 00 00 02 F3 DC
39 01 00 00 00 00 02 26 00
@@ -172,9 +177,14 @@
39 01 00 00 00 00 05 2A 00 00 05 9F
39 01 00 00 00 00 05 2B 00 00 0C 7F
39 01 00 00 00 00 03 90 03 03
39 01 00 00 00 00 13 91 89 28 00 28 D2
00 02 86 04 3A 00 0A 02 AB 01 E9 10
F0
39 01 00 00 00 00 13 91 89 28 00 28 c2
00 02 68 04 6c 00 0a 02 77 01 e9 10
f0
39 01 00 00 00 00 05 ff aa 55 a5 81
39 01 00 00 00 00 02 6f 23
39 01 00 00 00 00 15 fb 00 01 00 11 33
33 33 55 57 d0 00 00 44 56 77 78 9a
bc dd f0
39 01 00 00 00 00 02 6F 06
39 01 00 00 00 00 02 F3 DC
39 01 00 00 00 00 02 26 00
@@ -274,9 +284,14 @@
39 01 00 00 00 00 05 2A 00 00 05 9F
39 01 00 00 00 00 05 2B 00 00 0C 7F
39 01 00 00 00 00 03 90 03 03
39 01 00 00 00 00 13 91 89 28 00 28 D2
00 02 86 04 3A 00 0A 02 AB 01 E9 10
F0
39 01 00 00 00 00 13 91 89 28 00 28 c2
00 02 68 04 6c 00 0a 02 77 01 e9 10
f0
39 01 00 00 00 00 05 ff aa 55 a5 81
39 01 00 00 00 00 02 6f 23
39 01 00 00 00 00 15 fb 00 01 00 11 33
33 33 55 57 d0 00 00 44 56 77 78 9a
bc dd f0
39 01 00 00 00 00 02 6F 06
39 01 00 00 00 00 02 F3 DC
39 01 00 00 00 00 02 26 00

184
display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi
View File

@@ -89,9 +89,14 @@
39 01 00 00 00 00 05 2A 00 00 05 9F
39 01 00 00 00 00 05 2B 00 00 0C 7F
39 01 00 00 00 00 03 90 03 03
39 01 00 00 00 00 13 91 89 28 00 28 D2
00 02 86 04 3A 00 0A 02 AB 01 E9 10
F0
39 01 00 00 00 00 13 91 89 28 00 28 c2
00 02 68 04 6c 00 0a 02 77 01 e9 10
f0
39 01 00 00 00 00 05 ff aa 55 a5 81
39 01 00 00 00 00 02 6f 23
39 01 00 00 00 00 15 fb 00 01 00 11 33
33 33 55 57 d0 00 00 44 56 77 78 9a
bc dd f0
39 01 00 00 00 00 02 6F 06
39 01 00 00 00 00 02 F3 DC
39 01 00 00 00 00 02 26 00
@@ -130,93 +135,6 @@
timing@1 {
cell-index = <1>;
qcom,mdss-dsi-panel-framerate = <120>;
qcom,mdss-dsi-panel-width = <1080>;
qcom,mdss-dsi-panel-height = <2400>;
qcom,mdss-dsi-h-front-porch = <20>;
qcom,mdss-dsi-h-back-porch = <20>;
qcom,mdss-dsi-h-pulse-width = <4>;
qcom,mdss-dsi-h-sync-skew = <0>;
qcom,mdss-dsi-v-back-porch = <18>;
qcom,mdss-dsi-v-front-porch = <20>;
qcom,mdss-dsi-v-pulse-width = <2>;
qcom,mdss-dsi-h-left-border = <0>;
qcom,mdss-dsi-h-right-border = <0>;
qcom,mdss-dsi-v-top-border = <0>;
qcom,mdss-dsi-v-bottom-border = <0>;
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
qcom,mdss-dsi-timing-switch-command = [
39 01 00 00 00 00 05 2A 00 00 04 37
39 01 00 00 00 00 05 2B 00 00 09 5F
39 01 00 00 00 00 02 8F 01
39 01 00 00 00 00 02 2f 00
39 01 00 00 00 00 02 26 00
39 01 00 00 00 00 06 f0 55 aa 52 08 00
39 01 00 00 00 00 06 c0 54 c0 00 21 43
39 01 00 00 00 00 06 f0 55 aa 52 08 02
39 01 00 00 00 00 02 cc 30
39 01 00 00 00 00 02 ce 01
39 01 00 00 20 00 02 cc 00
];
qcom,mdss-dsi-on-command = [
39 01 00 00 00 00 06 F0 55 AA 52 08 01
39 01 00 00 00 00 02 6F 01
39 01 00 00 00 00 04 C5 0B 0B 0B
39 01 00 00 00 00 05 FF AA 55 A5 80
39 01 00 00 00 00 02 6F 02
39 01 00 00 00 00 02 F5 10
39 01 00 00 00 00 02 6F 1B
39 01 00 00 00 00 02 F4 55
39 01 00 00 00 00 02 6F 18
39 01 00 00 00 00 02 F8 19
39 01 00 00 00 00 02 6F 0F
39 01 00 00 00 00 02 FC 00
39 01 00 00 00 00 05 2A 00 00 04 37
39 01 00 00 00 00 05 2B 00 00 09 5F
39 01 00 00 00 00 03 90 03 03
39 01 00 00 00 00 13 91 89 28 00 28 D2 00 02 86 04 3A 00 0A 02 AB 01 E9 10 F0
39 01 00 00 00 00 13 93 89 28 00 28 D2 00 02 25 03 B6 00 07 02 AB 02 8B 10 F0
39 01 00 00 00 00 13 95 89 28 00 28 D2 00 01 C3 02 FC 00 05 02 AB 03 D1 10 F0
39 01 00 00 00 00 02 03 00
39 01 00 00 00 00 02 8F 01
39 01 00 00 00 00 02 6F 06
39 01 00 00 00 00 02 F3 DC
39 01 00 00 00 00 02 26 00
39 01 00 00 00 00 02 35 00
39 01 00 00 00 00 05 3B 00 18 00 10
39 01 00 00 00 00 02 53 20
39 01 00 00 00 00 07 51 07 FF 07 FF 0F FF
39 01 00 00 00 00 02 5A 01
39 01 00 00 00 00 02 5F 00
39 01 00 00 00 00 02 9C 01
05 01 00 00 00 00 01 2C
39 01 00 00 00 00 02 2F 00
05 01 00 00 78 00 01 11
05 01 00 00 14 00 01 29
];
qcom,mdss-dsi-off-command = [
05 01 00 00 14 00 02 28 00
05 01 00 00 78 00 02 10 00];
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
qcom,mdss-dsi-timing-switch-command-state =
"dsi_lp_mode";
qcom,mdss-dsi-h-sync-pulse = <0>;
qcom,compression-mode = "dsc";
qcom,mdss-dsc-slice-height = <40>;
qcom,mdss-dsc-slice-width = <540>;
qcom,mdss-dsc-slice-per-pkt = <1>;
qcom,mdss-dsc-bit-per-component = <8>;
qcom,mdss-dsc-bit-per-pixel = <8>;
qcom,mdss-dsc-block-prediction-enable;
};
timing@2 {
cell-index = <2>;
qcom,mdss-dsi-panel-framerate = <90>;
qcom,mdss-dsi-panel-width = <1440>;
qcom,mdss-dsi-panel-height = <3200>;
@@ -263,9 +181,14 @@
39 01 00 00 00 00 05 2A 00 00 05 9F
39 01 00 00 00 00 05 2B 00 00 0C 7F
39 01 00 00 00 00 03 90 03 03
39 01 00 00 00 00 13 91 89 28 00 28 D2
00 02 86 04 3A 00 0A 02 AB 01 E9 10
F0
39 01 00 00 00 00 13 91 89 28 00 28 c2
00 02 68 04 6c 00 0a 02 77 01 e9 10
f0
39 01 00 00 00 00 05 ff aa 55 a5 81
39 01 00 00 00 00 02 6f 23
39 01 00 00 00 00 15 fb 00 01 00 11 33
33 33 55 57 d0 00 00 44 56 77 78 9a
bc dd f0
39 01 00 00 00 00 02 6F 06
39 01 00 00 00 00 02 F3 DC
39 01 00 00 00 00 02 26 00
@@ -310,8 +233,8 @@
qcom,mdss-dsc-block-prediction-enable;
};
timing@3 {
cell-index = <3>;
timing@2 {
cell-index = <2>;
qcom,mdss-dsi-panel-framerate = <60>;
qcom,mdss-dsi-panel-width = <1440>;
qcom,mdss-dsi-panel-height = <3200>;
@@ -365,9 +288,14 @@
39 01 00 00 00 00 05 2A 00 00 05 9F
39 01 00 00 00 00 05 2B 00 00 0C 7F
39 01 00 00 00 00 03 90 03 03
39 01 00 00 00 00 13 91 89 28 00 28 D2
00 02 86 04 3A 00 0A 02 AB 01 E9 10
F0
39 01 00 00 00 00 13 91 89 28 00 28 c2
00 02 68 04 6c 00 0a 02 77 01 e9 10
f0
39 01 00 00 00 00 05 ff aa 55 a5 81
39 01 00 00 00 00 02 6f 23
39 01 00 00 00 00 15 fb 00 01 00 11 33
33 33 55 57 d0 00 00 44 56 77 78 9a
bc dd f0
39 01 00 00 00 00 02 6F 06
39 01 00 00 00 00 02 F3 DC
39 01 00 00 00 00 02 26 00
@@ -417,8 +345,8 @@
qcom,mdss-dsc-block-prediction-enable;
};
timing@4 {
cell-index = <4>;
timing@3 {
cell-index = <3>;
qcom,mdss-dsi-panel-framerate = <40>;
qcom,mdss-dsi-panel-width = <1440>;
qcom,mdss-dsi-panel-height = <3200>;
@@ -472,9 +400,14 @@
39 01 00 00 00 00 05 2A 00 00 05 9F
39 01 00 00 00 00 05 2B 00 00 0C 7F
39 01 00 00 00 00 03 90 03 03
39 01 00 00 00 00 13 91 89 28 00 28 D2
00 02 86 04 3A 00 0A 02 AB 01 E9 10
F0
39 01 00 00 00 00 13 91 89 28 00 28 c2
00 02 68 04 6c 00 0a 02 77 01 e9 10
f0
39 01 00 00 00 00 05 ff aa 55 a5 81
39 01 00 00 00 00 02 6f 23
39 01 00 00 00 00 15 fb 00 01 00 11 33
33 33 55 57 d0 00 00 44 56 77 78 9a
bc dd f0
39 01 00 00 00 00 02 6F 06
39 01 00 00 00 00 02 F3 DC
39 01 00 00 00 00 02 26 00
@@ -524,8 +457,8 @@
qcom,mdss-dsc-block-prediction-enable;
};
timing@5 {
cell-index = <5>;
timing@4 {
cell-index = <4>;
qcom,mdss-dsi-panel-framerate = <30>;
qcom,mdss-dsi-panel-width = <1440>;
qcom,mdss-dsi-panel-height = <3200>;
@@ -579,9 +512,14 @@
39 01 00 00 00 00 05 2A 00 00 05 9F
39 01 00 00 00 00 05 2B 00 00 0C 7F
39 01 00 00 00 00 03 90 03 03
39 01 00 00 00 00 13 91 89 28 00 28 D2
00 02 86 04 3A 00 0A 02 AB 01 E9 10
F0
39 01 00 00 00 00 13 91 89 28 00 28 c2
00 02 68 04 6c 00 0a 02 77 01 e9 10
f0
39 01 00 00 00 00 05 ff aa 55 a5 81
39 01 00 00 00 00 02 6f 23
39 01 00 00 00 00 15 fb 00 01 00 11 33
33 33 55 57 d0 00 00 44 56 77 78 9a
bc dd f0
39 01 00 00 00 00 02 6F 06
39 01 00 00 00 00 02 F3 DC
39 01 00 00 00 00 02 26 00
@@ -631,8 +569,8 @@
qcom,mdss-dsc-block-prediction-enable;
};
timing@6 {
cell-index = <6>;
timing@5 {
cell-index = <5>;
qcom,mdss-dsi-panel-framerate = <24>;
qcom,mdss-dsi-panel-width = <1440>;
qcom,mdss-dsi-panel-height = <3200>;
@@ -686,9 +624,14 @@
39 01 00 00 00 00 05 2A 00 00 05 9F
39 01 00 00 00 00 05 2B 00 00 0C 7F
39 01 00 00 00 00 03 90 03 03
39 01 00 00 00 00 13 91 89 28 00 28 D2
00 02 86 04 3A 00 0A 02 AB 01 E9 10
F0
39 01 00 00 00 00 13 91 89 28 00 28 c2
00 02 68 04 6c 00 0a 02 77 01 e9 10
f0
39 01 00 00 00 00 05 ff aa 55 a5 81
39 01 00 00 00 00 02 6f 23
39 01 00 00 00 00 15 fb 00 01 00 11 33
33 33 55 57 d0 00 00 44 56 77 78 9a
bc dd f0
39 01 00 00 00 00 02 6F 06
39 01 00 00 00 00 02 F3 DC
39 01 00 00 00 00 02 26 00
@@ -738,8 +681,8 @@
qcom,mdss-dsc-block-prediction-enable;
};
timing@7 {
cell-index = <7>;
timing@6 {
cell-index = <6>;
qcom,mdss-dsi-panel-framerate = <20>;
qcom,mdss-dsi-panel-width = <1440>;
qcom,mdss-dsi-panel-height = <3200>;
@@ -793,9 +736,14 @@
39 01 00 00 00 00 05 2A 00 00 05 9F
39 01 00 00 00 00 05 2B 00 00 0C 7F
39 01 00 00 00 00 03 90 03 03
39 01 00 00 00 00 13 91 89 28 00 28 D2
00 02 86 04 3A 00 0A 02 AB 01 E9 10
F0
39 01 00 00 00 00 13 91 89 28 00 28 c2
00 02 68 04 6c 00 0a 02 77 01 e9 10
f0
39 01 00 00 00 00 05 ff aa 55 a5 81
39 01 00 00 00 00 02 6f 23
39 01 00 00 00 00 15 fb 00 01 00 11 33
33 33 55 57 d0 00 00 44 56 77 78 9a
bc dd f0
39 01 00 00 00 00 02 6F 06
39 01 00 00 00 00 02 F3 DC
39 01 00 00 00 00 02 26 00

11
display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi
View File

@@ -75,9 +75,14 @@
39 01 00 00 00 00 05 2A 00 00 05 9F
39 01 00 00 00 00 05 2B 00 00 0C 7F
39 01 00 00 00 00 03 90 03 03
39 01 00 00 00 00 13 91 89 28 00 28 D2
00 02 86 04 3A 00 0A 02 AB 01 E9 10
F0
39 01 00 00 00 00 13 91 89 28 00 28 c2
00 02 68 04 6c 00 0a 02 77 01 e9 10
f0
39 01 00 00 00 00 05 ff aa 55 a5 81
39 01 00 00 00 00 02 6f 23
39 01 00 00 00 00 15 fb 00 01 00 11 33
33 33 55 57 d0 00 00 44 56 77 78 9a
bc dd f0
39 01 00 00 00 00 02 6F 06
39 01 00 00 00 00 02 F3 DC
39 01 00 00 00 00 02 26 00

11
display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi
View File

@@ -77,9 +77,14 @@
39 01 00 00 00 00 05 2A 00 00 05 9F
39 01 00 00 00 00 05 2B 00 00 0C 7F
39 01 00 00 00 00 03 90 03 03
39 01 00 00 00 00 13 91 89 28 00 28 D2
00 02 86 04 3A 00 0A 02 AB 01 E9 10
F0
39 01 00 00 00 00 13 91 89 28 00 28 c2
00 02 68 04 6c 00 0a 02 77 01 e9 10
f0
39 01 00 00 00 00 05 ff aa 55 a5 81
39 01 00 00 00 00 02 6f 23
39 01 00 00 00 00 15 fb 00 01 00 11 33
33 33 55 57 d0 00 00 44 56 77 78 9a
bc dd f0
39 01 00 00 00 00 02 6F 06
39 01 00 00 00 00 02 F3 DC
39 01 00 00 00 00 02 26 00

11
display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi
View File

@@ -75,9 +75,14 @@
39 01 00 00 00 00 05 2A 00 00 05 9F
39 01 00 00 00 00 05 2B 00 00 0C 7F
39 01 00 00 00 00 03 90 03 03
39 01 00 00 00 00 13 91 89 28 00 28 D2
00 02 86 04 3A 00 0A 02 AB 01 E9 10
F0
39 01 00 00 00 00 13 91 89 28 00 28 c2
00 02 68 04 6c 00 0a 02 77 01 e9 10
f0
39 01 00 00 00 00 05 ff aa 55 a5 81
39 01 00 00 00 00 02 6f 23
39 01 00 00 00 00 15 fb 00 01 00 11 33
33 33 55 57 d0 00 00 44 56 77 78 9a
bc dd f0
39 01 00 00 00 00 02 6F 06
39 01 00 00 00 00 02 F3 DC
39 01 00 00 00 00 02 26 00

11
display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi
View File

@@ -77,9 +77,14 @@
39 01 00 00 00 00 05 2A 00 00 05 9F
39 01 00 00 00 00 05 2B 00 00 0C 7F
39 01 00 00 00 00 03 90 03 03
39 01 00 00 00 00 13 91 89 28 00 28 D2
00 02 86 04 3A 00 0A 02 AB 01 E9 10
F0
39 01 00 00 00 00 13 91 89 28 00 28 c2
00 02 68 04 6c 00 0a 02 77 01 e9 10
f0
39 01 00 00 00 00 05 ff aa 55 a5 81
39 01 00 00 00 00 02 6f 23
39 01 00 00 00 00 15 fb 00 01 00 11 33
33 33 55 57 d0 00 00 44 56 77 78 9a
bc dd f0
39 01 00 00 00 00 02 6F 06
39 01 00 00 00 00 02 F3 DC
39 01 00 00 00 00 02 26 00

11
display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi
View File

@@ -77,9 +77,14 @@
39 01 00 00 00 00 05 2A 00 00 05 9F
39 01 00 00 00 00 05 2B 00 00 0C 7F
39 01 00 00 00 00 03 90 03 03
39 01 00 00 00 00 13 91 89 28 00 28 D2
00 02 86 04 3A 00 0A 02 AB 01 E9 10
F0
39 01 00 00 00 00 13 91 89 28 00 28 c2
00 02 68 04 6c 00 0a 02 77 01 e9 10
f0
39 01 00 00 00 00 05 ff aa 55 a5 81
39 01 00 00 00 00 02 6f 23
39 01 00 00 00 00 15 fb 00 01 00 11 33
33 33 55 57 d0 00 00 44 56 77 78 9a
bc dd f0
39 01 00 00 00 00 02 6F 06
39 01 00 00 00 00 02 F3 DC
39 01 00 00 00 00 02 26 00

11
display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi
View File

@@ -79,9 +79,14 @@
39 01 00 00 00 00 05 2A 00 00 05 9F
39 01 00 00 00 00 05 2B 00 00 0C 7F
39 01 00 00 00 00 03 90 03 03
39 01 00 00 00 00 13 91 89 28 00 28 D2
00 02 86 04 3A 00 0A 02 AB 01 E9 10
F0
39 01 00 00 00 00 13 91 89 28 00 28 c2
00 02 68 04 6c 00 0a 02 77 01 e9 10
f0
39 01 00 00 00 00 05 ff aa 55 a5 81
39 01 00 00 00 00 02 6f 23
39 01 00 00 00 00 15 fb 00 01 00 11 33
33 33 55 57 d0 00 00 44 56 77 78 9a
bc dd f0
39 01 00 00 00 00 02 6F 06
39 01 00 00 00 00 02 F3 DC
39 01 00 00 00 00 02 26 00

6
display/sun-sde-common.dtsi
View File

@@ -13,13 +13,11 @@
reg = <0x0ae00000 0x93800>,
<0x0aeb0000 0x2008>,
<0x0af80000 0x7000>,
<0x400000 0x2000>,
<0x0af08000 0x24>;
<0x400000 0x2000>;
reg-names = "mdp_phys",
"vbif_phys",
"regdma_phys",
"ipcc_reg",
"disp_cc";
"ipcc_reg";
/* interrupt config */
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;

2
display/sun-sde-display-atp-overlay.dts
View File

@@ -11,6 +11,6 @@
/ {
model = "Qualcomm Technologies, Inc. Sun ATP";
compatible = "qcom,sun-atp", "qcom,sun", "qcom,sunp-atp", "qcom,sunp", "qcom,atp";
qcom,msm-id = <618 0x10000>, <618 0x20000>;
qcom,msm-id = <618 0x10000>, <618 0x20000>, <0x100026a 0x10000>, <0x100026a 0x20000>;
qcom,board-id = <0x10021 0>;
};

4
display/sun-sde-display-cdp-kiwi-overlay.dts
View File

@@ -11,6 +11,8 @@
/ {
model = "Qualcomm Technologies, Inc. Sun CDP Kiwi WLAN";
compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp", "qcom,cdp";
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
<0x100026a 0x10000>, <0x100026a 0x20000>,
<0x100027f 0x10000>, <0x100027f 0x20000>;
qcom,board-id = <0x20001 0>;
};

6
display/sun-sde-display-cdp-kiwi-v8-overlay.dts
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
@@ -12,6 +12,8 @@
model = "Qualcomm Technologies, Inc. Sun CDP Kiwi WLAN V8 Power Grid";
compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp",
"qcom,cdp";
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
<0x100026a 0x10000>, <0x100026a 0x20000>,
<0x100027f 0x10000>, <0x100027f 0x20000>;
qcom,board-id = <0x60001 0>;
};

6
display/sun-sde-display-cdp-nfc-overlay.dts
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
@@ -11,6 +11,8 @@
/ {
model = "Qualcomm Technologies, Inc. Sun CDP SN300 NFC";
compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp", "qcom,cdp";
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
<0x100026a 0x10000>, <0x100026a 0x20000>,
<0x100027f 0x10000>, <0x100027f 0x20000>;
qcom,board-id = <0x40001 0>;
};

19
display/sun-sde-display-cdp-no-display-overlay.dts Normal file
View File

@@ -0,0 +1,19 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "sun-sde-display-cdp-no-display.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Sun CDP No Display";
compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp",
"qcom,cdp";
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
<0x100026a 0x10000>, <0x100026a 0x20000>,
<0x100027f 0x10000>, <0x100027f 0x20000>;
qcom,board-id = <0x30001 0>;
};

15
display/sun-sde-display-cdp-no-display.dtsi Normal file
View File

@@ -0,0 +1,15 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "sun-sde-display.dtsi"
&dsi_sim_vid {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&sde_dsi {
qcom,dsi-default-panel = <&dsi_sim_vid>;
};

6
display/sun-sde-display-cdp-overlay.dts
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
@@ -11,6 +11,8 @@
/ {
model = "Qualcomm Technologies, Inc. Sun CDP";
compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp";
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
<0x100026a 0x10000>, <0x100026a 0x20000>,
<0x100027f 0x10000>, <0x100027f 0x20000>;
qcom,board-id = <1 0>;
};

6
display/sun-sde-display-cdp-v8-overlay.dts
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
@@ -12,6 +12,8 @@
model = "Qualcomm Technologies, Inc. Sun CDP V8 Power Grid";
compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp",
"qcom,cdp";
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
<0x100026a 0x10000>, <0x100026a 0x20000>,
<0x100027f 0x10000>, <0x100027f 0x20000>;
qcom,board-id = <0x50001 0>;
};

16
display/sun-sde-display-cdp.dtsi
View File

@@ -126,6 +126,19 @@
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
};
&dsi_nt37801_amoled_fhd_plus_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
};
&dsi_vtdr6130_amoled_120hz_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
@@ -239,7 +252,8 @@
&dsi_nt37801_amoled_video_cphy
&dsi_nt37801_amoled_cmd_spr
&dsi_nt37801_amoled_qsync_cmd
&dsi_nt37801_amoled_qsync_video>;
&dsi_nt37801_amoled_qsync_video
&dsi_nt37801_amoled_fhd_plus_cmd>;
};
};

78
display/sun-sde-display-common.dtsi
View File

@@ -14,6 +14,7 @@
#include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi"
#include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi"
#include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi"
#include "dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi"
#include "dsi-panel-sharp-dsc-4k-cmd.dtsi"
#include "dsi-panel-sharp-dsc-4k-video.dtsi"
#include "dsi-panel-sim-cmd-au.dtsi"
@@ -31,6 +32,7 @@
#include "dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi"
#include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi"
#include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi"
#include "dsi-panel-ext-bridge-1080p.dtsi"
#include "sun-sde-display-pinctrl.dtsi"
@@ -372,48 +374,41 @@
};
timing@1 {
qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a
0b 0a 02 04 00 21 0f];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
timing@2 {
qcom,mdss-dsi-panel-phy-timings = [00 1f 08 07 18 22 08
08 08 08 02 04 1a 0d];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
timing@3 {
timing@2 {
qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 1f 06
06 06 06 02 04 13 0b];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
timing@4 {
timing@3 {
qcom,mdss-dsi-panel-phy-timings = [00 11 03 04 12 1e 04
04 04 03 02 04 0e 09];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
timing@5 {
timing@4 {
qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 10 1d 03
03 03 02 02 04 0c 08];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
timing@6 {
timing@5 {
qcom,mdss-dsi-panel-phy-timings = [00 0c 02 02 10 1c 03
03 03 02 02 04 0b 08];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
timing@7 {
timing@6 {
qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 0f 1c 02
02 02 02 02 04 0a 07];
qcom,display-topology = <2 2 1>;
@@ -643,6 +638,65 @@
};
};
&dsi_nt37801_amoled_fhd_plus_cmd {
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1";
qcom,esd-check-enabled;
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
qcom,mdss-dsi-panel-status-value = <0x9c>;
qcom,mdss-dsi-panel-status-read-length = <1>;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a
0b 0a 02 04 00 21 0f];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
timing@1 {
qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07
06 06 07 02 04 16 0b];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
timing@2 {
qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07
06 06 07 02 04 16 0b];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
timing@3 {
qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07
06 06 07 02 04 16 0b];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
timing@4 {
qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07
06 06 07 02 04 16 0b];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_ext_bridge_1080p {
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 18 22 08
08 08 02 04 1a 0c 00];
qcom,display-topology = <1 0 1>;
};
};
};
&dsi_sharp_4k_dsc_cmd {
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";

16
display/sun-sde-display-hdk-overlay.dts Normal file
View File

@@ -0,0 +1,16 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "sun-sde-display-hdk.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SunP QRD HDK";
compatible = "qcom,sunp-hdk", "qcom,sunp", "qcom,hdk";
qcom,msm-id = <639 0x10000>, <639 0x20000>, <618 0x10000>, <618 0x20000>;
qcom,board-id = <0x1001f 0>;
};

281
display/sun-sde-display-hdk.dtsi Normal file
View File

@@ -0,0 +1,281 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "sun-sde-display.dtsi"
&dsi_vtdr6130_amoled_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
};
&dsi_vtdr6130_amoled_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
};
&dsi_vtdr6130_amoled_120hz_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_nt37801_amoled_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_nt37801_amoled_cmd_cphy {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_nt37801_amoled_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_nt37801_amoled_video_cphy {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_vtdr6130_amoled_120hz_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_sim_panel_au {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_vtdr6130_amoled_qsync_144hz_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_vtdr6130_amoled_qsync_144hz_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_sharp_4k_dsc_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,platform-reset-gpio = <&tlmm 98 0>;
qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
};
&dsi_sharp_4k_dsc_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,platform-reset-gpio = <&tlmm 98 0>;
qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
};
&dsi_sim_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_vid {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_dsc_375_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_dsc_10b_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_dual_sim_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
};
&dsi_dual_sim_dsc_375_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_sec_hd_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <1023>;
};
&tlmm {
lt9611_pins: lt9611_pins {
mux {
pins = "gpio69", "gpio60", "gpio214", "gpio83";
function = "gpio";
};
config {
pins = "gpio69", "gpio60", "gpio214", "gpio83";
drive-strength = <8>;
bias-disable = <0>;
};
};
};
&qupv3_se5_i2c {
status = "ok";
lt9611: lt,lt9611@2b {
compatible = "lt,lt9611uxc";
reg = <0x2b>;
interrupt-parent = <&tlmm>;
interrupts = <44 0>;
interrupt-names = "lt_irq";
lt,irq-gpio = <&tlmm 69 0x0>;
lt,reset-gpio = <&tlmm 60 0x0>;
lt,hdmi-3p3-en = <&tlmm 214 0x0>;
lt,hdmi-1p2-en = <&tlmm 83 0x0>;
lt,non-pluggable;
pinctrl-names = "default";
pinctrl-0 = <&lt9611_pins>;
lt,preferred-mode = "1920x1080";
lt,customize-modes {
lt,customize-mode-id@0 {
lt,mode-h-active = <1920>;
lt,mode-h-front-porch = <88>;
lt,mode-h-pulse-width = <44>;
lt,mode-h-back-porch = <148>;
lt,mode-h-active-high;
lt,mode-v-active = <1080>;
lt,mode-v-front-porch = <4>;
lt,mode-v-pulse-width = <5>;
lt,mode-v-back-porch = <36>;
lt,mode-v-active-high;
lt,mode-clock-in-khz = <148500>;
};
lt,customize-mode-id@1 {
lt,mode-h-active = <3840>;
lt,mode-h-front-porch = <176>;
lt,mode-h-pulse-width = <88>;
lt,mode-h-back-porch = <400>;
lt,mode-h-active-high;
lt,mode-v-active = <2160>;
lt,mode-v-front-porch = <8>;
lt,mode-v-pulse-width = <10>;
lt,mode-v-back-porch = <72>;
lt,mode-v-active-high;
lt,mode-clock-in-khz = <608040>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lt9611_in_0: endpoint {
remote-endpoint = <&ext_dsi_0_out>;
};
};
};
};
};
&sde_dsi {
qcom,dsi-default-panel = <&dsi_ext_bridge_1080p>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ext_dsi_0_out: endpoint {
remote-endpoint = <&lt9611_in_0>;
};
};
};
};
&battery_charger {
qcom,display-panels = <&dsi_vtdr6130_amoled_cmd
&dsi_vtdr6130_amoled_video
&dsi_vtdr6130_amoled_120hz_cmd
&dsi_vtdr6130_amoled_120hz_video>;
};

4
display/sun-sde-display-mtp-3-5mm-overlay.dts
View File

@@ -11,6 +11,8 @@
/ {
model = "Qualcomm Technologies, Inc. Sun MTP with 3.5mm";
compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp";
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
<0x100026a 0x10000>, <0x100026a 0x20000>,
<0x100027f 0x10000>, <0x100027f 0x20000>;
qcom,board-id = <0x60008 0>;
};

4
display/sun-sde-display-mtp-kiwi-overlay.dts
View File

@@ -11,6 +11,8 @@
/ {
model = "Qualcomm Technologies, Inc. Sun MTP Kiwi WLAN";
compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp";
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
<0x100026a 0x10000>, <0x100026a 0x20000>,
<0x100027f 0x10000>, <0x100027f 0x20000>;
qcom,board-id = <0x20008 0>;
};

6
display/sun-sde-display-mtp-kiwi-v8-overlay.dts
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
@@ -12,6 +12,8 @@
model = "Qualcomm Technologies, Inc. Sun MTP Kiwi WLAN V8 Power Grid";
compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp",
"qcom,mtp";
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
<0x100026a 0x10000>, <0x100026a 0x20000>,
<0x100027f 0x10000>, <0x100027f 0x20000>;
qcom,board-id = <0x50008 0>;
};

6
display/sun-sde-display-mtp-nfc-overlay.dts
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
@@ -11,6 +11,8 @@
/ {
model = "Qualcomm Technologies, Inc. Sun MTP SN300 NFC";
compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp";
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
<0x100026a 0x10000>, <0x100026a 0x20000>,
<0x100027f 0x10000>, <0x100027f 0x20000>;
qcom,board-id = <0x30008 0>;
};

4
display/sun-sde-display-mtp-overlay.dts
View File

@@ -11,6 +11,8 @@
/ {
model = "Qualcomm Technologies, Inc. Sun MTP";
compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp";
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
<0x100026a 0x10000>, <0x100026a 0x20000>,
<0x100027f 0x10000>, <0x100027f 0x20000>;
qcom,board-id = <8 0>;
};

6
display/sun-sde-display-mtp-qmp1000-overlay.dts
View File

@@ -11,6 +11,8 @@
/ {
model = "Qualcomm Technologies, Inc. Sun MTP QMP1000";
compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp";
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
qcom,board-id = <0x10108 0>;
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
<0x100026a 0x10000>, <0x100026a 0x20000>,
<0x100027f 0x10000>, <0x100027f 0x20000>;
qcom,board-id = <0x108 0>;
};

4
display/sun-sde-display-mtp-qmp1000-v8-overlay.dts
View File

@@ -11,6 +11,8 @@
/ {
model = "Qualcomm Technologies, Inc. Sun MTP QMP1000 V8 Power Grid";
compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp";
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
<0x100026a 0x10000>, <0x100026a 0x20000>,
<0x100027f 0x10000>, <0x100027f 0x20000>;
qcom,board-id = <0x40108 0>;
};

6
display/sun-sde-display-mtp-v8-overlay.dts
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
@@ -12,6 +12,8 @@
model = "Qualcomm Technologies, Inc. Sun MTP V8 Power Grid";
compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp",
"qcom,mtp";
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
<0x100026a 0x10000>, <0x100026a 0x20000>,
<0x100027f 0x10000>, <0x100027f 0x20000>;
qcom,board-id = <0x40008 0>;
};

13
display/sun-sde-display-mtp.dtsi
View File

@@ -111,6 +111,16 @@
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_nt37801_amoled_fhd_plus_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_vtdr6130_amoled_120hz_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
@@ -223,7 +233,8 @@
&dsi_nt37801_amoled_dsc_10b_video
&dsi_nt37801_amoled_cmd_spr
&dsi_nt37801_amoled_qsync_cmd
&dsi_nt37801_amoled_qsync_video>;
&dsi_nt37801_amoled_qsync_video
&dsi_nt37801_amoled_fhd_plus_cmd>;
};
};

6
display/sun-sde-display-qrd-sku1-overlay.dts
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
@@ -12,6 +12,8 @@
model = "Qualcomm Technologies, Inc. Sun QRD SKU1";
compatible = "qcom,sun-qrd", "qcom,sun", "qcom,sunp-qrd", "qcom,sunp",
"qcom,qrd";
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
<0x100026a 0x10000>, <0x100026a 0x20000>,
<0x100027f 0x10000>, <0x100027f 0x20000>;
qcom,board-id = <0x1000B 0>;
};

6
display/sun-sde-display-qrd-sku1-v8-overlay.dts
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
@@ -12,6 +12,8 @@
model = "Qualcomm Technologies, Inc. Sun QRD SKU1 V8 Power Grid";
compatible = "qcom,sun-qrd", "qcom,sun", "qcom,sunp-qrd", "qcom,sunp",
"qcom,qrd";
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
<0x100026a 0x10000>, <0x100026a 0x20000>,
<0x100027f 0x10000>, <0x100027f 0x20000>;
qcom,board-id = <0x3000B 0>;
};

6
display/sun-sde-display-qrd-sku2-v8-overlay.dts
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
@@ -12,6 +12,8 @@
model = "Qualcomm Technologies, Inc. Sun QRD SKU2 V8 Power Grid";
compatible = "qcom,sun-qrd", "qcom,sun", "qcom,sunp-qrd", "qcom,sunp",
"qcom,qrd";
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
<0x100026a 0x10000>, <0x100026a 0x20000>,
<0x100027f 0x10000>, <0x100027f 0x20000>;
qcom,board-id = <0x2000B 0>;
};

2
display/sun-sde-display-rcm-kiwi-overlay.dts
View File

@@ -11,6 +11,6 @@
/ {
model = "Qualcomm Technologies, Inc. Sun RCM Kiwi WLAN";
compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp-rcm", "qcom,sunp", "qcom,rcm";
qcom,msm-id = <618 0x10000>, <618 0x20000>;
qcom,msm-id = <618 0x10000>, <618 0x20000>, <0x100026a 0x10000>, <0x100026a 0x20000>;
qcom,board-id = <0x40015 0>;
};

2
display/sun-sde-display-rcm-kiwi-v8-overlay.dts
View File

@@ -11,6 +11,6 @@
/ {
model = "Qualcomm Technologies, Inc. Sun RCM Kiwi WLAN V8 Power Grid";
compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp-rcm", "qcom,sunp", "qcom,rcm";
qcom,msm-id = <618 0x10000>, <618 0x20000>;
qcom,msm-id = <618 0x10000>, <618 0x20000>, <0x100026a 0x10000>, <0x100026a 0x20000>;
qcom,board-id = <0x20015 0>;
};

4
display/sun-sde-display-rcm-overlay.dts
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
@@ -11,6 +11,6 @@
/ {
model = "Qualcomm Technologies, Inc. Sun RCM";
compatible = "qcom,sun-rcm", "qcom,sun", "qcom,rcm";
qcom,msm-id = <618 0x10000>, <618 0x20000>;
qcom,msm-id = <618 0x10000>, <618 0x20000>, <0x100026a 0x10000>, <0x100026a 0x20000>;
qcom,board-id = <0x15 0>;
};

2
display/sun-sde-display-rcm-v8-overlay.dts
View File

@@ -11,6 +11,6 @@
/ {
model = "Qualcomm Technologies, Inc. Sun RCM V8 Power Grid";
compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp-rcm", "qcom,sunp", "qcom,rcm";
qcom,msm-id = <618 0x10000>, <618 0x20000>;
qcom,msm-id = <618 0x10000>, <618 0x20000>, <0x100026a 0x10000>, <0x100026a 0x20000>;
qcom,board-id = <0x30015 0>;
};

70
display/sun-sde-display.dtsi
View File

@@ -58,6 +58,19 @@
reg = <0x0 0xfc800000 0x0 0x02b00000>;
label = "cont_splash_region";
};
/*
* Demura memory regions are to be commented out if
* feature not in use.
*/
demura_memory_0: demura_region_0 {
reg = <0x0 0x0 0x0 0x0>;
label = "demura hfc region 0";
};
demura_memory_1: demura_region_1 {
reg = <0x0 0x0 0x0 0x0>;
label = "demura hfc region 1";
};
};
&sde_dsi {
@@ -119,7 +132,8 @@
};
&mdss_mdp {
connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 &sde_dp>;
connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2
&sde_dp &sde_cesta>;
};
&dsi_vtdr6130_amoled_cmd {
@@ -155,42 +169,37 @@
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <0 0 720 40 1440 40>;
qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
};
timing@1 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <0 0 540 40 1080 40>;
qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
};
timing@2 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <0 0 720 40 1440 40>;
qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
};
timing@3 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <0 0 720 40 1440 40>;
qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
};
timing@4 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <0 0 720 40 1440 40>;
qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
};
timing@5 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <0 0 720 40 1440 40>;
qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
};
timing@6 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <0 0 720 40 1440 40>;
};
timing@7 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <0 0 720 40 1440 40>;
qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
};
};
};
@@ -199,17 +208,46 @@
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <0 0 720 40 1440 40>;
qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
};
timing@1 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <0 0 720 40 1440 40>;
qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
};
timing@2 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <0 0 720 40 1440 40>;
qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
};
};
};
&dsi_nt37801_amoled_fhd_plus_cmd {
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <540 40 540 40 1080 40>;
};
timing@1 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <540 40 540 40 1080 40>;
};
timing@2 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <540 40 540 40 1080 40>;
};
timing@3 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <540 40 540 40 1080 40>;
};
timing@4 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <540 40 540 40 1080 40>;
};
};
};

64
display/sun-sde.dtsi
View File

@@ -204,26 +204,63 @@
qcom,iommu-faults = "non-fatal";
qcom,iommu-vmid = <0xa>;
};
sde_cesta: qcom,sde_cesta@0x0af30000 {
cell-index = <0>;
compatible = "qcom,sde-cesta";
reg = <0xaf30000 0x60>,
<0xaf31000 0x30>,
<0xaf32000 0x30>,
<0xaf33000 0x30>,
<0xaf34000 0x30>,
<0xaf35000 0x30>,
<0xaf36000 0x30>;
reg-names = "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5";
clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK_SRC>;
clock-names = "branch_clk", "core_clk";
clock-rate = <575000000 575000000>;
clock-max-rate = <575000000 575000000>;
clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC>;
interconnects = <&mmss_noc MASTER_MDP_DISP_CRM_HW_0
&mc_virt SLAVE_EBI1_DISP_CRM_HW_0>,
<&mmss_noc MASTER_MDP_DISP_CRM_HW_1
&mc_virt SLAVE_EBI1_DISP_CRM_HW_1>,
<&mmss_noc MASTER_MDP_DISP_CRM_HW_2
&mc_virt SLAVE_EBI1_DISP_CRM_HW_2>,
<&mmss_noc MASTER_MDP_DISP_CRM_HW_3
&mc_virt SLAVE_EBI1_DISP_CRM_HW_3>,
<&mmss_noc MASTER_MDP_DISP_CRM_HW_4
&mc_virt SLAVE_EBI1_DISP_CRM_HW_4>,
<&mmss_noc MASTER_MDP_DISP_CRM_HW_5
&mc_virt SLAVE_EBI1_DISP_CRM_HW_5>,
<&mmss_noc MASTER_MDP_DISP_CRM_SW_0
&mc_virt SLAVE_EBI1_DISP_CRM_SW_0>;
interconnect-names = "qcom,sde-data-bus-hw-0", "qcom,sde-data-bus-hw-1",
"qcom,sde-data-bus-hw-2", "qcom,sde-data-bus-hw-3",
"qcom,sde-data-bus-hw-4", "qcom,sde-data-bus-hw-5",
"qcom,sde-data-bus-sw-0";
power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
};
};
&mdss_mdp {
clocks =
<&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK_SRC>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>,
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>;
clock-names = "gcc_bus",
"iface_clk", "branch_clk", "core_clk", "vsync_clk",
"lut_clk";
clock-rate = <0 0 575000000 575000000 19200000 575000000>;
clock-max-rate = <0 0 575000000 575000000 19200000 575000000>;
clock-mmrm = <0 0 0 DISP_CC_MDSS_MDP_CLK_SRC 0 0>;
clock-names = "gcc_bus", "iface_clk", "vsync_clk", "lut_clk";
clock-rate = <0 0 19200000 575000000>;
clock-max-rate = <0 0 19200000 575000000>;
qcom,hw-fence-sw-version = <0x1>;
vdd-supply = <&disp_cc_mdss_core_gdsc>;
mmcx-supply = <&VDD_MMCX_LEVEL>;
qti,smmu-proxy-cb-id = <QTI_SMMU_PROXY_DISPLAY_CB>;
@@ -262,15 +299,6 @@
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
};
qcom,platform-supply-entry@1 {
reg = <1>;
qcom,supply-name = "vdd";
qcom,supply-min-voltage = <0>;
qcom,supply-max-voltage = <0>;
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
};
};
};

8
display/trustedvm-sun-sde.dtsi
View File

@@ -37,6 +37,14 @@
qcom,sde-vm-exclude-reg-names = "sid_phys";
qcom,tvm-include-reg = <0xaf30000 0x60>,
<0xaf31000 0x30>,
<0xaf32000 0x30>,
<0xaf33000 0x30>,
<0xaf34000 0x30>,
<0xaf35000 0x30>,
<0xaf36000 0x30>;
qcom,sde-hw-version =<0xC0000000>;
clocks = <&clock_cpucc GCC_DISP_AHB_CLK>,