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ARM: dts: msm: add xo clock in sde_cesta for kera target

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Add xo clock in sde_cesta for kera target. This will help
to vote for xo frequency during cesta idle time.

Change-Id: Ic4370c8a49ffbec2743c022e438280d371a5a968
Signed-off-by: Sailesh Reddy Male <quic_reddymal@quicinc.com>
This commit is contained in:
Sailesh Reddy Male
2025-01-20 15:07:40 +05:30
committed by Vishvanath Singh
parent 97a28e65f9
commit 01b4df928e
1 changed files with 6 additions and 5 deletions
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11
display/kera-sde.dtsi
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@@ -222,12 +222,13 @@
reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5"; reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5";
clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>,
<&dispcc DISP_CC_XO_CLK_SRC>;
clock-names = "branch_clk", "core_clk"; clock-names = "branch_clk", "core_clk", "xo";
clock-rate = <660000000 660000000>; clock-rate = <660000000 660000000 19200000>;
clock-max-rate = <660000000 660000000>; clock-max-rate = <660000000 660000000 19200000>;
clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC>; clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC 0>;
interconnects = <&mmss_noc MASTER_MDP_DISP_CRM_HW_0 interconnects = <&mmss_noc MASTER_MDP_DISP_CRM_HW_0
&mc_virt SLAVE_EBI1_DISP_CRM_HW_0>, &mc_virt SLAVE_EBI1_DISP_CRM_HW_0>,