From 01b4df928e22a26f0ab689daa650625ca7a8b525 Mon Sep 17 00:00:00 2001 From: Sailesh Reddy Male Date: Mon, 20 Jan 2025 15:07:40 +0530 Subject: [PATCH] ARM: dts: msm: add xo clock in sde_cesta for kera target Add xo clock in sde_cesta for kera target. This will help to vote for xo frequency during cesta idle time. Change-Id: Ic4370c8a49ffbec2743c022e438280d371a5a968 Signed-off-by: Sailesh Reddy Male --- display/kera-sde.dtsi | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/display/kera-sde.dtsi b/display/kera-sde.dtsi index 8c06d42e..1148e017 100644 --- a/display/kera-sde.dtsi +++ b/display/kera-sde.dtsi @@ -222,12 +222,13 @@ reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5"; clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, + <&dispcc DISP_CC_XO_CLK_SRC>; - clock-names = "branch_clk", "core_clk"; - clock-rate = <660000000 660000000>; - clock-max-rate = <660000000 660000000>; - clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC>; + clock-names = "branch_clk", "core_clk", "xo"; + clock-rate = <660000000 660000000 19200000>; + clock-max-rate = <660000000 660000000 19200000>; + clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC 0>; interconnects = <&mmss_noc MASTER_MDP_DISP_CRM_HW_0 &mc_virt SLAVE_EBI1_DISP_CRM_HW_0>,