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ARM: dts: msm: Define dtsi property memory-region in SVM Kera and Tuna

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Property memory-region is not defined for secure I2C/SPI QUP wrapper
instance and GPI instance. Updated the property correctly now.

Fixes: f1bff316cc ("ARM: dts: msm: Add spi, i2c, gpi nodes for SVM tuna")
Fixes: e6e2aa812d ("ARM: dts: msm: Add spi, i2c, gpi nodes for SVM kera")
Change-Id: I9f43e38ea78c90009708070beca75e3a93bf5424
Signed-off-by: Prasanna S <quic_prass@quicinc.com>
This commit is contained in:
Prasanna S
2024-11-21 15:11:18 +05:30
parent 8b185ef3d6
commit 00b06e64e6
2 changed files with 8 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
qcom/kera-vm.dtsi
View File

@@ -309,6 +309,7 @@
reg-names = "gpi-top"; reg-names = "gpi-top";
iommus = <&apps_smmu 0xb8 0x0>; iommus = <&apps_smmu 0xb8 0x0>;
qcom,iommu-group = <&qup_iommu_group>; qcom,iommu-group = <&qup_iommu_group>;
memory-region = <&qup_iommu_group>;
dma-coherent; dma-coherent;
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
@@ -342,6 +343,7 @@
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
iommus = <&apps_smmu 0xb8 0x0>; iommus = <&apps_smmu 0xb8 0x0>;
qcom,iommu-group = <&qup_iommu_group>; qcom,iommu-group = <&qup_iommu_group>;
memory-region = <&qup_iommu_group>;
dma-coherent; dma-coherent;
ranges; ranges;
status = "ok"; status = "ok";
@@ -383,6 +385,7 @@
reg-names = "gpi-top"; reg-names = "gpi-top";
iommus = <&apps_smmu 0x438 0x0>; iommus = <&apps_smmu 0x438 0x0>;
qcom,iommu-group = <&qup_iommu_group>; qcom,iommu-group = <&qup_iommu_group>;
memory-region = <&qup_iommu_group>;
dma-coherent; dma-coherent;
interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
@@ -416,6 +419,7 @@
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
iommus = <&apps_smmu 0x438 0x0>; iommus = <&apps_smmu 0x438 0x0>;
qcom,iommu-group = <&qup_iommu_group>; qcom,iommu-group = <&qup_iommu_group>;
memory-region = <&qup_iommu_group>;
dma-coherent; dma-coherent;
ranges; ranges;
status = "ok"; status = "ok";

4
qcom/tuna-vm.dtsi
View File

@@ -564,6 +564,7 @@
reg-names = "gpi-top"; reg-names = "gpi-top";
iommus = <&apps_smmu 0xb8 0x0>; iommus = <&apps_smmu 0xb8 0x0>;
qcom,iommu-group = <&qup_iommu_group>; qcom,iommu-group = <&qup_iommu_group>;
memory-region = <&qup_iommu_group>;
dma-coherent; dma-coherent;
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
@@ -597,6 +598,7 @@
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
iommus = <&apps_smmu 0xb8 0x0>; iommus = <&apps_smmu 0xb8 0x0>;
qcom,iommu-group = <&qup_iommu_group>; qcom,iommu-group = <&qup_iommu_group>;
memory-region = <&qup_iommu_group>;
dma-coherent; dma-coherent;
ranges; ranges;
status = "ok"; status = "ok";
@@ -638,6 +640,7 @@
reg-names = "gpi-top"; reg-names = "gpi-top";
iommus = <&apps_smmu 0x438 0x0>; iommus = <&apps_smmu 0x438 0x0>;
qcom,iommu-group = <&qup_iommu_group>; qcom,iommu-group = <&qup_iommu_group>;
memory-region = <&qup_iommu_group>;
dma-coherent; dma-coherent;
interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
@@ -671,6 +674,7 @@
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
iommus = <&apps_smmu 0x438 0x0>; iommus = <&apps_smmu 0x438 0x0>;
qcom,iommu-group = <&qup_iommu_group>; qcom,iommu-group = <&qup_iommu_group>;
memory-region = <&qup_iommu_group>;
dma-coherent; dma-coherent;
ranges; ranges;
status = "ok"; status = "ok";