260 lines
7.8 KiB
C
260 lines
7.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2010-2015,2019 The Linux Foundation. All rights reserved.
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* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef __QCOM_SCM_INT_H
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#define __QCOM_SCM_INT_H
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#include <linux/semaphore.h>
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enum qcom_scm_convention {
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SMC_CONVENTION_UNKNOWN,
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SMC_CONVENTION_LEGACY,
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SMC_CONVENTION_ARM_32,
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SMC_CONVENTION_ARM_64,
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};
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extern enum qcom_scm_convention qcom_scm_convention;
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extern struct semaphore qcom_scm_sem_lock;
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#define MAX_QCOM_SCM_ARGS 10
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#define MAX_QCOM_SCM_RETS 3
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enum qcom_scm_arg_types {
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QCOM_SCM_VAL,
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QCOM_SCM_RO,
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QCOM_SCM_RW,
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QCOM_SCM_BUFVAL,
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};
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#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
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(((a) & 0x3) << 4) | \
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(((b) & 0x3) << 6) | \
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(((c) & 0x3) << 8) | \
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(((d) & 0x3) << 10) | \
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(((e) & 0x3) << 12) | \
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(((f) & 0x3) << 14) | \
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(((g) & 0x3) << 16) | \
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(((h) & 0x3) << 18) | \
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(((i) & 0x3) << 20) | \
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(((j) & 0x3) << 22) | \
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((num) & 0xf))
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#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
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/**
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* struct qcom_scm_desc
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* @arginfo: Metadata describing the arguments in args[]
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* @args: The array of arguments for the secure syscall
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*/
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struct qcom_scm_desc {
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u32 svc;
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u32 cmd;
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u32 arginfo;
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u64 args[MAX_QCOM_SCM_ARGS];
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u32 owner;
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bool multicall_allowed;
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};
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/**
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* struct qcom_scm_res
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* @result: The values returned by the secure syscall
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*/
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struct qcom_scm_res {
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u64 result[MAX_QCOM_SCM_RETS];
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};
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enum qcom_scm_call_type {
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QCOM_SCM_CALL_NORMAL,
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QCOM_SCM_CALL_ATOMIC,
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QCOM_SCM_CALL_NORETRY,
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};
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enum qcom_scm_wq_feature {
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QCOM_SCM_SINGLE_SMC_ALLOW,
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QCOM_SCM_MULTI_SMC_WHITE_LIST_ALLOW, /* Release global lock for certain allowed SMC calls */
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};
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struct qcom_scm;
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extern struct completion *qcom_scm_lookup_wq(struct qcom_scm *scm, u32 wq_ctx);
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extern void scm_waitq_flag_handler(struct completion *wq, u32 flags);
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extern int scm_get_wq_ctx(u32 *wq_ctx, u32 *flags, u32 *more_pending);
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extern bool qcom_scm_multi_call_allow(struct device *dev, bool multicall_allowed);
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#define SCM_SMC_FNID(s, c) ((((s) & 0xFF) << 8) | ((c) & 0xFF))
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extern int __scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,
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enum qcom_scm_convention qcom_convention,
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struct qcom_scm_res *res, enum qcom_scm_call_type call_type);
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#define scm_smc_call(dev, desc, res, call_type) \
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__scm_smc_call((dev), (desc), qcom_scm_convention, (res), (call_type))
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#define SCM_LEGACY_FNID(s, c) (((s) << 10) | ((c) & 0x3ff))
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extern int scm_legacy_call_atomic(struct device *dev,
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const struct qcom_scm_desc *desc,
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struct qcom_scm_res *res);
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extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc,
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struct qcom_scm_res *res);
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#define QCOM_SCM_SVC_BOOT 0x01
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#define QCOM_SCM_BOOT_SET_ADDR 0x01
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#define QCOM_SCM_BOOT_TERMINATE_PC 0x02
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#define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10
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#define QCOM_SCM_BOOT_SEC_WDOG_DIS 0x07
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#define QCOM_SCM_BOOT_SEC_WDOG_TRIGGER 0x08
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#define QCOM_SCM_BOOT_WDOG_DEBUG_PART 0x09
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#define QCOM_SCM_BOOT_SET_ADDR_MC 0x11
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#define QCOM_SCM_BOOT_SPIN_CPU 0x0d
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#define QCOM_SCM_BOOT_SWITCH_MODE 0x0f
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#define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10
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#define QCOM_SCM_BOOT_CONFIG_CPU_ERRATA 0x12
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#define QCOM_SCM_BOOT_SET_REMOTE_STATE 0x0a
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#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
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#define QCOM_SCM_BOOT_MAX_CPUS 4
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#define QCOM_SCM_BOOT_MC_FLAG_AARCH64 BIT(0)
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#define QCOM_SCM_BOOT_MC_FLAG_COLDBOOT BIT(1)
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#define QCOM_SCM_BOOT_MC_FLAG_WARMBOOT BIT(2)
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#define QCOM_SCM_SVC_PIL 0x02
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#define QCOM_SCM_PIL_PAS_INIT_IMAGE 0x01
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#define QCOM_SCM_PIL_PAS_MEM_SETUP 0x02
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#define QCOM_SCM_PIL_PAS_AUTH_AND_RESET 0x05
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#define QCOM_SCM_PIL_PAS_SHUTDOWN 0x06
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#define QCOM_SCM_PIL_PAS_IS_SUPPORTED 0x07
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#define QCOM_SCM_PIL_PAS_MSS_RESET 0x0a
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#define QCOM_SCM_SVC_UTIL 0x03
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#define QCOM_SCM_UTIL_GET_SEC_DUMP_STATE 0x10
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#define QCOM_SCM_UTIL_DUMP_TABLE_ASSIGN 0x13
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#define QCOM_SCM_SVC_IO 0x05
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#define QCOM_SCM_IO_READ 0x01
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#define QCOM_SCM_IO_WRITE 0x02
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#define QCOM_SCM_IO_RESET 0x03
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#define QCOM_SCM_SVC_INFO 0x06
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#define QCOM_SCM_INFO_IS_CALL_AVAIL 0x01
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#define QCOM_SCM_INFO_GET_FEAT_VERSION_CMD 0x03
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#define QCOM_SCM_SVC_PWR 0x09
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#define QCOM_SCM_PWR_IO_DISABLE_PMIC_ARBITER 0x01
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#define QCOM_SCM_SVC_MP 0x0c
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#define QCOM_SCM_MP_RESTORE_SEC_CFG 0x02
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#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE 0x03
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#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT 0x04
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#define QCOM_SCM_MP_IOMMU_SET_CP_POOL_SIZE 0x05
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#define QCOM_SCM_MP_VIDEO_VAR 0x08
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#define QCOM_SCM_MP_MEM_PROTECT_REGION_ID 0x10
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#define QCOM_SCM_MP_ASSIGN 0x16
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#define QCOM_SCM_MP_CMD_SD_CTRL 0x18
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#define QCOM_SCM_MP_CP_SMMU_APERTURE_ID 0x1b
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#define QCOM_SCM_MEMP_SHM_BRIDGE_ENABLE 0x1c
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#define QCOM_SCM_MEMP_SHM_BRIDGE_DELETE 0x1d
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#define QCOM_SCM_MEMP_SHM_BRDIGE_CREATE 0x1e
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#define QCOM_SCM_CP_APERTURE_REG 0x0
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#define QCOM_SCM_CP_LPAC_APERTURE_REG 0x1
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#define QCOM_SCM_SVC_DCVS 0x0D
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#define QCOM_SCM_DCVS_RESET 0x07
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#define QCOM_SCM_DCVS_UPDATE 0x08
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#define QCOM_SCM_DCVS_INIT 0x09
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#define QCOM_SCM_DCVS_UPDATE_V2 0x0a
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#define QCOM_SCM_DCVS_INIT_V2 0x0b
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#define QCOM_SCM_DCVS_INIT_CA_V2 0x0c
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#define QCOM_SCM_DCVS_UPDATE_CA_V2 0x0d
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#define QCOM_SCM_DCVS_TUNING 0x0e
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#define QCOM_SCM_SVC_OCMEM 0x0f
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#define QCOM_SCM_OCMEM_LOCK_CMD 0x01
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#define QCOM_SCM_OCMEM_UNLOCK_CMD 0x02
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#define QCOM_SCM_SVC_ES 0x10 /* Enterprise Security */
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#define QCOM_SCM_ES_INVALIDATE_ICE_KEY 0x03
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#define QCOM_SCM_ES_CONFIG_SET_ICE_KEY 0x04
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#define QCOM_SCM_ES_CONFIG_SET_ICE_KEY_V2 0x05
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#define QCOM_SCM_ES_CLEAR_ICE_KEY 0x06
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#define QCOM_SCM_ES_DERIVE_RAW_SECRET 0x07
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#define QCOM_SCM_SVC_HDCP 0x11
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#define QCOM_SCM_HDCP_INVOKE 0x01
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#define QCOM_SCM_SVC_LMH 0x13
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#define QCOM_SCM_LMH_LIMIT_PROFILE_CHANGE 0x01
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#define QCOM_SCM_LMH_LIMIT_DCVSH 0x10
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#define QCOM_SCM_LMH_DEBUG_FETCH_DATA 0x0D
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#define QCOM_SCM_SVC_SMMU_PROGRAM 0x15
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#define QCOM_SCM_SMMU_PT_FORMAT 0x01
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#define QCOM_SCM_SMMU_SECURE_LUT 0x03
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#define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x03
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#define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x02
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#define QCOM_SCM_SVC_CAMERA 0x18
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#define QCOM_SCM_CAMERA_PROTECT_ALL 0x06
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#define QCOM_SCM_CAMERA_PROTECT_PHY_LANES 0x07
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#define QCOM_SCM_CAMERA_UPDATE_CAMNOC_QOS 0x0A
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#define QCOM_SCM_SVC_WAITQ 0x24
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#define QCOM_SCM_WAITQ_ACK 0x01
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#define QCOM_SCM_WAITQ_RESUME 0x02
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#define QCOM_SCM_WAITQ_GET_WQ_CTX 0x03
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#define QCOM_SCM_GET_WQ_QUEUE_INFO 0x04
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#define QCOM_SCM_SVC_TSENS 0x1E
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#define QCOM_SCM_TSENS_INIT_ID 0x5
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/* OEM Services and Function IDs */
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#define QCOM_SCM_SVC_OEM_POWER 0x09
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#define QCOM_SCM_OEM_POWER_REBOOT 0x22
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/* GPU Service IDs */
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#define QCOM_SCM_SVC_GPU 0x28
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#define QCOM_SCM_SVC_GPU_INIT_REGS 0x1
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/* TOS Services and Function IDs */
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#define QCOM_SCM_SVC_QSEELOG 0x01
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#define QCOM_SCM_QSEELOG_REGISTER 0x06
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#define QCOM_SCM_QUERY_ENCR_LOG_FEAT_ID 0x0b
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#define QCOM_SCM_REQUEST_ENCR_LOG_ID 0x0c
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#define QCOM_SCM_SVC_SMCINVOKE 0x06
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#define QCOM_SCM_SMCINVOKE_INVOKE_LEGACY 0x00
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#define QCOM_SCM_SMCINVOKE_INVOKE 0x02
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#define QCOM_SCM_SMCINVOKE_CB_RSP 0x01
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/* Feature IDs for QCOM_SCM_INFO_GET_FEAT_VERSION */
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#define QCOM_SCM_FEAT_LOG_ID 0x0a
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#define QCOM_SCM_SVC_WAITQ 0x24
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#define QCOM_SCM_WAITQ_RESUME 0x02
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#define QCOM_SCM_WAITQ_GET_WQ_CTX 0x03
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/* common error codes */
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#define QCOM_SCM_V2_EBUSY -12
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#define QCOM_SCM_ENOMEM -5
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#define QCOM_SCM_EOPNOTSUPP -4
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#define QCOM_SCM_EINVAL_ADDR -3
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#define QCOM_SCM_EINVAL_ARG -2
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#define QCOM_SCM_ERROR -1
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#define QCOM_SCM_INTERRUPTED 1
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#define QCOM_SCM_WAITQ_SLEEP 2
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#define QCOM_SCM_WAITQ_WAKE 3
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static inline int qcom_scm_remap_error(int err)
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{
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switch (err) {
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case QCOM_SCM_ERROR:
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return -EIO;
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case QCOM_SCM_EINVAL_ADDR:
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case QCOM_SCM_EINVAL_ARG:
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return -EINVAL;
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case QCOM_SCM_EOPNOTSUPP:
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return -EOPNOTSUPP;
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case QCOM_SCM_ENOMEM:
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return -ENOMEM;
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case QCOM_SCM_V2_EBUSY:
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return -EBUSY;
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}
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return -EINVAL;
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}
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#endif
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