525 lines
16 KiB
C
525 lines
16 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef __MSM_GPI_H_
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#define __MSM_GPI_H_
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#include <linux/types.h>
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struct __packed msm_gpi_tre {
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u32 dword[4];
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};
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enum GPI_EV_TYPE {
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XFER_COMPLETE_EV_TYPE = 0x22,
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IMMEDIATE_DATA_EV_TYPE = 0x30,
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QUP_NOTIF_EV_TYPE = 0x31,
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STALE_EV_TYPE = 0xFF,
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QUP_TCE_TYPE_Q2SPI_STATUS = 0x35,
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QUP_TCE_TYPE_Q2SPI_CR_HEADER = 0x36,
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};
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enum Q2SPI_CR_HEADER_CODE {
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Q2SPI_CR_CODE_SUCCESS = 0x1,
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Q2SPI_CR_HEADER_LEN_ZERO = 0xB,
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Q2SPI_CR_HEADER_INCORRECT = 0xC,
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};
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enum msm_gpi_tre_type {
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MSM_GPI_TRE_INVALID = 0x00,
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MSM_GPI_TRE_NOP = 0x01,
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MSM_GPI_TRE_DMA_W_BUF = 0x10,
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MSM_GPI_TRE_DMA_IMMEDIATE = 0x11,
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MSM_GPI_TRE_DMA_W_SG_LIST = 0x12,
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MSM_GPI_TRE_GO = 0x20,
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MSM_GPI_TRE_CONFIG0 = 0x22,
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MSM_GPI_TRE_CONFIG1 = 0x23,
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MSM_GPI_TRE_CONFIG2 = 0x24,
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MSM_GPI_TRE_CONFIG3 = 0x25,
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MSM_GPI_TRE_LOCK = 0x30,
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MSM_GPI_TRE_UNLOCK = 0x31,
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};
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#define MSM_GPI_TRE_TYPE(tre) ((tre->dword[3] >> 16) & 0xFF)
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/* Lock TRE */
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#define MSM_GPI_LOCK_TRE_DWORD0 (0)
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#define MSM_GPI_LOCK_TRE_DWORD1 (0)
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#define MSM_GPI_LOCK_TRE_DWORD2 (0)
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#define MSM_GPI_LOCK_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) \
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((0x3 << 20) | (0x0 << 16) | (link_rx << 11) | (bei << 10) | \
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(ieot << 9) | (ieob << 8) | ch)
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/* Unlock TRE */
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#define MSM_GPI_UNLOCK_TRE_DWORD0 (0)
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#define MSM_GPI_UNLOCK_TRE_DWORD1 (0)
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#define MSM_GPI_UNLOCK_TRE_DWORD2 (0)
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#define MSM_GPI_UNLOCK_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) \
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((0x3 << 20) | (0x1 << 16) | (link_rx << 11) | (bei << 10) | \
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(ieot << 9) | (ieob << 8) | ch)
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/* DMA w. Buffer TRE */
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#ifdef CONFIG_ARM64
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#define MSM_GPI_DMA_W_BUFFER_TRE_DWORD0(ptr) ((u32)ptr)
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#define MSM_GPI_DMA_W_BUFFER_TRE_DWORD1(ptr) ((u32)(ptr >> 32))
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#else
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#define MSM_GPI_DMA_W_BUFFER_TRE_DWORD0(ptr) (ptr)
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#define MSM_GPI_DMA_W_BUFFER_TRE_DWORD1(ptr) 0
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#endif
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#define MSM_GPI_DMA_W_BUFFER_TRE_DWORD2(length) (length & 0xFFFFFF)
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#define MSM_GPI_DMA_W_BUFFER_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) \
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((0x1 << 20) | (0x0 << 16) | (link_rx << 11) | (bei << 10) | \
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(ieot << 9) | (ieob << 8) | ch)
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#define MSM_GPI_DMA_W_BUFFER_TRE_GET_LEN(tre) (tre->dword[2] & 0xFFFFFF)
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#define MSM_GPI_DMA_W_BUFFER_TRE_SET_LEN(tre, length) (tre->dword[2] = \
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MSM_GPI_DMA_W_BUFFER_TRE_DWORD2(length))
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/* DMA Immediate TRE */
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#define MSM_GPI_DMA_IMMEDIATE_TRE_DWORD0(d3, d2, d1, d0) ((d3 << 24) | \
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(d2 << 16) | (d1 << 8) | (d0))
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#define MSM_GPI_DMA_IMMEDIATE_TRE_DWORD1(d4, d5, d6, d7) ((d7 << 24) | \
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(d6 << 16) | (d5 << 8) | (d4))
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#define MSM_GPI_DMA_IMMEDIATE_TRE_DWORD2(length) (length & 0xF)
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#define MSM_GPI_DMA_IMMEDIATE_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) \
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((0x1 << 20) | (0x1 << 16) | (link_rx << 11) | (bei << 10) | \
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(ieot << 9) | (ieob << 8) | ch)
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#define MSM_GPI_DMA_IMMEDIATE_TRE_GET_LEN(tre) (tre->dword[2] & 0xF)
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/* DMA w. Scatter/Gather List TRE */
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#ifdef CONFIG_ARM64
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#define MSM_GPI_SG_LIST_TRE_DWORD0(ptr) ((u32)ptr)
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#define MSM_GPI_SG_LIST_TRE_DWORD1(ptr) ((u32)(ptr >> 32))
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#else
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#define MSM_GPI_SG_LIST_TRE_DWORD0(ptr) (ptr)
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#define MSM_GPI_SG_LIST_TRE_DWORD1(ptr) 0
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#endif
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#define MSM_GPI_SG_LIST_TRE_DWORD2(length) (length & 0xFFFF)
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#define MSM_GPI_SG_LIST_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) ((0x1 << 20) \
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| (0x2 << 16) | (link_rx << 11) | (bei << 10) | (ieot << 9) | \
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(ieob << 8) | ch)
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/* SG Element */
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#ifdef CONFIG_ARM64
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#define MSM_GPI_SG_ELEMENT_DWORD0(ptr) ((u32)ptr)
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#define MSM_GPI_SG_ELEMENT_DWORD1(ptr) ((u32)(ptr >> 32))
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#else
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#define MSM_GPI_SG_ELEMENT_DWORD0(ptr) (ptr)
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#define MSM_GPI_SG_ELEMENT_DWORD1(ptr) 0
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#endif
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#define MSM_GSI_SG_ELEMENT_DWORD2(length) (length & 0xFFFFF)
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#define MSM_GSI_SG_ELEMENT_DWORD3 (0)
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/* Config2 TRE */
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#define GPI_CONFIG2_TRE_DWORD0(gr, txp) ((gr << 20) | (txp))
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#define GPI_CONFIG2_TRE_DWORD1(txp) (txp)
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#define GPI_CONFIG2_TRE_DWORD2 (0)
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#define GPI_CONFIG2_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) ((0x2 << 20) | \
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(0x4 << 16) | (link_rx << 11) | (bei << 10) | (ieot << 9) | \
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(ieob << 8) | ch)
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/* Config3 TRE */
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#define GPI_CONFIG3_TRE_DWORD0(rxp) (rxp)
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#define GPI_CONFIG3_TRE_DWORD1(rxp) (rxp)
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#define GPI_CONFIG3_TRE_DWORD2 (0)
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#define GPI_CONFIG3_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) ((0x2 << 20) \
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| (0x5 << 16) | (link_rx << 11) | (bei << 10) | (ieot << 9) | \
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(ieob << 8) | ch)
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/* SPI Go TRE */
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#define MSM_GPI_SPI_GO_TRE_DWORD0(flags, cs, command) ((flags << 24) | \
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(cs << 8) | command)
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#define MSM_GPI_SPI_GO_TRE_DWORD1 (0)
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#define MSM_GPI_SPI_GO_TRE_DWORD2(rx_len) (rx_len)
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#define MSM_GPI_SPI_GO_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) ((0x2 << 20) | \
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(0x0 << 16) | (link_rx << 11) | (bei << 10) | (ieot << 9) | \
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(ieob << 8) | ch)
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/* SPI Config0 TRE */
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#define MSM_GPI_SPI_CONFIG0_TRE_DWORD0(pack, flags, word_size) ((pack << 24) | \
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(flags << 8) | word_size)
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#define MSM_GPI_SPI_CONFIG0_TRE_DWORD1(it_del, cs_clk_del, iw_del) \
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((it_del << 16) | (cs_clk_del << 8) | iw_del)
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#define MSM_GPI_SPI_CONFIG0_TRE_DWORD2(clk_src, clk_div) ((clk_src << 16) | \
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clk_div)
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#define MSM_GPI_SPI_CONFIG0_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) \
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((0x2 << 20) | (0x2 << 16) | (link_rx << 11) | (bei << 10) | \
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(ieot << 9) | (ieob << 8) | ch)
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/* UART Go TRE */
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#define MSM_GPI_UART_GO_TRE_DWORD0(en_hunt, command) ((en_hunt << 8) | command)
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#define MSM_GPI_UART_GO_TRE_DWORD1 (0)
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#define MSM_GPI_UART_GO_TRE_DWORD2 (0)
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#define MSM_GPI_UART_GO_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) ((0x2 << 20) \
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| (0x0 << 16) | (link_rx << 11) | (bei << 10) | (ieot << 9) | \
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(ieob << 8) | ch)
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/* UART Config0 TRE */
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#define MSM_GPI_UART_CONFIG0_TRE_DWORD0(pack, hunt, flags, parity, sbl, size) \
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((pack << 24) | (hunt << 16) | (flags << 8) | (parity << 5) | \
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(sbl << 3) | size)
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#define MSM_GPI_UART_CONFIG0_TRE_DWORD1(rfr_level, rx_stale) \
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((rfr_level << 24) | rx_stale)
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#define MSM_GPI_UART_CONFIG0_TRE_DWORD2(clk_source, clk_div) \
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((clk_source << 16) | clk_div)
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#define MSM_GPI_UART_CONFIG0_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) \
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((0x2 << 20) | (0x2 << 16) | (link_rx << 11) | (bei << 10) | \
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(ieot << 9) | (ieob << 8) | ch)
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/* I2C GO TRE */
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#define MSM_GPI_I2C_GO_TRE_DWORD0(flags, slave, opcode) \
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((flags << 24) | (slave << 8) | opcode)
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#define MSM_GPI_I2C_GO_TRE_DWORD1 (0)
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#define MSM_GPI_I2C_GO_TRE_DWORD2(rx_len) (rx_len)
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#define MSM_GPI_I2C_GO_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) ((0x2 << 20) | \
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(0x0 << 16) | (link_rx << 11) | (bei << 10) | (ieot << 9) | \
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(ieob << 8) | ch)
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/* I2C Config0 TRE */
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#define MSM_GPI_I2C_CONFIG0_TRE_DWORD0(pack, t_cycle, t_high, t_low) \
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((pack << 24) | (t_cycle << 16) | (t_high << 8) | t_low)
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#define MSM_GPI_I2C_CONFIG0_TRE_DWORD1(inter_delay, noise_rej) \
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((inter_delay << 16) | noise_rej)
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#define MSM_GPI_I2C_CONFIG0_TRE_DWORD2(clk_src, clk_div) \
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((clk_src << 16) | clk_div)
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#define MSM_GPI_I2C_CONFIG0_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) \
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((0x2 << 20) | (0x2 << 16) | (link_rx << 11) | (bei << 10) | \
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(ieot << 9) | (ieob << 8) | ch)
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/* I3C GO TRE */
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#define MSM_GPI_I3C_GO_TRE_DWORD0(flags, ccc_hdr, slave, opcode) \
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((flags << 24) | (ccc_hdr << 16) | (slave << 8) | opcode)
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#define MSM_GPI_I3C_GO_TRE_DWORD1(flags) (flags)
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#define MSM_GPI_I3C_GO_TRE_DWORD2(rx_len) (rx_len)
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#define MSM_GPI_I3C_GO_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) ((0x2 << 20) | \
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(0x0 << 16) | (link_rx << 11) | (bei << 10) | (ieot << 9) | \
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(ieob << 8) | ch)
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/* I3C Config0 TRE */
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#define MSM_GPI_I3C_CONFIG0_TRE_DWORD0(pack, t_cycle, t_high, t_low) \
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((pack << 24) | (t_cycle << 16) | (t_high << 8) | t_low)
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#define MSM_GPI_I3C_CONFIG0_TRE_DWORD1(inter_delay, t_cycle, t_high) \
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((inter_delay << 16) | (t_cycle << 8) | t_high)
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#define MSM_GPI_I3C_CONFIG0_TRE_DWORD2(clk_src, clk_div) \
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((clk_src << 16) | clk_div)
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#define MSM_GPI_I3C_CONFIG0_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) \
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((0x2 << 20) | (0x2 << 16) | (link_rx << 11) | (bei << 10) | \
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(ieot << 9) | (ieob << 8) | ch)
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#ifdef CONFIG_ARM64
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#define MSM_GPI_RING_PHYS_ADDR_UPPER(ptr) ((u32)(ptr >> 32))
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#else
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#define MSM_GPI_RING_PHYS_ADDR_UPPER(ptr) 0
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#endif
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/* Static GPII here uses bit5 bit4 bit3 bit2 bit1(xxx1 111x) */
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#define STATIC_GPII_BMSK (0x1e)
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#define STATIC_GPII_SHFT (0x1)
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#define GPI_EV_PRIORITY_BMSK (0x1)
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#define GSI_SE_ERR(log_ctx, print, dev, x...) do { \
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ipc_log_string(log_ctx, x); \
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if (print) { \
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if (dev) \
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dev_err((dev), x); \
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else \
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pr_err(x); \
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} \
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} while (0)
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#define GSI_SE_DBG(log_ctx, print, dev, x...) do { \
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ipc_log_string(log_ctx, x); \
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if (print) { \
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if (dev) \
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dev_dbg((dev), x); \
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else \
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pr_debug(x); \
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} \
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} while (0)
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#define LOCK_TRE_SET BIT(0)
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#define CONFIG_TRE_SET BIT(1)
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#define GO_TRE_SET BIT(2)
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#define DMA_TRE_SET BIT(3)
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#define UNLOCK_TRE_SET BIT(4)
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#define GSI_MAX_TRE_TYPES (5)
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#define GSI_MAX_NUM_TRE_MSGS (448)
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#define GSI_MAX_IMMEDIATE_DMA_LEN (8)
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/* cmds to perform by using dmaengine_slave_config() */
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enum msm_gpi_ctrl_cmd {
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MSM_GPI_INIT,
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MSM_GPI_CMD_UART_SW_STALE,
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MSM_GPI_CMD_UART_RFR_READY,
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MSM_GPI_CMD_UART_RFR_NOT_READY,
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};
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enum msm_gpi_cb_event {
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/* These events are hardware generated events */
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MSM_GPI_QUP_NOTIFY,
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MSM_GPI_QUP_ERROR, /* global error */
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MSM_GPI_QUP_CH_ERROR, /* channel specific error */
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MSM_GPI_QUP_FW_ERROR, /* unhandled error */
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/* These events indicate a software bug */
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MSM_GPI_QUP_PENDING_EVENT,
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MSM_GPI_QUP_EOT_DESC_MISMATCH,
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MSM_GPI_QUP_SW_ERROR,
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MSM_GPI_QUP_CR_HEADER,
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MSM_GPI_QUP_MAX_EVENT,
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};
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struct msm_gpi_error_log {
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u32 routine;
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u32 type;
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u32 error_code;
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};
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struct __packed qup_q2spi_cr_header_event {
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u8 cr_hdr[4];
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u8 cr_ed_byte[4];
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u32 reserved0 : 24;
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u8 code : 8;
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u32 byte0_len : 4;
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u32 reserved1 : 3;
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u32 byte0_err : 1;
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u32 reserved2 : 8;
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u8 type : 8;
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u8 ch_id : 8;
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};
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struct msm_gpi_cb {
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enum msm_gpi_cb_event cb_event;
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u64 status;
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u64 timestamp;
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u64 count;
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struct msm_gpi_error_log error_log;
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struct __packed qup_q2spi_cr_header_event q2spi_cr_header_event;
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};
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static const char *const gpi_cb_event_str[MSM_GPI_QUP_MAX_EVENT] = {
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[MSM_GPI_QUP_NOTIFY] = "NOTIFY",
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[MSM_GPI_QUP_ERROR] = "GLOBAL ERROR",
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[MSM_GPI_QUP_CH_ERROR] = "CHAN ERROR",
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[MSM_GPI_QUP_FW_ERROR] = "UNHANDLED ERROR",
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[MSM_GPI_QUP_PENDING_EVENT] = "PENDING EVENT",
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[MSM_GPI_QUP_EOT_DESC_MISMATCH] = "EOT/DESC MISMATCH",
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[MSM_GPI_QUP_SW_ERROR] = "SW ERROR",
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[MSM_GPI_QUP_CR_HEADER] = "Doorbell CR EVENT"
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};
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#define TO_GPI_CB_EVENT_STR(event) (((event) >= MSM_GPI_QUP_MAX_EVENT) ? \
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"INVALID" : gpi_cb_event_str[(event)])
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struct dma_chan;
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struct gpi_client_info {
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/*
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* memory for msm_gpi_cb is released after callback, clients shall
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* save any required data for post processing after returning
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* from callback
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*/
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void (*callback)(struct dma_chan *chan,
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struct msm_gpi_cb const *msm_gpi_cb,
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void *cb_param);
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void *cb_param;
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};
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/*
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* control structure to config gpi dma engine via dmaengine_slave_config()
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* dma_chan.private should point to msm_gpi_ctrl structure
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*/
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struct msm_gpi_ctrl {
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enum msm_gpi_ctrl_cmd cmd;
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union {
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struct gpi_client_info init;
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};
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};
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enum msm_gpi_tce_code {
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MSM_GPI_TCE_SUCCESS = 1,
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MSM_GPI_TCE_EOT = 2,
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MSM_GPI_TCE_EOB = 4,
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MSM_GPI_TCE_UNEXP_ERR = 16,
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};
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/*
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* gpi specific callback parameters to pass between gpi client and gpi engine.
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* client shall set async_desc.callback_parm to msm_gpi_dma_async_tx_cb_param
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*/
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struct msm_gpi_dma_async_tx_cb_param {
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u32 length;
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enum msm_gpi_tce_code completion_code; /* TCE event code */
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u32 status;
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struct __packed msm_gpi_tre imed_tre;
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void *userdata;
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enum GPI_EV_TYPE tce_type;
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u32 q2spi_status:8;
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};
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struct gsi_tre_info {
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struct msm_gpi_tre lock_t;
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struct msm_gpi_tre go_t;
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struct msm_gpi_tre config_t;
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struct msm_gpi_tre dma_t;
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struct msm_gpi_tre unlock_t;
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u8 flags;
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};
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struct gsi_tre_queue {
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u32 msg_cnt;
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u32 unmap_msg_cnt;
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u32 freed_msg_cnt;
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dma_addr_t dma_buf[GSI_MAX_NUM_TRE_MSGS];
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void *virt_buf[GSI_MAX_NUM_TRE_MSGS];
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u32 len[GSI_MAX_NUM_TRE_MSGS];
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|
atomic_t irq_cnt;
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};
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|
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|
struct gsi_xfer_param {
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struct dma_async_tx_descriptor *desc;
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struct msm_gpi_dma_async_tx_cb_param cb;
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struct dma_chan *ch;
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|
struct scatterlist *sg; /* lock, cfg0, go, TX, unlock */
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dma_addr_t sg_dma;
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struct msm_gpi_ctrl ev;
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struct gsi_tre_info tre;
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|
struct gsi_tre_queue tre_queue;
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spinlock_t multi_tre_lock; /* multi tre spin lock */
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void (*cb_fun)(void *ptr); /* tx or rx cb */
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|
};
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|
|
|
struct gsi_common {
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|
u8 protocol;
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|
struct completion *xfer;
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|
struct device *dev;
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|
void *dev_node;
|
|
struct gsi_xfer_param tx;
|
|
struct gsi_xfer_param rx;
|
|
void *ipc;
|
|
bool req_chan;
|
|
bool *err; /* For every gsi error performing gsi reset */
|
|
int *protocol_err; /* protocol specific error*/
|
|
void (*ev_cb_fun)(struct dma_chan *ch, struct msm_gpi_cb const *cb_str, void *ptr);
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|
};
|
|
|
|
/* Client drivers of the GPI can call this function to dump the GPI registers
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* whenever client met some scenario like timeout, error in GPI transfer mode.
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|
*/
|
|
void gpi_dump_for_geni(struct dma_chan *chan);
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|
|
|
/**
|
|
* gpi_q2spi_terminate_all() - function to stop and restart the channels
|
|
* @chan: gsi dma channel handle
|
|
*
|
|
* Return: Returns success or failure
|
|
*/
|
|
int gpi_q2spi_terminate_all(struct dma_chan *chan);
|
|
|
|
/**
|
|
* gpi_update_multi_desc_flag() - update multi descriptor flag and num of msgs for
|
|
* multi descriptor mode handling.
|
|
* @chan: Base address of dma channel
|
|
* @is_multi_descriptor: is multi descriptor flag
|
|
* @num_msgs: number of client messages
|
|
*
|
|
* Return:None
|
|
*/
|
|
void gpi_update_multi_desc_flag(struct dma_chan *chan, bool is_multi_descriptor, int num_msgs);
|
|
|
|
/**
|
|
* gsi_common_tre_process() - Process received TRE's from GSI HW
|
|
* @gsi: Base address of the gsi common structure.
|
|
* @num_xfers: number of messages count.
|
|
* @num_msg_per_irq: num of messages per irq.
|
|
* @wrapper_dev: Pointer to the corresponding QUPv3 wrapper core.
|
|
*
|
|
* This function is used to process received TRE's from GSI HW.
|
|
* And also used for error case, it will clear and unmap all pending transfers.
|
|
*
|
|
* Return: None.
|
|
*/
|
|
void gsi_common_tre_process(struct gsi_common *gsi, u32 num_xfers, u32 num_msg_per_irq,
|
|
struct device *wrapper_dev);
|
|
|
|
/**
|
|
* gsi_common_tx_tre_optimization() - Process received TRE's from GSI HW
|
|
* @gsi: Base address of the gsi common structure.
|
|
* @num_xfers: number of messages count.
|
|
* @num_msg_per_irq: num of messages per irq.
|
|
* @xfer_timeout: xfer timeout value.
|
|
* @wrapper_dev: Pointer to the corresponding QUPv3 wrapper core.
|
|
*
|
|
* This function is used to optimize dma tre's, it keeps always HW busy.
|
|
*
|
|
* Return: Returning timeout value
|
|
*/
|
|
int gsi_common_tx_tre_optimization(struct gsi_common *gsi, u32 num_xfers, u32 num_msg_per_irq,
|
|
u32 xfer_timeout, struct device *wrapper_dev);
|
|
|
|
/**
|
|
* geni_gsi_ch_start() - gsi channel command to start the GSI RX and TX channels
|
|
* @chan: dma channel handle
|
|
*
|
|
* Return: Returns success or failure
|
|
*/
|
|
int geni_gsi_ch_start(struct dma_chan *chan);
|
|
|
|
/**
|
|
* geni_gsi_connect_doorbell() - function to connect gsi doorbell
|
|
* @chan: dma channel handle
|
|
*
|
|
* Return: Returns success or failure
|
|
*/
|
|
int geni_gsi_connect_doorbell(struct dma_chan *chan);
|
|
|
|
/**
|
|
* geni_gsi_disconnect_doorbell_stop_ch() - function to disconnect gsi doorbell and stop channel
|
|
* @chan: dma channel handle
|
|
*
|
|
* Return: Returns success or failure
|
|
*/
|
|
int geni_gsi_disconnect_doorbell_stop_ch(struct dma_chan *chan, bool stop_ch);
|
|
|
|
/**
|
|
* geni_gsi_common_request_channel() - gsi common dma request channel
|
|
* @gsi: Base address of gsi common
|
|
* @stop_ch: stop channel if set to true
|
|
*
|
|
* Return: Returns success or failure
|
|
*/
|
|
int geni_gsi_common_request_channel(struct gsi_common *gsi);
|
|
|
|
/**
|
|
* gsi_common_prep_desc_and_submit() - gsi common prepare descriptor and gsi submit
|
|
* @gsi: Base address of gsi common
|
|
* @segs: Num of segments
|
|
* @tx_chan: dma transfer channel type
|
|
* @skip_callbacks: flag used to register callbacks
|
|
*
|
|
* Return: Returns success or failure
|
|
*/
|
|
int gsi_common_prep_desc_and_submit(struct gsi_common *gsi, int segs, bool tx_chan, bool skip_cb);
|
|
|
|
/**
|
|
* gsi_common_fill_tre_buf() - gsi common fill tre buffers
|
|
* @gsi: Base address of gsi common
|
|
* @tx_chan: dma transfer channel type
|
|
*
|
|
* Return: Returns tre count
|
|
*/
|
|
int gsi_common_fill_tre_buf(struct gsi_common *gsi, bool tx_chan);
|
|
|
|
/**
|
|
* gsi_common_clear_tre_indexes() - gsi common queue clear tre indexes
|
|
* @gsi_q: Base address of gsi common queue
|
|
*
|
|
* Return: None
|
|
*/
|
|
void gsi_common_clear_tre_indexes(struct gsi_tre_queue *gsi_q);
|
|
#endif
|
|
|