6cd94d5e57
Pull ARM SoC platform changes from Arnd Bergmann:
"New and updated SoC support, notable changes include:
- bcm:
brcmstb SMP support
initial iproc/cygnus support
- exynos:
Exynos4415 SoC support
PMU and suspend support for Exynos5420
PMU support for Exynos3250
pm related maintenance
- imx:
new LS1021A SoC support
vybrid 610 global timer support
- integrator:
convert to using multiplatform configuration
- mediatek:
earlyprintk support for mt8127/mt8135
- meson:
meson8 soc and l2 cache controller support
- mvebu:
Armada 38x CPU hotplug support
drop support for prerelease Armada 375 Z1 stepping
extended suspend support, now works on Armada 370/XP
- omap:
hwmod related maintenance
prcm cleanup
- pxa:
initial pxa27x DT handling
- rockchip:
SMP support for rk3288
add cpu frequency scaling support
- shmobile:
r8a7740 power domain support
various small restart, timer, pci apmu changes
- sunxi:
Allwinner A80 (sun9i) earlyprintk support
- ux500:
power domain support
Overall, a significant chunk of changes, coming mostly from the usual
suspects: omap, shmobile, samsung and mvebu, all of which already
contain a lot of platform specific code in arch/arm"
* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (187 commits)
ARM: mvebu: use the cpufreq-dt platform_data for independent clocks
soc: integrator: Add terminating entry for integrator_cm_match
ARM: mvebu: add SDRAM controller description for Armada XP
ARM: mvebu: adjust mbus controller description on Armada 370/XP
ARM: mvebu: add suspend/resume DT information for Armada XP GP
ARM: mvebu: synchronize secondary CPU clocks on resume
ARM: mvebu: make sure MMU is disabled in armada_370_xp_cpu_resume
ARM: mvebu: Armada XP GP specific suspend/resume code
ARM: mvebu: reserve the first 10 KB of each memory bank for suspend/resume
ARM: mvebu: implement suspend/resume support for Armada XP
clk: mvebu: add suspend/resume for gatable clocks
bus: mvebu-mbus: provide a mechanism to save SDRAM window configuration
bus: mvebu-mbus: suspend/resume support
clocksource: time-armada-370-xp: add suspend/resume support
irqchip: armada-370-xp: Add suspend/resume support
ARM: add lolevel debug support for asm9260
ARM: add mach-asm9260
ARM: EXYNOS: use u8 for val[] in struct exynos_pmu_conf
power: reset: imx-snvs-poweroff: add power off driver for i.mx6
ARM: imx: temporarily remove CONFIG_SOC_FSL from LS1021A
...
101 lines
2.7 KiB
C
101 lines
2.7 KiB
C
/*
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* SH-Mobile Timer
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*
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* Copyright (C) 2010 Magnus Damm
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* Copyright (C) 2002 - 2009 Paul Mundt
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/platform_device.h>
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#include <linux/clocksource.h>
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#include <linux/delay.h>
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#include <linux/of_address.h>
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static void __init shmobile_setup_delay_hz(unsigned int max_cpu_core_hz,
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unsigned int mult, unsigned int div)
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{
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/* calculate a worst-case loops-per-jiffy value
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* based on maximum cpu core hz setting and the
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* __delay() implementation in arch/arm/lib/delay.S
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*
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* this will result in a longer delay than expected
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* when the cpu core runs on lower frequencies.
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*/
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unsigned int value = HZ * div / mult;
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if (!preset_lpj)
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preset_lpj = max_cpu_core_hz / value;
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}
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void __init shmobile_init_delay(void)
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{
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struct device_node *np, *cpus;
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bool is_a7_a8_a9 = false;
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bool is_a15 = false;
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bool has_arch_timer = false;
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u32 max_freq = 0;
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cpus = of_find_node_by_path("/cpus");
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if (!cpus)
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return;
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for_each_child_of_node(cpus, np) {
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u32 freq;
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if (!of_property_read_u32(np, "clock-frequency", &freq))
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max_freq = max(max_freq, freq);
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if (of_device_is_compatible(np, "arm,cortex-a8") ||
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of_device_is_compatible(np, "arm,cortex-a9")) {
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is_a7_a8_a9 = true;
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} else if (of_device_is_compatible(np, "arm,cortex-a7")) {
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is_a7_a8_a9 = true;
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has_arch_timer = true;
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} else if (of_device_is_compatible(np, "arm,cortex-a15")) {
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is_a15 = true;
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has_arch_timer = true;
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}
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}
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of_node_put(cpus);
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if (!max_freq)
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return;
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if (!has_arch_timer || !IS_ENABLED(CONFIG_ARM_ARCH_TIMER)) {
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if (is_a7_a8_a9)
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shmobile_setup_delay_hz(max_freq, 1, 3);
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else if (is_a15)
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shmobile_setup_delay_hz(max_freq, 2, 4);
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}
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}
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static void __init shmobile_late_time_init(void)
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{
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/*
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* Make sure all compiled-in early timers register themselves.
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*
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* Run probe() for two "earlytimer" devices, these will be the
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* clockevents and clocksource devices respectively. In the event
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* that only a clockevents device is available, we -ENODEV on the
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* clocksource and the jiffies clocksource is used transparently
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* instead. No error handling is necessary here.
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*/
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early_platform_driver_register_all("earlytimer");
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early_platform_driver_probe("earlytimer", 2, 0);
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}
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void __init shmobile_earlytimer_init(void)
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{
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late_time_init = shmobile_late_time_init;
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}
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