236 lines
8.5 KiB
C
Executable File
236 lines
8.5 KiB
C
Executable File
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SUN_H
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#define __DT_BINDINGS_INTERCONNECT_QCOM_SUN_H
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#define MASTER_GPU_TCU 0
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#define MASTER_SYS_TCU 1
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#define MASTER_APPSS_PROC 2
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#define MASTER_LLCC 3
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#define MASTER_QDSS_BAM 4
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#define MASTER_QSPI_0 5
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#define MASTER_QUP_1 6
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#define MASTER_QUP_2 7
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#define MASTER_A1NOC_SNOC 8
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#define MASTER_A2NOC_SNOC 9
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#define MASTER_CAMNOC_HF 10
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#define MASTER_CAMNOC_NRT_ICP_SF 11
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#define MASTER_CAMNOC_RT_CDM_SF 12
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#define MASTER_CAMNOC_SF 13
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#define MASTER_GEM_NOC_CNOC 14
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#define MASTER_GEM_NOC_PCIE_SNOC 15
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#define MASTER_GFX3D 16
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#define MASTER_LPASS_GEM_NOC 17
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#define MASTER_LPASS_LPINOC 18
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#define MASTER_LPIAON_NOC 19
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#define MASTER_LPASS_PROC 20
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#define MASTER_MDP 21
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#define MASTER_MSS_PROC 22
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#define MASTER_MNOC_HF_MEM_NOC 23
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#define MASTER_MNOC_SF_MEM_NOC 24
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#define MASTER_CDSP_PROC 25
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#define MASTER_COMPUTE_NOC 26
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#define MASTER_ANOC_PCIE_GEM_NOC 27
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#define MASTER_SNOC_SF_MEM_NOC 28
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#define MASTER_UBWC_P 29
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#define MASTER_CDSP_HCP 30
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#define MASTER_VIDEO_CV_PROC 31
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#define MASTER_VIDEO_EVA 32
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#define MASTER_VIDEO_MVP 33
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#define MASTER_VIDEO_V_PROC 34
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#define MASTER_CNOC_CFG 35
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#define MASTER_CNOC_MNOC_CFG 36
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#define MASTER_PCIE_ANOC_CFG 37
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#define MASTER_QUP_CORE_0 38
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#define MASTER_QUP_CORE_1 39
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#define MASTER_QUP_CORE_2 40
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#define MASTER_CRYPTO 41
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#define MASTER_IPA 42
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#define MASTER_QUP_3 43
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#define MASTER_SOCCP_AGGR_NOC 44
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#define MASTER_SP 45
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#define MASTER_GIC 46
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#define MASTER_PCIE_0 47
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#define MASTER_QDSS_ETR 48
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#define MASTER_QDSS_ETR_1 49
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#define MASTER_SDCC_2 50
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#define MASTER_SDCC_4 51
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#define MASTER_UFS_MEM 52
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#define MASTER_USB3_0 53
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#define SLAVE_UBWC_P 512
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#define SLAVE_EBI1 513
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#define SLAVE_AHB2PHY_SOUTH 514
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#define SLAVE_AHB2PHY_NORTH 515
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#define SLAVE_AOSS 516
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#define SLAVE_CAMERA_CFG 517
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#define SLAVE_CLK_CTL 518
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#define SLAVE_CRYPTO_0_CFG 519
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#define SLAVE_DISPLAY_CFG 520
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#define SLAVE_EVA_CFG 521
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#define SLAVE_GFX3D_CFG 522
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#define SLAVE_I2C 523
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#define SLAVE_I3C_IBI0_CFG 524
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#define SLAVE_I3C_IBI1_CFG 525
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#define SLAVE_IMEM_CFG 526
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#define SLAVE_IPA_CFG 527
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#define SLAVE_IPC_ROUTER_CFG 528
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#define SLAVE_CNOC_MSS 529
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#define SLAVE_PCIE_CFG 530
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#define SLAVE_PRNG 531
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#define SLAVE_QDSS_CFG 532
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#define SLAVE_QSPI_0 533
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#define SLAVE_QUP_3 534
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#define SLAVE_QUP_1 535
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#define SLAVE_QUP_2 536
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#define SLAVE_SDCC_2 537
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#define SLAVE_SDCC_4 538
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#define SLAVE_SOCCP 539
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#define SLAVE_SPSS_CFG 540
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#define SLAVE_TCSR 541
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#define SLAVE_TLMM 542
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#define SLAVE_TME_CFG 543
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#define SLAVE_UFS_MEM_CFG 544
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#define SLAVE_USB3_0 545
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#define SLAVE_VENUS_CFG 546
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#define SLAVE_VSENSE_CTRL_CFG 547
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#define SLAVE_A1NOC_SNOC 548
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#define SLAVE_A2NOC_SNOC 549
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#define SLAVE_APPSS 550
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#define SLAVE_GEM_NOC_CNOC 551
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#define SLAVE_SNOC_GEM_NOC_SF 552
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#define SLAVE_LLCC 553
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#define SLAVE_LPASS_GEM_NOC 554
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#define SLAVE_LPIAON_NOC_LPASS_AG_NOC 555
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#define SLAVE_LPICX_NOC_LPIAON_NOC 556
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#define SLAVE_MNOC_HF_MEM_NOC 557
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#define SLAVE_MNOC_SF_MEM_NOC 558
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#define SLAVE_CDSP_MEM_NOC 559
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#define SLAVE_MEM_NOC_PCIE_SNOC 560
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#define SLAVE_ANOC_PCIE_GEM_NOC 561
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#define SLAVE_CNOC_CFG 562
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#define SLAVE_DDRSS_CFG 563
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#define SLAVE_CNOC_MNOC_CFG 564
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#define SLAVE_PCIE_ANOC_CFG 565
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#define SLAVE_QUP_CORE_0 566
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#define SLAVE_QUP_CORE_1 567
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#define SLAVE_QUP_CORE_2 568
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#define SLAVE_BOOT_IMEM 569
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#define SLAVE_IMEM 570
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#define SLAVE_BOOT_IMEM_2 571
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#define SLAVE_SERVICE_CNOC 572
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#define SLAVE_SERVICE_MNOC 573
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#define SLAVE_SERVICE_PCIE_ANOC 574
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#define SLAVE_PCIE_0 575
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#define SLAVE_QDSS_STM 576
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#define SLAVE_TCU 577
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#define MASTER_LLCC_DISP 1000
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#define MASTER_MDP_DISP 1001
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#define MASTER_MNOC_HF_MEM_NOC_DISP 1002
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#define MASTER_ANOC_PCIE_GEM_NOC_DISP 1003
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#define SLAVE_EBI1_DISP 1512
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#define SLAVE_LLCC_DISP 1513
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#define SLAVE_MNOC_HF_MEM_NOC_DISP 1514
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#define MASTER_LLCC_CAM_IFE_0 2000
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#define MASTER_CAMNOC_HF_CAM_IFE_0 2001
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#define MASTER_CAMNOC_NRT_ICP_SF_CAM_IFE_0 2002
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#define MASTER_CAMNOC_RT_CDM_SF_CAM_IFE_0 2003
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#define MASTER_CAMNOC_SF_CAM_IFE_0 2004
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#define MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0 2005
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#define MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0 2006
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#define MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_0 2007
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#define SLAVE_EBI1_CAM_IFE_0 2512
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#define SLAVE_LLCC_CAM_IFE_0 2513
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#define SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0 2514
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#define SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0 2515
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#define MASTER_LLCC_CAM_IFE_1 3000
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#define MASTER_CAMNOC_HF_CAM_IFE_1 3001
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#define MASTER_CAMNOC_NRT_ICP_SF_CAM_IFE_1 3002
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#define MASTER_CAMNOC_RT_CDM_SF_CAM_IFE_1 3003
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#define MASTER_CAMNOC_SF_CAM_IFE_1 3004
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#define MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1 3005
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#define MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1 3006
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#define MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_1 3007
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#define SLAVE_EBI1_CAM_IFE_1 3512
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#define SLAVE_LLCC_CAM_IFE_1 3513
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#define SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1 3514
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#define SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1 3515
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#define MASTER_LLCC_CAM_IFE_2 4000
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#define MASTER_CAMNOC_HF_CAM_IFE_2 4001
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#define MASTER_CAMNOC_NRT_ICP_SF_CAM_IFE_2 4002
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#define MASTER_CAMNOC_RT_CDM_SF_CAM_IFE_2 4003
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#define MASTER_CAMNOC_SF_CAM_IFE_2 4004
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#define MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2 4005
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#define MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2 4006
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#define MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_2 4007
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#define SLAVE_EBI1_CAM_IFE_2 4512
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#define SLAVE_LLCC_CAM_IFE_2 4513
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#define SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2 4514
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#define SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2 4515
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#define MASTER_IPA_CORE_PCIE_CRM_HW_0 5000
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#define MASTER_LLCC_PCIE_CRM_HW_0 5001
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#define MASTER_ANOC_PCIE_GEM_NOC_PCIE_CRM_HW_0 5002
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#define MASTER_PCIE_0_PCIE_CRM_HW_0 5003
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#define SLAVE_EBI1_PCIE_CRM_HW_0 5512
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#define SLAVE_IPA_CORE_PCIE_CRM_HW_0 5513
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#define SLAVE_LLCC_PCIE_CRM_HW_0 5514
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#define SLAVE_ANOC_PCIE_GEM_NOC_PCIE_CRM_HW_0 5515
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#define MASTER_LLCC_DISP_CRM_HW_0 6000
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#define MASTER_MDP_DISP_CRM_HW_0 6001
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#define MASTER_MNOC_HF_MEM_NOC_DISP_CRM_HW_0 6002
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#define MASTER_ANOC_PCIE_GEM_NOC_DISP_CRM_HW_0 6003
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#define SLAVE_EBI1_DISP_CRM_HW_0 6512
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#define SLAVE_LLCC_DISP_CRM_HW_0 6513
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#define SLAVE_MNOC_HF_MEM_NOC_DISP_CRM_HW_0 6514
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#define MASTER_LLCC_DISP_CRM_HW_1 7000
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#define MASTER_MDP_DISP_CRM_HW_1 7001
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#define MASTER_MNOC_HF_MEM_NOC_DISP_CRM_HW_1 7002
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#define MASTER_ANOC_PCIE_GEM_NOC_DISP_CRM_HW_1 7003
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#define SLAVE_EBI1_DISP_CRM_HW_1 7512
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#define SLAVE_LLCC_DISP_CRM_HW_1 7513
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#define SLAVE_MNOC_HF_MEM_NOC_DISP_CRM_HW_1 7514
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#define MASTER_LLCC_DISP_CRM_HW_2 8000
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#define MASTER_MDP_DISP_CRM_HW_2 8001
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#define MASTER_MNOC_HF_MEM_NOC_DISP_CRM_HW_2 8002
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#define MASTER_ANOC_PCIE_GEM_NOC_DISP_CRM_HW_2 8003
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#define SLAVE_EBI1_DISP_CRM_HW_2 8512
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#define SLAVE_LLCC_DISP_CRM_HW_2 8513
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#define SLAVE_MNOC_HF_MEM_NOC_DISP_CRM_HW_2 8514
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#define MASTER_LLCC_DISP_CRM_HW_3 9000
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#define MASTER_MDP_DISP_CRM_HW_3 9001
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#define MASTER_MNOC_HF_MEM_NOC_DISP_CRM_HW_3 9002
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#define MASTER_ANOC_PCIE_GEM_NOC_DISP_CRM_HW_3 9003
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#define SLAVE_EBI1_DISP_CRM_HW_3 9512
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#define SLAVE_LLCC_DISP_CRM_HW_3 9513
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#define SLAVE_MNOC_HF_MEM_NOC_DISP_CRM_HW_3 9514
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#define MASTER_LLCC_DISP_CRM_HW_4 10000
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#define MASTER_MDP_DISP_CRM_HW_4 10001
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#define MASTER_MNOC_HF_MEM_NOC_DISP_CRM_HW_4 10002
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#define MASTER_ANOC_PCIE_GEM_NOC_DISP_CRM_HW_4 10003
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#define SLAVE_EBI1_DISP_CRM_HW_4 10512
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#define SLAVE_LLCC_DISP_CRM_HW_4 10513
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#define SLAVE_MNOC_HF_MEM_NOC_DISP_CRM_HW_4 10514
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#define MASTER_LLCC_DISP_CRM_HW_5 11000
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#define MASTER_MDP_DISP_CRM_HW_5 11001
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#define MASTER_MNOC_HF_MEM_NOC_DISP_CRM_HW_5 11002
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#define MASTER_ANOC_PCIE_GEM_NOC_DISP_CRM_HW_5 11003
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#define SLAVE_EBI1_DISP_CRM_HW_5 11512
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#define SLAVE_LLCC_DISP_CRM_HW_5 11513
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#define SLAVE_MNOC_HF_MEM_NOC_DISP_CRM_HW_5 11514
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#define MASTER_LLCC_DISP_CRM_SW_0 12000
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#define MASTER_MDP_DISP_CRM_SW_0 12001
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#define MASTER_MNOC_HF_MEM_NOC_DISP_CRM_SW_0 12002
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#define MASTER_ANOC_PCIE_GEM_NOC_DISP_CRM_SW_0 12003
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#define SLAVE_EBI1_DISP_CRM_SW_0 12512
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#define SLAVE_LLCC_DISP_CRM_SW_0 12513
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#define SLAVE_MNOC_HF_MEM_NOC_DISP_CRM_SW_0 12514
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#define MASTER_UBWC MASTER_UBWC_P
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#define MASTER_PCIE_3 MASTER_PCIE_0
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#define SLAVE_UBWC SLAVE_UBWC_P
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#define MASTER_PCIE_3_PCIE_CRM_HW_0 MASTER_PCIE_0_PCIE_CRM_HW_0
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#endif
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