49 lines
2.1 KiB
C
Executable File
49 lines
2.1 KiB
C
Executable File
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H
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#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H
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#ifndef PM8550_SID
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#define PM8550_SID 1
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#endif
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/* ADC channels for PM8550_ADC for PMIC5 Gen3 */
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#define PM8550_ADC5_GEN3_OFFSET_REF (PM8550_SID << 8 | 0x00)
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#define PM8550_ADC5_GEN3_1P25VREF (PM8550_SID << 8 | 0x01)
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#define PM8550_ADC5_GEN3_VREF_VADC (PM8550_SID << 8 | 0x02)
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#define PM8550_ADC5_GEN3_DIE_TEMP (PM8550_SID << 8 | 0x03)
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#define PM8550_ADC5_GEN3_AMUX_THM1 (PM8550_SID << 8 | 0x04)
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#define PM8550_ADC5_GEN3_AMUX_THM2 (PM8550_SID << 8 | 0x05)
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#define PM8550_ADC5_GEN3_AMUX_THM3 (PM8550_SID << 8 | 0x06)
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#define PM8550_ADC5_GEN3_AMUX_THM4 (PM8550_SID << 8 | 0x07)
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#define PM8550_ADC5_GEN3_AMUX_THM5 (PM8550_SID << 8 | 0x08)
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#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2 (PM8550_SID << 8 | 0x09)
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#define PM8550_ADC5_GEN3_AMUX1_GPIO3 (PM8550_SID << 8 | 0x0a)
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#define PM8550_ADC5_GEN3_AMUX2_GPIO4 (PM8550_SID << 8 | 0x0b)
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#define PM8550_ADC5_GEN3_AMUX3_GPIO7 (PM8550_SID << 8 | 0x0c)
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#define PM8550_ADC5_GEN3_AMUX4_GPIO12 (PM8550_SID << 8 | 0x0d)
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/* 100k pull-up */
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#define PM8550_ADC5_GEN3_AMUX_THM1_100K_PU (PM8550_SID << 8 | 0x44)
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#define PM8550_ADC5_GEN3_AMUX_THM2_100K_PU (PM8550_SID << 8 | 0x45)
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#define PM8550_ADC5_GEN3_AMUX_THM3_100K_PU (PM8550_SID << 8 | 0x46)
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#define PM8550_ADC5_GEN3_AMUX_THM4_100K_PU (PM8550_SID << 8 | 0x47)
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#define PM8550_ADC5_GEN3_AMUX_THM5_100K_PU (PM8550_SID << 8 | 0x48)
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#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2_100K_PU (PM8550_SID << 8 | 0x49)
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#define PM8550_ADC5_GEN3_AMUX1_GPIO3_100K_PU (PM8550_SID << 8 | 0x4a)
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#define PM8550_ADC5_GEN3_AMUX2_GPIO4_100K_PU (PM8550_SID << 8 | 0x4b)
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#define PM8550_ADC5_GEN3_AMUX3_GPIO7_100K_PU (PM8550_SID << 8 | 0x4c)
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#define PM8550_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8550_SID << 8 | 0x4d)
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/* 1/3 Divider */
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#define PM8550_ADC5_GEN3_AMUX3_GPIO7_DIV3 (PM8550_SID << 8 | 0x8c)
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#define PM8550_ADC5_GEN3_AMUX4_GPIO12_DIV3 (PM8550_SID << 8 | 0x8d)
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#define PM8550_ADC5_GEN3_VPH_PWR (PM8550_SID << 8 | 0x8e)
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#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H */
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