770 lines
21 KiB
C
Executable File
770 lines
21 KiB
C
Executable File
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. */
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/* Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */
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#include <linux/err.h>
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#include <linux/ipc_logging.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/nvmem-consumer.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/string.h>
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/* SDAM NVMEM register offsets: */
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#define REG_SDAM_COUNT 0x45
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#define REG_PUSH_PTR 0x46
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#define REG_PUSH_SDAM_NUM 0x47
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#define REG_FIFO_DATA_START 0x4B
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#define REG_FIFO_DATA_END 0xBF
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/* PMIC PON LOG binary format in the FIFO: */
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struct pmic_pon_log_entry {
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u8 state;
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u8 event;
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u8 data1;
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u8 data0;
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};
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#define FIFO_SIZE (REG_FIFO_DATA_END - REG_FIFO_DATA_START + 1)
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#define FIFO_ENTRY_SIZE (sizeof(struct pmic_pon_log_entry))
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#define IPC_LOG_PAGES 3
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struct pmic_pon_log_dev {
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struct device *dev;
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struct pmic_pon_log_entry *log;
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int log_len;
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int log_max_entries;
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void *ipc_log;
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struct nvmem_device **nvmem;
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int nvmem_count;
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int sdam_fifo_count;
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};
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enum pmic_pon_state {
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PMIC_PON_STATE_FAULT0 = 0x0,
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PMIC_PON_STATE_PON = 0x1,
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PMIC_PON_STATE_POFF = 0x2,
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PMIC_PON_STATE_ON = 0x3,
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PMIC_PON_STATE_RESET = 0x4,
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PMIC_PON_STATE_OFF = 0x5,
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PMIC_PON_STATE_FAULT6 = 0x6,
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PMIC_PON_STATE_WARM_RESET = 0x7,
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};
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static const char * const pmic_pon_state_label[] = {
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[PMIC_PON_STATE_FAULT0] = "FAULT",
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[PMIC_PON_STATE_PON] = "PON",
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[PMIC_PON_STATE_POFF] = "POFF",
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[PMIC_PON_STATE_ON] = "ON",
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[PMIC_PON_STATE_RESET] = "RESET",
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[PMIC_PON_STATE_OFF] = "OFF",
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[PMIC_PON_STATE_FAULT6] = "FAULT",
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[PMIC_PON_STATE_WARM_RESET] = "WARM_RESET",
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};
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enum pmic_pon_event {
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PMIC_PON_EVENT_PON_TRIGGER_RECEIVED = 0x01,
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PMIC_PON_EVENT_OTP_COPY_COMPLETE = 0x02,
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PMIC_PON_EVENT_TRIM_COMPLETE = 0x03,
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PMIC_PON_EVENT_XVLO_CHECK_COMPLETE = 0x04,
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PMIC_PON_EVENT_PMIC_CHECK_COMPLETE = 0x05,
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PMIC_PON_EVENT_RESET_TRIGGER_RECEIVED = 0x06,
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PMIC_PON_EVENT_RESET_TYPE = 0x07,
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PMIC_PON_EVENT_WARM_RESET_COUNT = 0x08,
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PMIC_PON_EVENT_FAULT_REASON_1_2 = 0x09,
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PMIC_PON_EVENT_FAULT_REASON_3 = 0x0A,
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PMIC_PON_EVENT_PBS_PC_DURING_FAULT = 0x0B,
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PMIC_PON_EVENT_FUNDAMENTAL_RESET = 0x0C,
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PMIC_PON_EVENT_PON_SEQ_START = 0x0D,
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PMIC_PON_EVENT_PON_SUCCESS = 0x0E,
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PMIC_PON_EVENT_WAITING_ON_PSHOLD = 0x0F,
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PMIC_PON_EVENT_PMIC_SID1_FAULT = 0x10,
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PMIC_PON_EVENT_PMIC_SID2_FAULT = 0x11,
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PMIC_PON_EVENT_PMIC_SID3_FAULT = 0x12,
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PMIC_PON_EVENT_PMIC_SID4_FAULT = 0x13,
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PMIC_PON_EVENT_PMIC_SID5_FAULT = 0x14,
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PMIC_PON_EVENT_PMIC_SID6_FAULT = 0x15,
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PMIC_PON_EVENT_PMIC_SID7_FAULT = 0x16,
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PMIC_PON_EVENT_PMIC_SID8_FAULT = 0x17,
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PMIC_PON_EVENT_PMIC_SID9_FAULT = 0x18,
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PMIC_PON_EVENT_PMIC_SID10_FAULT = 0x19,
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PMIC_PON_EVENT_PMIC_SID11_FAULT = 0x1A,
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PMIC_PON_EVENT_PMIC_SID12_FAULT = 0x1B,
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PMIC_PON_EVENT_PMIC_SID13_FAULT = 0x1C,
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PMIC_PON_EVENT_PMIC_VREG_READY_CHECK = 0x20,
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};
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enum pmic_pon_reset_type {
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PMIC_PON_RESET_TYPE_WARM_RESET = 0x1,
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PMIC_PON_RESET_TYPE_SHUTDOWN = 0x4,
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PMIC_PON_RESET_TYPE_HARD_RESET = 0x7,
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};
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static const char * const pmic_pon_reset_type_label[] = {
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[PMIC_PON_RESET_TYPE_WARM_RESET] = "WARM_RESET",
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[PMIC_PON_RESET_TYPE_SHUTDOWN] = "SHUTDOWN",
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[PMIC_PON_RESET_TYPE_HARD_RESET] = "HARD_RESET",
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};
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static const char * const pmic_pon_fault_reason1[8] = {
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[0] = "GP_FAULT0",
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[1] = "GP_FAULT1",
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[2] = "GP_FAULT2",
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[3] = "GP_FAULT3",
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[4] = "MBG_FAULT",
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[5] = "OVLO",
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[6] = "UVLO",
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[7] = "AVDD_RB",
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};
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static const char * const pmic_pon_fault_reason2[8] = {
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[0] = "UNKNOWN(0)",
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[1] = "UNKNOWN(1)",
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[2] = "PMIC_RB",
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[3] = "FAULT_N",
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[4] = "FAULT_WATCHDOG",
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[5] = "PBS_NACK",
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[6] = "RESTART_PON",
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[7] = "OVERTEMP_STAGE3",
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};
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static const char * const pmic_pon_fault_reason3[8] = {
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[0] = "GP_FAULT4",
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[1] = "GP_FAULT5",
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[2] = "GP_FAULT6",
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[3] = "GP_FAULT7",
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[4] = "GP_FAULT8",
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[5] = "GP_FAULT9",
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[6] = "GP_FAULT10",
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[7] = "GP_FAULT11",
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};
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static const char * const pmic_pon_s3_reset_reason[8] = {
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[0] = "UNKNOWN(0)",
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[1] = "UNKNOWN(1)",
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[2] = "UNKNOWN(2)",
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[3] = "UNKNOWN(3)",
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[4] = "FAULT_N",
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[5] = "FAULT_WATCHDOG",
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[6] = "PBS_NACK",
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[7] = "KPDPWR_AND/OR_RESIN",
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};
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static const char * const pmic_pon_pon_pbl_status[8] = {
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[0] = "UNKNOWN(0)",
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[1] = "UNKNOWN(1)",
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[2] = "UNKNOWN(2)",
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[3] = "UNKNOWN(3)",
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[4] = "UNKNOWN(4)",
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[5] = "UNKNOWN(5)",
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[6] = "XVDD",
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[7] = "DVDD",
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};
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struct pmic_pon_trigger_mapping {
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u16 code;
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const char *label;
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};
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static const struct pmic_pon_trigger_mapping pmic_pon_pon_trigger_map[] = {
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{0x0084, "PS_HOLD"},
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{0x0085, "HARD_RESET"},
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{0x0086, "RESIN_N"},
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{0x0087, "KPDPWR_N"},
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/* PM5100 USB PON trigger */
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{0x0202, "USB_CHARGER"},
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{0x0621, "RTC_ALARM"},
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{0x0640, "SMPL"},
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/* PMX75 USB PON trigger */
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{0x18A0, "USB_CHARGER"},
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{0x18C0, "PMIC_SID1_GPIO5"},
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/* PMI632 USB PON trigger */
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{0x2763, "USB_CHARGER"},
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/* PM8350B USB PON trigger */
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{0x31C2, "USB_CHARGER"},
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/* PM8550B USB PON trigger */
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/* PM7550BA USB PON trigger */
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{0x71C2, "USB_CHARGER"},
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/* PM7250B USB PON trigger */
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{0x8732, "USB_CHARGER"},
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};
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static const struct pmic_pon_trigger_mapping pmic_pon_reset_trigger_map[] = {
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{0x0080, "KPDPWR_N_S2"},
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{0x0081, "RESIN_N_S2"},
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{0x0082, "KPDPWR_N_AND_RESIN_N_S2"},
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{0x0083, "PMIC_WATCHDOG_S2"},
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{0x0084, "PS_HOLD"},
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{0x0085, "SW_RESET"},
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{0x0086, "RESIN_N_DEBOUNCE"},
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{0x0087, "KPDPWR_N_DEBOUNCE"},
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{0x21E3, "PMIC_SID2_BCL_ALARM"},
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{0x31F5, "PMIC_SID3_BCL_ALARM"},
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{0x11D0, "PMIC_SID1_OCP"},
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{0x21D0, "PMIC_SID2_OCP"},
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{0x41D0, "PMIC_SID4_OCP"},
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{0x51D0, "PMIC_SID5_OCP"},
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};
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static const enum pmic_pon_event pmic_pon_important_events[] = {
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PMIC_PON_EVENT_PON_TRIGGER_RECEIVED,
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PMIC_PON_EVENT_RESET_TRIGGER_RECEIVED,
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PMIC_PON_EVENT_RESET_TYPE,
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PMIC_PON_EVENT_FAULT_REASON_1_2,
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PMIC_PON_EVENT_FAULT_REASON_3,
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PMIC_PON_EVENT_FUNDAMENTAL_RESET,
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PMIC_PON_EVENT_PMIC_SID1_FAULT,
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PMIC_PON_EVENT_PMIC_SID2_FAULT,
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PMIC_PON_EVENT_PMIC_SID3_FAULT,
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PMIC_PON_EVENT_PMIC_SID4_FAULT,
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PMIC_PON_EVENT_PMIC_SID5_FAULT,
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PMIC_PON_EVENT_PMIC_SID6_FAULT,
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PMIC_PON_EVENT_PMIC_SID7_FAULT,
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PMIC_PON_EVENT_PMIC_SID8_FAULT,
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PMIC_PON_EVENT_PMIC_SID9_FAULT,
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PMIC_PON_EVENT_PMIC_SID10_FAULT,
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PMIC_PON_EVENT_PMIC_SID11_FAULT,
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PMIC_PON_EVENT_PMIC_SID12_FAULT,
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PMIC_PON_EVENT_PMIC_SID13_FAULT,
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PMIC_PON_EVENT_PMIC_VREG_READY_CHECK,
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};
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static bool pmic_pon_entry_is_important(const struct pmic_pon_log_entry *entry)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(pmic_pon_important_events); i++)
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if (entry->event == pmic_pon_important_events[i])
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return true;
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return false;
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}
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static int pmic_pon_log_read_entry(struct pmic_pon_log_dev *pon_dev,
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u32 entry_start_index, struct pmic_pon_log_entry *entry)
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{
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u8 *buf = (u8 *)entry;
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int ret, len, fifo_total_size, entry_start_sdam, entry_start_addr, i;
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fifo_total_size = FIFO_SIZE * pon_dev->sdam_fifo_count;
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entry_start_index = entry_start_index % fifo_total_size;
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entry_start_sdam = entry_start_index / FIFO_SIZE;
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entry_start_addr = (entry_start_index % FIFO_SIZE)
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+ REG_FIFO_DATA_START;
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if (entry_start_addr + FIFO_ENTRY_SIZE - 1 > REG_FIFO_DATA_END) {
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/* The entry continues beyond the end of this SDAM */
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len = FIFO_SIZE - (entry_start_index % FIFO_SIZE);
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ret = nvmem_device_read(pon_dev->nvmem[entry_start_sdam],
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entry_start_addr, len, buf);
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if (ret < 0)
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return ret;
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i = (entry_start_sdam + 1) % pon_dev->sdam_fifo_count;
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ret = nvmem_device_read(pon_dev->nvmem[i], REG_FIFO_DATA_START,
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FIFO_ENTRY_SIZE - len, &buf[len]);
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} else {
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ret = nvmem_device_read(pon_dev->nvmem[entry_start_sdam],
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entry_start_addr, FIFO_ENTRY_SIZE, buf);
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}
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return ret;
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}
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static int pmic_pon_log_print_reason(char *buf, int buf_size, u8 data,
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const char * const *reason)
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{
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int pos = 0;
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int i;
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bool first;
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if (data == 0) {
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pos += scnprintf(buf + pos, buf_size - pos, "None");
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} else {
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first = true;
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for (i = 0; i < 8; i++) {
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if (data & BIT(i)) {
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pos += scnprintf(buf + pos, buf_size - pos,
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"%s%s",
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(first ? "" : ", "), reason[i]);
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first = false;
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}
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}
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}
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return pos;
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}
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#define BUF_SIZE 128
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static int pmic_pon_log_parse_entry(const struct pmic_pon_log_entry *entry,
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void *ipc_log)
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{
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char buf[BUF_SIZE];
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const char *label = NULL;
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bool is_important;
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int pos = 0;
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int i;
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u16 data;
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data = (entry->data1 << 8) | entry->data0;
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buf[0] = '\0';
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is_important = pmic_pon_entry_is_important(entry);
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switch (entry->event) {
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case PMIC_PON_EVENT_PON_TRIGGER_RECEIVED:
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for (i = 0; i < ARRAY_SIZE(pmic_pon_pon_trigger_map); i++) {
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if (pmic_pon_pon_trigger_map[i].code == data) {
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label = pmic_pon_pon_trigger_map[i].label;
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break;
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}
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}
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pos += scnprintf(buf + pos, BUF_SIZE - pos,
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"PON Trigger: ");
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if (label) {
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pos += scnprintf(buf + pos, BUF_SIZE - pos, "%s",
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label);
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} else {
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pos += scnprintf(buf + pos, BUF_SIZE - pos,
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"SID=0x%X, PID=0x%02X, IRQ=0x%X",
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entry->data1 >> 4, (data >> 4) & 0xFF,
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entry->data0 & 0x7);
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}
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break;
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case PMIC_PON_EVENT_OTP_COPY_COMPLETE:
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scnprintf(buf, BUF_SIZE,
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"OTP Copy Complete: last addr written=0x%04X",
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data);
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break;
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case PMIC_PON_EVENT_TRIM_COMPLETE:
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scnprintf(buf, BUF_SIZE, "Trim Complete: %u bytes written",
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data);
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break;
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case PMIC_PON_EVENT_XVLO_CHECK_COMPLETE:
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scnprintf(buf, BUF_SIZE, "XVLO Check Complete");
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break;
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case PMIC_PON_EVENT_PMIC_CHECK_COMPLETE:
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scnprintf(buf, BUF_SIZE, "PMICs Detected: SID Mask=0x%04X",
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data);
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break;
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case PMIC_PON_EVENT_RESET_TRIGGER_RECEIVED:
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for (i = 0; i < ARRAY_SIZE(pmic_pon_reset_trigger_map); i++) {
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if (pmic_pon_reset_trigger_map[i].code == data) {
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label = pmic_pon_reset_trigger_map[i].label;
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break;
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}
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}
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pos += scnprintf(buf + pos, BUF_SIZE - pos,
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"Reset Trigger: ");
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if (label) {
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pos += scnprintf(buf + pos, BUF_SIZE - pos, "%s",
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label);
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} else {
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pos += scnprintf(buf + pos, BUF_SIZE - pos,
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"SID=0x%X, PID=0x%02X, IRQ=0x%X",
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entry->data1 >> 4, (data >> 4) & 0xFF,
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entry->data0 & 0x7);
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}
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break;
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case PMIC_PON_EVENT_RESET_TYPE:
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if (entry->data0 < ARRAY_SIZE(pmic_pon_reset_type_label) &&
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pmic_pon_reset_type_label[entry->data0])
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scnprintf(buf, BUF_SIZE, "Reset Type: %s",
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pmic_pon_reset_type_label[entry->data0]);
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else
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scnprintf(buf, BUF_SIZE, "Reset Type: UNKNOWN (%u)",
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entry->data0);
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break;
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case PMIC_PON_EVENT_WARM_RESET_COUNT:
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scnprintf(buf, BUF_SIZE, "Warm Reset Count: %u", data);
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break;
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case PMIC_PON_EVENT_FAULT_REASON_1_2:
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if (!entry->data0 && !entry->data1)
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is_important = false;
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if (entry->data0 || !is_important) {
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pos += scnprintf(buf + pos, BUF_SIZE - pos,
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"FAULT_REASON1=");
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pos += pmic_pon_log_print_reason(buf + pos,
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BUF_SIZE - pos, entry->data0,
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pmic_pon_fault_reason1);
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}
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if (entry->data1 || !is_important) {
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pos += scnprintf(buf + pos, BUF_SIZE - pos,
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"%sFAULT_REASON2=",
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(entry->data0 || !is_important)
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? "; " : "");
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pos += pmic_pon_log_print_reason(buf + pos,
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BUF_SIZE - pos, entry->data1,
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pmic_pon_fault_reason2);
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}
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break;
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case PMIC_PON_EVENT_FAULT_REASON_3:
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if (!entry->data0)
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is_important = false;
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pos += scnprintf(buf + pos, BUF_SIZE - pos, "FAULT_REASON3=");
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pos += pmic_pon_log_print_reason(buf + pos, BUF_SIZE - pos,
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entry->data0, pmic_pon_fault_reason3);
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break;
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case PMIC_PON_EVENT_PBS_PC_DURING_FAULT:
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scnprintf(buf, BUF_SIZE, "PBS PC at Fault: 0x%04X", data);
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break;
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case PMIC_PON_EVENT_FUNDAMENTAL_RESET:
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if (!entry->data0 && !entry->data1)
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is_important = false;
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pos += scnprintf(buf + pos, BUF_SIZE - pos,
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"Fundamental Reset: ");
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if (entry->data1 || !is_important) {
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pos += scnprintf(buf + pos, BUF_SIZE - pos,
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"PON_PBL_STATUS=");
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pos += pmic_pon_log_print_reason(buf + pos,
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BUF_SIZE - pos, entry->data1,
|
|
pmic_pon_pon_pbl_status);
|
|
}
|
|
if (entry->data0 || !is_important) {
|
|
pos += scnprintf(buf + pos, BUF_SIZE - pos,
|
|
"%sS3_RESET_REASON=",
|
|
(entry->data1 || !is_important)
|
|
? "; " : "");
|
|
pos += pmic_pon_log_print_reason(buf + pos,
|
|
BUF_SIZE - pos, entry->data0,
|
|
pmic_pon_s3_reset_reason);
|
|
}
|
|
|
|
break;
|
|
case PMIC_PON_EVENT_PON_SEQ_START:
|
|
scnprintf(buf, BUF_SIZE, "Begin PON Sequence");
|
|
break;
|
|
case PMIC_PON_EVENT_PON_SUCCESS:
|
|
scnprintf(buf, BUF_SIZE, "PON Successful");
|
|
break;
|
|
case PMIC_PON_EVENT_WAITING_ON_PSHOLD:
|
|
scnprintf(buf, BUF_SIZE, "Waiting on PS_HOLD");
|
|
break;
|
|
case PMIC_PON_EVENT_PMIC_SID1_FAULT ... PMIC_PON_EVENT_PMIC_SID13_FAULT:
|
|
if (!entry->data0 && !entry->data1)
|
|
is_important = false;
|
|
pos += scnprintf(buf + pos, BUF_SIZE - pos, "PMIC SID%u ",
|
|
entry->event - PMIC_PON_EVENT_PMIC_SID1_FAULT + 1);
|
|
if (entry->data0 || !is_important) {
|
|
pos += scnprintf(buf + pos, BUF_SIZE - pos,
|
|
"FAULT_REASON1=");
|
|
pos += pmic_pon_log_print_reason(buf + pos,
|
|
BUF_SIZE - pos, entry->data0,
|
|
pmic_pon_fault_reason1);
|
|
}
|
|
if (entry->data1 || !is_important) {
|
|
pos += scnprintf(buf + pos, BUF_SIZE - pos,
|
|
"%sFAULT_REASON2=",
|
|
(entry->data0 || !is_important)
|
|
? "; " : "");
|
|
pos += pmic_pon_log_print_reason(buf + pos,
|
|
BUF_SIZE - pos, entry->data1,
|
|
pmic_pon_fault_reason2);
|
|
}
|
|
break;
|
|
case PMIC_PON_EVENT_PMIC_VREG_READY_CHECK:
|
|
if (!data)
|
|
is_important = false;
|
|
scnprintf(buf, BUF_SIZE, "VREG Check: %sVREG_FAULT detected",
|
|
data ? "" : "No ");
|
|
break;
|
|
default:
|
|
scnprintf(buf, BUF_SIZE, "Unknown Event (0x%02X): data=0x%04X",
|
|
entry->event, data);
|
|
break;
|
|
}
|
|
|
|
if (is_important)
|
|
pr_info("PMIC PON log: %s\n", buf);
|
|
else
|
|
pr_debug("PMIC PON log: %s\n", buf);
|
|
|
|
if (entry->state < ARRAY_SIZE(pmic_pon_state_label))
|
|
ipc_log_string(ipc_log, "State=%s; %s\n",
|
|
pmic_pon_state_label[entry->state], buf);
|
|
else
|
|
ipc_log_string(ipc_log, "State=Unknown (0x%02X); %s\n",
|
|
entry->state, buf);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int pmic_pon_log_parse(struct pmic_pon_log_dev *pon_dev)
|
|
{
|
|
int ret, i, addr_end, sdam_end, fifo_index_start, fifo_index_end, index;
|
|
struct pmic_pon_log_entry entry;
|
|
u8 buf;
|
|
|
|
ret = nvmem_device_read(pon_dev->nvmem[0], REG_PUSH_PTR, 1, &buf);
|
|
if (ret < 0)
|
|
return ret;
|
|
addr_end = buf;
|
|
|
|
if (addr_end < REG_FIFO_DATA_START || addr_end > REG_FIFO_DATA_END) {
|
|
dev_err(pon_dev->dev, "unexpected PON log end address: %02X\n",
|
|
addr_end);
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = nvmem_device_read(pon_dev->nvmem[0], REG_PUSH_SDAM_NUM, 1, &buf);
|
|
if (ret < 0)
|
|
return ret;
|
|
sdam_end = buf;
|
|
|
|
if (sdam_end >= pon_dev->sdam_fifo_count) {
|
|
dev_err(pon_dev->dev, "unexpected PON log end SDAM index: %d\n",
|
|
sdam_end);
|
|
return -EINVAL;
|
|
}
|
|
|
|
fifo_index_end = sdam_end * FIFO_SIZE + addr_end - REG_FIFO_DATA_START;
|
|
|
|
/*
|
|
* Calculate the FIFO start index from the end index assuming that the
|
|
* FIFO is full.
|
|
*/
|
|
fifo_index_start = fifo_index_end
|
|
- pon_dev->log_max_entries * FIFO_ENTRY_SIZE;
|
|
if (fifo_index_start < 0)
|
|
fifo_index_start += FIFO_SIZE * pon_dev->sdam_fifo_count;
|
|
|
|
for (i = 0; i < pon_dev->log_max_entries; i++) {
|
|
index = fifo_index_start + i * FIFO_ENTRY_SIZE;
|
|
|
|
ret = pmic_pon_log_read_entry(pon_dev, index, &entry);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
if (entry.state == 0 && entry.event == 0 && entry.data1 == 0 &&
|
|
entry.data0 == 0) {
|
|
/*
|
|
* Ignore all 0 entries which correspond to unused
|
|
* FIFO space in the case that the FIFO has not wrapped
|
|
* around.
|
|
*/
|
|
continue;
|
|
}
|
|
|
|
ret = pmic_pon_log_parse_entry(&entry, pon_dev->ipc_log);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
pon_dev->log[pon_dev->log_len++] = entry;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#define FAULT_REASON2_FAULT_N_MASK BIT(3)
|
|
#define FAULT_REASON2_RESTART_PON_MASK BIT(6)
|
|
|
|
static bool smpl_panic;
|
|
static bool pon_smpl_flag;
|
|
module_param(smpl_panic, bool, 0444);
|
|
/* Trigger a kernel panic if the last power off was caused by a PMIC fault. */
|
|
static void pmic_pon_log_fault_panic(struct pmic_pon_log_dev *pon_dev)
|
|
{
|
|
int last_pon_success = pon_dev->log_len - 1;
|
|
int prev_pon_success = 0;
|
|
int warm_reset_skip_count = 0;
|
|
bool pon_success_found = false;
|
|
char buf[BUF_SIZE];
|
|
u8 mask;
|
|
int i;
|
|
u16 data;
|
|
|
|
mask = (u8)~(FAULT_REASON2_RESTART_PON_MASK |
|
|
FAULT_REASON2_FAULT_N_MASK);
|
|
/*
|
|
* Iterate over log events from newest to oldest. Find the most recent
|
|
* and second most recent PON success events. Ignore PON success events
|
|
* associated with a Warm Reset.
|
|
*/
|
|
for (i = pon_dev->log_len - 1; i >= 0; i--) {
|
|
if (pon_dev->log[i].event == PMIC_PON_EVENT_PON_SUCCESS) {
|
|
if (!pon_success_found) {
|
|
last_pon_success = i;
|
|
pon_success_found = true;
|
|
} else if (warm_reset_skip_count > 0) {
|
|
warm_reset_skip_count--;
|
|
} else {
|
|
prev_pon_success = i;
|
|
break;
|
|
}
|
|
} else if (pon_dev->log[i].event ==
|
|
PMIC_PON_EVENT_WARM_RESET_COUNT) {
|
|
warm_reset_skip_count = (pon_dev->log[i].data1 << 8) |
|
|
pon_dev->log[i].data0;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Check if a fault event occurred between the previous and last PON
|
|
* success events. Trigger a kernel panic if so.
|
|
*/
|
|
for (i = prev_pon_success; i <= last_pon_success; i++) {
|
|
switch (pon_dev->log[i].event) {
|
|
/* TEMP: trigger panic on {0x0640, SMPL} for test purpose. Remove after test */
|
|
case PMIC_PON_EVENT_PON_TRIGGER_RECEIVED:
|
|
data = (pon_dev->log[i].data1 << 8) | pon_dev->log[i].data0;
|
|
if (data == 0x0640)
|
|
pon_smpl_flag = true;
|
|
break;
|
|
case PMIC_PON_EVENT_FAULT_REASON_1_2:
|
|
if (pon_dev->log[i].data0) {
|
|
pmic_pon_log_print_reason(buf, BUF_SIZE,
|
|
pon_dev->log[i].data0,
|
|
pmic_pon_fault_reason1);
|
|
panic("PMIC SID0 FAULT; FAULT_REASON1=%s", buf);
|
|
} else if (pon_dev->log[i].data1 & mask) {
|
|
pmic_pon_log_print_reason(buf, BUF_SIZE,
|
|
pon_dev->log[i].data1,
|
|
pmic_pon_fault_reason2);
|
|
panic("PMIC SID0 FAULT; FAULT_REASON2=%s", buf);
|
|
}
|
|
break;
|
|
case PMIC_PON_EVENT_FAULT_REASON_3:
|
|
if (pon_dev->log[i].data0) {
|
|
pmic_pon_log_print_reason(buf, BUF_SIZE,
|
|
pon_dev->log[i].data0,
|
|
pmic_pon_fault_reason3);
|
|
panic("PMIC SID0 FAULT; FAULT_REASON3=%s", buf);
|
|
}
|
|
break;
|
|
case PMIC_PON_EVENT_PMIC_SID1_FAULT ... PMIC_PON_EVENT_PMIC_SID13_FAULT:
|
|
if (pon_dev->log[i].data0) {
|
|
pmic_pon_log_print_reason(buf, BUF_SIZE,
|
|
pon_dev->log[i].data0,
|
|
pmic_pon_fault_reason1);
|
|
panic("PMIC SID%u FAULT; FAULT_REASON1=%s",
|
|
pon_dev->log[i].event -
|
|
PMIC_PON_EVENT_PMIC_SID1_FAULT + 1,
|
|
buf);
|
|
} else if (pon_dev->log[i].data1 & mask) {
|
|
pmic_pon_log_print_reason(buf, BUF_SIZE,
|
|
pon_dev->log[i].data1,
|
|
pmic_pon_fault_reason2);
|
|
panic("PMIC SID%u FAULT; FAULT_REASON2=%s",
|
|
pon_dev->log[i].event -
|
|
PMIC_PON_EVENT_PMIC_SID1_FAULT + 1,
|
|
buf);
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
static int pmic_pon_log_probe(struct platform_device *pdev)
|
|
{
|
|
struct pmic_pon_log_dev *pon_dev;
|
|
char buf[12] = "";
|
|
int ret, i;
|
|
u8 reg = 0;
|
|
|
|
pon_dev = devm_kzalloc(&pdev->dev, sizeof(*pon_dev), GFP_KERNEL);
|
|
if (!pon_dev)
|
|
return -ENOMEM;
|
|
pon_dev->dev = &pdev->dev;
|
|
|
|
ret = of_count_phandle_with_args(pdev->dev.of_node, "nvmem", NULL);
|
|
if (ret < 0) {
|
|
if (ret != -EPROBE_DEFER)
|
|
dev_err(&pdev->dev, "failed to get nvmem count, ret=%d\n",
|
|
ret);
|
|
return ret;
|
|
} else if (ret == 0) {
|
|
dev_err(&pdev->dev, "nvmem property empty\n");
|
|
return -EINVAL;
|
|
}
|
|
pon_dev->nvmem_count = ret;
|
|
|
|
pon_dev->nvmem = devm_kcalloc(&pdev->dev, pon_dev->nvmem_count,
|
|
sizeof(*pon_dev->nvmem), GFP_KERNEL);
|
|
if (!pon_dev->nvmem)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < pon_dev->nvmem_count; i++) {
|
|
scnprintf(buf, ARRAY_SIZE(buf), "pon_log%d", i);
|
|
pon_dev->nvmem[i] = devm_nvmem_device_get(&pdev->dev, buf);
|
|
if (IS_ERR(pon_dev->nvmem[i]) && i == 0 &&
|
|
PTR_ERR(pon_dev->nvmem[i]) != EPROBE_DEFER)
|
|
pon_dev->nvmem[i] = devm_nvmem_device_get(&pdev->dev,
|
|
"pon_log");
|
|
if (IS_ERR(pon_dev->nvmem[i])) {
|
|
ret = PTR_ERR(pon_dev->nvmem[i]);
|
|
if (ret != -EPROBE_DEFER)
|
|
dev_err(&pdev->dev, "failed to get nvmem device %d, ret=%d\n",
|
|
i, ret);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
/* Read how many SDAMs are used for the PON log in PMIC hardware */
|
|
ret = nvmem_device_read(pon_dev->nvmem[0], REG_SDAM_COUNT, 1, ®);
|
|
if (ret < 0)
|
|
return ret;
|
|
pon_dev->sdam_fifo_count = reg + 1;
|
|
|
|
if (pon_dev->sdam_fifo_count > pon_dev->nvmem_count) {
|
|
dev_err(&pdev->dev, "Missing nvmem handles; found %d, expected %d\n",
|
|
pon_dev->nvmem_count, pon_dev->sdam_fifo_count);
|
|
return -ENODEV;
|
|
}
|
|
|
|
pon_dev->log_max_entries = FIFO_SIZE * pon_dev->sdam_fifo_count
|
|
/ FIFO_ENTRY_SIZE;
|
|
pon_dev->log = devm_kcalloc(&pdev->dev, pon_dev->log_max_entries,
|
|
sizeof(*pon_dev->log), GFP_KERNEL);
|
|
if (!pon_dev->log)
|
|
return -ENOMEM;
|
|
|
|
pon_dev->ipc_log = ipc_log_context_create(IPC_LOG_PAGES, "pmic_pon", 0);
|
|
platform_set_drvdata(pdev, pon_dev);
|
|
|
|
ret = pmic_pon_log_parse(pon_dev);
|
|
if (ret < 0)
|
|
dev_err(&pdev->dev, "PMIC PON log parsing failed, ret=%d\n",
|
|
ret);
|
|
|
|
if (of_property_read_bool(pdev->dev.of_node, "qcom,pmic-fault-panic"))
|
|
pmic_pon_log_fault_panic(pon_dev);
|
|
|
|
if (pon_smpl_flag && smpl_panic) {
|
|
panic("SMPL DETECTED - TRIGGER PANIC");
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int pmic_pon_log_remove(struct platform_device *pdev)
|
|
{
|
|
struct pmic_pon_log_dev *pon_dev = platform_get_drvdata(pdev);
|
|
|
|
ipc_log_context_destroy(pon_dev->ipc_log);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id pmic_pon_log_of_match[] = {
|
|
{ .compatible = "qcom,pmic-pon-log" },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, pmic_pon_log_of_match);
|
|
|
|
static struct platform_driver pmic_pon_log_driver = {
|
|
.driver = {
|
|
.name = "qti-pmic-pon-log",
|
|
.of_match_table = of_match_ptr(pmic_pon_log_of_match),
|
|
},
|
|
.probe = pmic_pon_log_probe,
|
|
.remove = pmic_pon_log_remove,
|
|
};
|
|
module_platform_driver(pmic_pon_log_driver);
|
|
|
|
MODULE_DESCRIPTION("QTI PMIC PON log driver");
|
|
MODULE_LICENSE("GPL");
|