511 lines
23 KiB
C
Executable File
511 lines
23 KiB
C
Executable File
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _SOC_QCOM_LLCC_PERFMON_H_
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#define _SOC_QCOM_LLCC_PERFMON_H_
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#define VER_CHK(v) (v >= LLCC_VERSION_2_1)
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#define VER_CHK4(v) (v >= LLCC_VERSION_4)
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#define VER_CHK6(v) ((v) >= LLCC_VERSION_6)
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/* COMMON */
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#define LLCC_COMMON_BASE(v) (VER_CHK6(v) ? 0x64000 : (VER_CHK(v) ? 0x34000 : 0x30000))
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#define LLCC_COMMON_HW_INFO(v) (LLCC_COMMON_BASE(v) + 0x0)
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#define LLCC_COMMON_STATUS0(v) (LLCC_COMMON_BASE(v) + 0xC)
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/* FEAC */
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#define FEAC_PROF_FLTR_CFG_BASE(v) (VER_CHK6(v) ? 0x73000 : (VER_CHK(v) ? 0x43000 : 0x37000))
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#define FEAC_PROF_FILTER_0_CFG1(v) (FEAC_PROF_FLTR_CFG_BASE(v) + 0x4)
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#define FEAC_PROF_FILTER_0_CFG2(v) (FEAC_PROF_FLTR_CFG_BASE(v) + 0x8)
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#define FEAC_PROF_FILTER_0_CFG3(v) (FEAC_PROF_FLTR_CFG_BASE(v) + 0xC)
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#define FEAC_PROF_FILTER_0_CFG5(v) (FEAC_PROF_FLTR_CFG_BASE(v) + 0x14)
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#define FEAC_PROF_FILTER_0_CFG6(v) (FEAC_PROF_FLTR_CFG_BASE(v) + 0x18)
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/* Mach 9*/
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#define FEAC_PROF_FILTER_0_SCID_CFG0 0x73018
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#define FEAC_PROF_FILTER_0_SCID_CFG1 0x7301C
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#define FEAC_PROF_FILTER_0_CFG7(v) (FEAC_PROF_FLTR_CFG_BASE(v) + (VER_CHK6(v) ? 0x20 : 0x1C))
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#define FEAC_PROF_FILTER_1_CFG1(v) (FEAC_PROF_FLTR_CFG_BASE(v) + 0x34)
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#define FEAC_PROF_FILTER_1_CFG2(v) (FEAC_PROF_FLTR_CFG_BASE(v) + 0x38)
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#define FEAC_PROF_FILTER_1_CFG3(v) (FEAC_PROF_FLTR_CFG_BASE(v) + 0x3C)
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#define FEAC_PROF_FILTER_1_CFG5(v) (FEAC_PROF_FLTR_CFG_BASE(v) + 0x44)
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#define FEAC_PROF_FILTER_1_CFG6(v) (FEAC_PROF_FLTR_CFG_BASE(v) + 0x48)
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/* Mach 9*/
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#define FEAC_PROF_FILTER_1_SCID_CFG0 0x73048
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#define FEAC_PROF_FILTER_1_SCID_CFG1 0x7304C
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#define FEAC_PROF_FILTER_1_CFG7(v) (FEAC_PROF_FLTR_CFG_BASE(v) + (VER_CHK6(v) ? 0x50 : 0x4C))
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#define FEAC_PROF_EVENT_n_CFG(v, n) ((FEAC_PROF_FLTR_CFG_BASE(v) + 0x60) + 4 * (n))
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#define FEAC_PROF_CFG(v) (FEAC_PROF_FLTR_CFG_BASE(v) + 0xA0)
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#define FEAC_PROF_CFG1(v) (FEAC_PROF_FLTR_CFG_BASE(v) + 0xA4)
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#define FEAC_LLCC2MC_PROF_CFG_0(v) (FEAC_PROF_FLTR_CFG_BASE(v) + 0xAC)
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#define FEAC_LLCC2MC_PROF_CFG_1(v) (FEAC_PROF_FLTR_CFG_BASE(v) + 0xB0)
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/* FERC */
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#define FERC_PROF_FLTR_CFG_BASE(v) (VER_CHK6(v) ? 0x79000 : (VER_CHK(v) ? 0x49000 : 0x3B000))
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#define FERC_PROF_FILTER_0_CFG0(v) (FERC_PROF_FLTR_CFG_BASE(v) + 0x0)
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#define FERC_PROF_FILTER_1_CFG0(v) (FERC_PROF_FLTR_CFG_BASE(v) + 0x10)
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#define FERC_PROF_EVENT_n_CFG(v, n) ((FERC_PROF_FLTR_CFG_BASE(v) + 0x20) + 4 * (n))
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#define FERC_PROF_CFG(v) (FERC_PROF_FLTR_CFG_BASE(v) + 0x60)
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/* FEWC */
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#define FEWC_PROF_FLTR_CFG_BASE(v) (VER_CHK6(v) ? 0x69000 : (VER_CHK(v) ? 0x39000 : 0x33000))
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#define FEWC_PROF_FILTER_0_CFG0(v) (FEWC_PROF_FLTR_CFG_BASE(v) + 0x0)
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#define FEWC_PROF_FILTER_1_CFG0(v) (FEWC_PROF_FLTR_CFG_BASE(v) + 0x10)
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#define FEWC_PROF_EVENT_n_CFG(v, n) ((FEWC_PROF_FLTR_CFG_BASE(v) + 0x20) + 4 * (n))
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/* EWB FEWC */
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#define DRP2EWB_PROF_FILTER_0_CFG1 (0x69084)
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#define DRP2EWB_PROF_FILTER_1_CFG1 (0x69094)
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#define DRP2EWB_PROF_BEAT_SCALING_CFG (0x690A0)
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#define LCP2EWB_PROF_FILTER_0_CFG1 (0x690A8)
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#define LCP2EWB_PROF_FILTER_1_CFG1 (0x690B8)
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#define LCP2EWB_PROF_BEAT_SCALING_CFG (0x690C4)
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#define WB2EWB_PROF_FILTER_0_CFG1 (0x690CC)
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#define WB2EWB_PROF_FILTER_1_CFG1 (0x690DC)
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#define WB2EWB_PROF_BEAT_SCALING_CFG (0x690E8)
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#define EWB_MISC_PROF_BEAT_SCALING_CFG (0x690EC)
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#define EWB_FCS_PROF_FILTER_0_CFG (0x690F4)
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#define EWB_FCS_PROF_FILTER_1_CFG (0x690F4)
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#define EWB_PROF_EVENT_n_CFG(n) (0x69100 + 4 * (n))
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/* LCP */
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#define LCP_PROF_FLTR_CFG_BASE(v) (VER_CHK6(v) ? 0xE2000 : 0xA2000)
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#define LCP_PROF_FILTER_0_CFG0(v) (LCP_PROF_FLTR_CFG_BASE(v) + 0x0)
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#define LCP_PROF_FILTER_1_CFG0(v) (LCP_PROF_FLTR_CFG_BASE(v) + 0x4)
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#define LCP_PROF_EVENT_n_CFG(v, n) ((LCP_PROF_FLTR_CFG_BASE(v) + 0x8) + 4 * (n))
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/* BEAC */
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#define BEAC0_PROF_FLTR_CFG_BASE(v) (VER_CHK(v) ? 0x61000 : 0x049000)
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#define BEAC0_PROF_FILTER_0_CFG3(v) (BEAC0_PROF_FLTR_CFG_BASE(v) + 0xC)
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#define BEAC0_PROF_FILTER_0_CFG4(v) (BEAC0_PROF_FLTR_CFG_BASE(v) + 0x10)
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#define BEAC0_PROF_FILTER_0_CFG5(v) (BEAC0_PROF_FLTR_CFG_BASE(v) + 0x14)
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#define BEAC0_PROF_FILTER_0_CFG2(v) (BEAC0_PROF_FLTR_CFG_BASE(v) + 0x8)
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#define BEAC0_PROF_FILTER_1_CFG2(v) (BEAC0_PROF_FLTR_CFG_BASE(v) + 0x28)
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#define BEAC0_PROF_FILTER_1_CFG3(v) (BEAC0_PROF_FLTR_CFG_BASE(v) + 0x2C)
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#define BEAC0_PROF_FILTER_1_CFG4(v) (BEAC0_PROF_FLTR_CFG_BASE(v) + 0x30)
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#define BEAC0_PROF_FILTER_1_CFG5(v) (BEAC0_PROF_FLTR_CFG_BASE(v) + 0x34)
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#define BEAC0_PROF_EVENT_n_CFG(v, n) ((BEAC0_PROF_FLTR_CFG_BASE(v) + 0x40) + 4 * (n))
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#define BEAC0_PROF_CFG(v) (BEAC0_PROF_FLTR_CFG_BASE(v) + 0x80)
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#define BEAC0_PROF_CFG0(v) (BEAC0_PROF_FLTR_CFG_BASE(v) + 0x88)
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#define BEAC0_PROF_CFG1(v) (BEAC0_PROF_FLTR_CFG_BASE(v) + 0x8C)
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#define BEAC_INST_OFF (0x4000)
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/* BERC */
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#define BERC_PROF_FLTR_CFG_BASE(v) (VER_CHK6(v) ? 0x6D000 : (VER_CHK(v) ? 0x3D000 : 0x39000))
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#define BERC_PROF_FILTER_0_CFG0(v) (BERC_PROF_FLTR_CFG_BASE(v) + 0x0)
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#define BERC_PROF_FILTER_1_CFG0(v) (BERC_PROF_FLTR_CFG_BASE(v) + 0x10)
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#define BERC_PROF_EVENT_n_CFG(v, n) ((BERC_PROF_FLTR_CFG_BASE(v) + 0x20) + 4 * (n))
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#define BERC_PROF_CFG(v) (BERC_PROF_FLTR_CFG_BASE(v) + 0x60)
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/* TRP */
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#define TRP_PROF_FLTR_CFG_BASE(v) (VER_CHK6(v) ? 0x48000 : 0x024000)
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#define TRP_PROF_FILTER_0_CFG1(v) (TRP_PROF_FLTR_CFG_BASE(v) + 0x4)
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#define TRP_PROF_FILTER_0_CFG2(v) (TRP_PROF_FLTR_CFG_BASE(v) + 0x8)
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/* Mach 9 */
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#define TRP_PROF_FILTER_0_SCID_CFG0 (0x48008)
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#define TRP_PROF_FILTER_0_SCID_CFG1 (0x4800C)
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#define TRP_PROF_FILTER_1_CFG1(v) (TRP_PROF_FLTR_CFG_BASE(v) + 0x14)
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#define TRP_PROF_FILTER_1_CFG2(v) (TRP_PROF_FLTR_CFG_BASE(v) + 0x18)
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/* Mach 9 */
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#define TRP_PROF_FILTER_1_SCID_CFG0 (0x48018)
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#define TRP_PROF_FILTER_1_SCID_CFG1 (0x4801C)
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#define TRP_PROF_EVENT_n_CFG(v, n) ((VER_CHK6(v) ? 0x48030 : 0x024020) + 4 * (n))
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#define TRP_SCID_n_STATUS(n) (0x000004 + (0x1000 * (n)))
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/* DRP */
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#define DRP_PROF_FLTR_CFG_BASE(v) (VER_CHK6(v) ? 0x81000 : (VER_CHK(v) ? 0x51000 : 0x044000))
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#define DRP_PROF_EVENT_n_CFG(v, n) ((DRP_PROF_FLTR_CFG_BASE(v) + 0x10) + 4 * (n))
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#define DRP_PROF_CFG(v) (DRP_PROF_FLTR_CFG_BASE(v) + 0x50)
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/* PMGR */
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#define PMGR_PROF_EVENT_n_CFG(v, n) ((VER_CHK6(v) ? 0x7D000 : (VER_CHK(v) ? 0x4D000 : 0x03F000)\
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) + 4 * (n))
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#define PERFMON_BASE(v) (VER_CHK6(v) ? 0x66000 : (VER_CHK(v) ? 0x36000 : 0x031000))
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#define PERFMON_COUNTER_n_CONFIG(v, n) ((PERFMON_BASE(v) + 0x20) + 4 * (n))
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#define PERFMON_NUM_CNTRS_DUMP_CFG(v) (PERFMON_BASE(v) + 0xEC)
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#define PERFMON_MODE(v) (PERFMON_BASE(v) + 0xC)
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#define PERFMON_DUMP(v) (VER_CHK6(v) ? 0x67000 : (VER_CHK4(v) ? 0x37000 :\
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VER_CHK(v) ? 0x36010 : 0x031010))
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#define LLCC_COUNTER_n_VALUE(v, n) ((VER_CHK6(v) ? 0x67008 : ((VER_CHK4(v) ? 0x37008 :\
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VER_CHK(v) ? 0x36060 : 0x31060))) + 4 * (n))
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#define EVENT_NUM_MAX (256)
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#define SCID_MAX(v) (VER_CHK6(v) ? (32 + 4) : (32))
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/* Perfmon */
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#define CLEAR_ON_ENABLE BIT(31)
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#define CLEAR_ON_DUMP BIT(30)
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#define FREEZE_ON_SATURATE BIT(29)
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#define CHAINING_EN BIT(28)
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#define COUNT_CLOCK_EVENT BIT(24)
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#define EVENT_SELECT_SHIFT (16)
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#define PERFMON_EVENT_SELECT_MASK GENMASK(EVENT_SELECT_SHIFT + 4, EVENT_SELECT_SHIFT)
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#define PORT_SELECT_SHIFT (0)
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#define PERFMON_PORT_SELECT_MASK GENMASK(PORT_SELECT_SHIFT + 3, PORT_SELECT_SHIFT)
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#define MANUAL_MODE (0)
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#define TIMED_MODE (1)
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#define TRIGGER_MODE (2)
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#define DUMP_SEL_SHIFT (13)
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#define DUMP_SEL BIT(DUMP_SEL_SHIFT)
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#define MONITOR_EN_SHIFT (15)
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#define MONITOR_EN BIT(MONITOR_EN_SHIFT)
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#define PERFMON_MODE_DUMP_SEL_MASK GENMASK(DUMP_SEL_SHIFT + 0, DUMP_SEL_SHIFT)
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#define PERFMON_MODE_MONITOR_EN_MASK GENMASK(MONITOR_EN_SHIFT + 0, MONITOR_EN_SHIFT)
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#define MONITOR_MODE_SHIFT (0)
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#define PERFMON_MODE_MONITOR_MODE_MASK GENMASK(MONITOR_MODE_SHIFT + 0, MONITOR_MODE_SHIFT)
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#define MONITOR_DUMP BIT(0)
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#define DUMP_NUM_COUNTERS_SHIFT (0)
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#define DUMP_NUM_COUNTERS_MASK GENMASK(DUMP_NUM_COUNTERS_SHIFT + 3,\
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DUMP_NUM_COUNTERS_SHIFT)
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/* COMMON */
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#define BYTE_SCALING (1024)
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#define BYTE_SCALING_DEF (512)
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#define MC_PROFTAG_DEF (2)
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#define BEAT_SCALING (32)
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#define LB_CNT_SHIFT (28)
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#define LB_CNT_MASK GENMASK(LB_CNT_SHIFT + 3, LB_CNT_SHIFT)
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#define NUM_MC_SHIFT (10)
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#define NUM_MC_MASK GENMASK(NUM_MC_SHIFT + 1, NUM_MC_SHIFT)
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#define BYTE_SCALING_SHIFT (16)
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#define PROF_CFG_BYTE_SCALING_MASK GENMASK(BYTE_SCALING_SHIFT + 11, BYTE_SCALING_SHIFT)
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#define BEAT_SCALING_SHIFT (8)
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#define PROF_CFG_BEAT_SCALING_MASK GENMASK(BEAT_SCALING_SHIFT + 7, BEAT_SCALING_SHIFT)
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#define WR_BEAT_FILTER_SEL_SHIFT (6)
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#define WR_BEAT_FILTER_SEL_MASK GENMASK(WR_BEAT_FILTER_SEL_SHIFT + 0, \
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WR_BEAT_FILTER_SEL_SHIFT)
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#define WR_BEAT_FILTER_EN_SHIFT (5)
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#define WR_BEAT_FILTER_EN BIT(WR_BEAT_FILTER_EN_SHIFT)
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#define WR_BEAT_FILTER_EN_MASK GENMASK(WR_BEAT_FILTER_EN_SHIFT + 0, \
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WR_BEAT_FILTER_EN_SHIFT)
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#define RD_BEAT_FILTER_SEL_SHIFT (4)
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#define RD_BEAT_FILTER_SEL_MASK GENMASK(RD_BEAT_FILTER_SEL_SHIFT + 0, \
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RD_BEAT_FILTER_SEL_SHIFT)
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#define RD_BEAT_FILTER_EN_SHIFT (3)
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#define RD_BEAT_FILTER_EN BIT(RD_BEAT_FILTER_EN_SHIFT)
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#define RD_BEAT_FILTER_EN_MASK GENMASK(RD_BEAT_FILTER_EN_SHIFT + 0, \
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RD_BEAT_FILTER_EN_SHIFT)
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#define MC_PROFTAG_SHIFT (1)
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#define MC_PROFTAG_MASK GENMASK(MC_PROFTAG_SHIFT + 1, MC_PROFTAG_SHIFT)
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#define BEAT_SCALING_0_SHIFT_ (8)
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#define PROF_CFG_BEAT_SCALING_0_MASK GENMASK(BEAT_SCALING_0_SHIFT + 7, BEAT_SCALING_0_SHIFT)
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#define BEAT_SCALING_1_SHIFT_ (8)
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#define PROF_CFG_BEAT_SCALING_1_MASK GENMASK(BEAT_SCALING_1_SHIFT + 7, BEAT_SCALING_1_SHIFT)
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#define WR_BEAT_FILTER_SEL_0_SHIFT (6)
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#define WR_BEAT_FILTER_SEL_0_MASK GENMASK(WR_BEAT_FILTER_SEL_0_SHIFT + 0, \
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WR_BEAT_FILTER_SEL_0_SHIFT)
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#define WR_BEAT_FILTER_EN_0_SHIFT (5)
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#define WR_BEAT_FILTER_EN_0 BIT(WR_BEAT_FILTER_EN_0_SHIFT)
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#define WR_BEAT_FILTER_EN_0_MASK GENMASK(WR_BEAT_FILTER_EN_0_SHIFT + 0, \
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WR_BEAT_FILTER_EN_0_SHIFT)
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#define RD_BEAT_FILTER_SEL_0_SHIFT (4)
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#define RD_BEAT_FILTER_SEL_0_MASK GENMASK(WR_BEAT_FILTER_SEL_0_SHIFT + 0, \
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WR_BEAT_FILTER_SEL_0_SHIFT)
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#define RD_BEAT_FILTER_EN_0_SHIFT (3)
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#define RD_BEAT_FILTER_EN_0 BIT(RD_BEAT_FILTER_EN_0_SHIFT)
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#define RD_BEAT_FILTER_EN_0_MASK GENMASK(WR_BEAT_FILTER_EN_0_SHIFT + 0, \
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WR_BEAT_FILTER_EN_0_SHIFT)
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#define WR_BEAT_FILTER_SEL_1_SHIFT (6)
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#define WR_BEAT_FILTER_SEL_1_MASK GENMASK(WR_BEAT_FILTER_SEL_1_SHIFT + 0, \
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WR_BEAT_FILTER_SEL_1_SHIFT)
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#define WR_BEAT_FILTER_EN_1_SHIFT (5)
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#define WR_BEAT_FILTER_EN_1 BIT(WR_BEAT_FILTER_EN_1_SHIFT)
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#define WR_BEAT_FILTER_EN_1_MASK GENMASK(WR_BEAT_FILTER_EN_1_SHIFT + 0, \
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WR_BEAT_FILTER_EN_1_SHIFT)
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#define RD_BEAT_FILTER_SEL_1_SHIFT (4)
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#define RD_BEAT_FILTER_SEL_1_MASK GENMASK(WR_BEAT_FILTER_SEL_1_SHIFT + 0, \
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WR_BEAT_FILTER_SEL_1_SHIFT)
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#define RD_BEAT_FILTER_EN_1_SHIFT (3)
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#define RD_BEAT_FILTER_EN_1 BIT(RD_BEAT_FILTER_EN_1_SHIFT)
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#define RD_BEAT_FILTER_EN_1_MASK GENMASK(WR_BEAT_FILTER_EN_1_SHIFT + 0, \
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WR_BEAT_FILTER_EN_1_SHIFT)
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#define PROF_EN_SHIFT (0)
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#define PROF_EN BIT(PROF_EN_SHIFT)
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#define PROF_CFG_EN_MASK GENMASK(PROF_EN_SHIFT + 0, PROF_EN_SHIFT)
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#define FILTER_EN_SHIFT (31)
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#define FILTER_EN BIT(FILTER_EN_SHIFT)
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#define FILTER_EN_MASK GENMASK(FILTER_EN_SHIFT + 0, FILTER_EN_SHIFT)
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#define FILTER_0 (0)
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#define FILTER_0_MASK GENMASK(FILTER_0 + 0, FILTER_0)
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#define FILTER_1 (1)
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#define FILTER_1_MASK GENMASK(FILTER_1 + 0, FILTER_1)
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#define FILTER_SEL_SHIFT (16)
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#define FILTER_SEL_MASK GENMASK(FILTER_SEL_SHIFT + 0, FILTER_SEL_SHIFT)
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#define EVENT_SEL_SHIFT (0)
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#define EVENT_SEL_MASK GENMASK(EVENT_SEL_SHIFT + 5, EVENT_SEL_SHIFT)
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#define EVENT_SEL_MASK7 GENMASK(EVENT_SEL_SHIFT + 6, EVENT_SEL_SHIFT)
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#define EVENT_SEL_MASK8 GENMASK(EVENT_SEL_SHIFT + 7, EVENT_SEL_SHIFT)
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#define MEMTAGOPS_MASK_SHIFT (12)
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#define MEMTAGOPS_MASK_MASK GENMASK(MEMTAGOPS_MASK_SHIFT + 2, MEMTAGOPS_MASK_SHIFT)
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#define MEMTAGOPS_MATCH_SHIFT (10)
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#define MEMTAGOPS_MATCH_MASK GENMASK(MEMTAGOPS_MATCH_SHIFT + 2, MEMTAGOPS_MATCH_SHIFT)
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#define DIRTYINFO_MASK_SHIFT (1)
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#define DIRTYINFO_MASK_MASK GENMASK(DIRTYINFO_MASK_SHIFT + 1, DIRTYINFO_MASK_SHIFT)
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#define DIRTYINFO_MATCH_SHIFT (0)
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#define DIRTYINFO_MATCH_MASK GENMASK(DIRTYINFO_MATCH_SHIFT + 1, DIRTYINFO_MATCH_SHIFT)
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#define CACHEALLOC_MASK_SHIFT (16)
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#define CACHEALLOC_MASK_MASK GENMASK(CACHEALLOC_MASK_SHIFT + 3, CACHEALLOC_MASK_SHIFT)
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#define CACHEALLOC_MATCH_SHIFT (12)
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#define CACHEALLOC_MATCH_MASK GENMASK(CACHEALLOC_MATCH_SHIFT + 3, CACHEALLOC_MATCH_SHIFT)
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#define OPCODE_MASK_SHIFT (28)
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#define OPCODE_MASK_MASK GENMASK(OPCODE_MASK_SHIFT + 3, OPCODE_MASK_SHIFT)
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#define OPCODE_MATCH_SHIFT (24)
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#define OPCODE_MATCH_MASK GENMASK(OPCODE_MATCH_SHIFT + 3, OPCODE_MATCH_SHIFT)
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#define MID_MASK_SHIFT (16)
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#define MID_MASK_MASK GENMASK(MID_MASK_SHIFT + 15, MID_MASK_SHIFT)
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#define MID_MATCH_SHIFT (0)
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#define MID_MATCH_MASK GENMASK(MID_MATCH_SHIFT + 15, MID_MATCH_SHIFT)
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#define SCID_MASK_SHIFT (16)
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#define SCID_MASK_MASK GENMASK(SCID_MASK_SHIFT + 15, SCID_MASK_SHIFT)
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#define SCID_MATCH_SHIFT (0)
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#define SCID_MATCH_MASK GENMASK(SCID_MATCH_SHIFT + 15, SCID_MATCH_SHIFT)
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#define SCID_MULTI_MATCH_SHIFT (0)
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#define SCID_MULTI_MATCH_MASK GENMASK(SCID_MULTI_MATCH_SHIFT + 31, SCID_MULTI_MATCH_SHIFT)
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#define SCID_MULTI_MATCH_CFG1_MASK GENMASK(SCID_MULTI_MATCH_SHIFT + 3, SCID_MULTI_MATCH_SHIFT)
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#define PROFTAG_MASK_SHIFT (2)
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#define PROFTAG_MASK_MASK GENMASK(PROFTAG_MASK_SHIFT + 1, PROFTAG_MASK_SHIFT)
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#define PROFTAG_MATCH_SHIFT (0)
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#define PROFTAG_MATCH_MASK GENMASK(PROFTAG_MATCH_SHIFT + 1, PROFTAG_MATCH_SHIFT)
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/* FEAC */
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#define FEAC_SCALING_FILTER_SEL_SHIFT (2)
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#define FEAC_SCALING_FILTER_SEL_MASK GENMASK(FEAC_SCALING_FILTER_SEL_SHIFT + 0,\
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FEAC_SCALING_FILTER_SEL_SHIFT)
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#define FEAC_SCALING_FILTER_EN_SHIFT (1)
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#define FEAC_SCALING_FILTER_EN BIT(FEAC_SCALING_FILTER_EN_SHIFT)
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#define FEAC_SCALING_FILTER_EN_MASK GENMASK(FEAC_SCALING_FILTER_EN_SHIFT + 0,\
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FEAC_SCALING_FILTER_EN_SHIFT)
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#define FEAC_WR_BEAT_FILTER_SEL_SHIFT (29)
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#define FEAC_WR_BEAT_FILTER_SEL_MASK GENMASK(FEAC_WR_BEAT_FILTER_SEL_SHIFT + 0,\
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FEAC_WR_BEAT_FILTER_SEL_SHIFT)
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#define FEAC_WR_BEAT_FILTER_EN_SHIFT (28)
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#define FEAC_WR_BEAT_FILTER_EN_MASK GENMASK(FEAC_WR_BEAT_FILTER_EN_SHIFT + 0,\
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FEAC_WR_BEAT_FILTER_EN_SHIFT)
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#define FEAC_WR_BEAT_FILTER_EN BIT(FEAC_WR_BEAT_FILTER_EN_SHIFT)
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#define FEAC_WR_BYTE_FILTER_SEL_SHIFT (6)
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#define FEAC_WR_BYTE_FILTER_SEL_MASK GENMASK(FEAC_WR_BYTE_FILTER_SEL_SHIFT + 0,\
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FEAC_WR_BYTE_FILTER_SEL_SHIFT)
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#define FEAC_WR_BYTE_FILTER_EN_SHIFT (5)
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#define FEAC_WR_BYTE_FILTER_EN_MASK GENMASK(FEAC_WR_BYTE_FILTER_EN_SHIFT + 0,\
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FEAC_WR_BYTE_FILTER_EN_SHIFT)
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#define FEAC_WR_BYTE_FILTER_EN BIT(FEAC_WR_BYTE_FILTER_EN_SHIFT)
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#define FEAC_RD_BEAT_FILTER_SEL_SHIFT (4)
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#define FEAC_RD_BEAT_FILTER_SEL_MASK GENMASK(FEAC_RD_BEAT_FILTER_SEL_SHIFT + 0,\
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FEAC_RD_BEAT_FILTER_SEL_SHIFT)
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#define FEAC_RD_BEAT_FILTER_EN_SHIFT (3)
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#define FEAC_RD_BEAT_FILTER_EN_MASK GENMASK(FEAC_RD_BEAT_FILTER_EN_SHIFT + 0,\
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FEAC_RD_BEAT_FILTER_EN_SHIFT)
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#define FEAC_RD_BEAT_FILTER_EN BIT(FEAC_RD_BEAT_FILTER_EN_SHIFT)
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#define FEAC_RD_BYTE_FILTER_SEL_SHIFT (2)
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#define FEAC_RD_BYTE_FILTER_SEL_MASK GENMASK(FEAC_RD_BYTE_FILTER_SEL_SHIFT + 0,\
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FEAC_RD_BYTE_FILTER_SEL_SHIFT)
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#define FEAC_RD_BYTE_FILTER_EN_SHIFT (1)
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#define FEAC_RD_BYTE_FILTER_EN_MASK GENMASK(FEAC_RD_BYTE_FILTER_EN_SHIFT + 0,\
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FEAC_RD_BYTE_FILTER_EN_SHIFT)
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#define FEAC_RD_BYTE_FILTER_EN BIT(FEAC_RD_BYTE_FILTER_EN_SHIFT)
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#define FEAC_ADDR_LOWER_MATCH_SHIFT (0)
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#define FEAC_ADDR_LOWER_MATCH_MASK GENMASK(FEAC_ADDR_LOWER_MATCH_SHIFT + 31,\
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FEAC_ADDR_LOWER_MATCH_SHIFT)
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#define FEAC_ADDR_LOWER_MASK_SHIFT (0)
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#define FEAC_ADDR_LOWER_MASK_MASK GENMASK(FEAC_ADDR_LOWER_MASK_SHIFT + 31,\
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FEAC_ADDR_LOWER_MASK_SHIFT)
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#define FEAC_ADDR_UPPER_MATCH_SHIFT (0)
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#define FEAC_ADDR_UPPER_MATCH_MASK GENMASK(FEAC_ADDR_UPPER_MATCH_SHIFT + 4,\
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FEAC_ADDR_UPPER_MATCH_SHIFT)
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#define FEAC_ADDR_UPPER_MASK_SHIFT (4)
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#define FEAC_ADDR_UPPER_MASK_MASK GENMASK(FEAC_ADDR_UPPER_MASK_SHIFT + 4,\
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FEAC_ADDR_UPPER_MASK_SHIFT)
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#define LLCC2MC_PROFTAG_MASK_SHIFT (17)
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#define LLCC2MC_PROFTAG_MASK_MASK GENMASK(LLCC2MC_PROFTAG_MASK_SHIFT + 1, \
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LLCC2MC_PROFTAG_MASK_SHIFT)
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#define LLCC2MC_PROFTAG_MATCH_SHIFT (19)
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#define LLCC2MC_PROFTAG_MATCH_MASK GENMASK(LLCC2MC_PROFTAG_MATCH_SHIFT + 1, \
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LLCC2MC_PROFTAG_MATCH_SHIFT)
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#define LLCC2LCP_PROFTAG_MASK_SHIFT (22)
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#define LLCC2LCP_PROFTAG_MASK_MASK GENMASK(LLCC2LCP_PROFTAG_MASK_SHIFT + 1, \
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LLCC2LCP_PROFTAG_MASK_SHIFT)
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#define LLCC2LCP_PROFTAG_MATCH_SHIFT (24)
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#define LLCC2LCP_PROFTAG_MATCH_MASK GENMASK(LLCC2LCP_PROFTAG_MATCH_SHIFT + 1, \
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LLCC2LCP_PROFTAG_MATCH_SHIFT)
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/* EWB */
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#define EWB_FCS_PROFTAG_MATCH_SHIFT (0)
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#define EWB_FCS_PROFTAG_MATCH_MASK GENMASK(EWB_FCS_PROFTAG_MATCH_SHIFT + 1,\
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EWB_FCS_PROFTAG_MATCH_SHIFT)
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#define EWB_FCS_PROFTAG_MASK_SHIFT (2)
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#define EWB_FCS_PROFTAG_MASK_MASK GENMASK(EWB_FCS_PROFTAG_MASK_SHIFT + 1,\
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EWB_FCS_PROFTAG_MASK_SHIFT)
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#define EWB_FILTER_EN_SHIFT (31)
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#define EWB_FILTER_EN_MASK GENMASK(EWB_FILTER_EN_SHIFT + 0, EWB_FILTER_EN_SHIFT)
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#define EWB_FILTER_EN BIT(31)
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#define EWB_FILTER_SEL_SHIFT (16)
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#define EWB_FILTER_SEL_MASK GENMASK(EWB_FILTER_SEL_SHIFT + 0, EWB_FILTER_SEL_SHIFT)
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#define EWB_EVENT_SEL_SHIFT (0)
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#define EWB_EVENT_SEL_MASK GENMASK(EWB_EVENT_SEL_SHIFT + 5, EWB_EVENT_SEL_SHIFT)
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#define EWB_PROFTAG_MASK_SHIFT (20)
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#define EWB_PROFTAG_MASK_MASK GENMASK(EWB_PROFTAG_MASK_SHIFT + 1,\
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EWB_PROFTAG_MASK_SHIFT)
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#define EWB_PROFTAG_MATCH_SHIFT (22)
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#define EWB_PROFTAG_MATCH_MASK GENMASK(EWB_PROFTAG_MATCH_SHIFT + 1,\
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EWB_PROFTAG_MATCH_SHIFT)
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#define EWB_BEAT_SCALING_FACTOR_0_SHIFT (0)
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#define EWB_BEAT_SCALING_FACTOR_0_MASK GENMASK(EWB_BEAT_SCALING_FACTOR_0_SHIFT + 7,\
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EWB_BEAT_SCALING_FACTOR_0_SHIFT)
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#define EWB_BEAT_FILTER_EN_0_SHIFT (8)
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#define EWB_BEAT_FILTER_EN_0_EN BIT(EWB_BEAT_FILTER_EN_0_SHIFT)
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#define EWB_BEAT_FILTER_EN_0_MASK GENMASK(EWB_BEAT_FILTER_EN_0_SHIFT + 0,\
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EWB_BEAT_FILTER_EN_0_SHIFT)
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#define EWB_BEAT_FILTER_SEL_0_SHIFT (9)
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#define EWB_BEAT_FILTER_SEL_0_EN BIT(EWB_BEAT_FILTER_SEL_0_SHIFT)
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#define EWB_BEAT_FILTER_SEL_0_MASK GENMASK(EWB_BEAT_FILTER_SEL_0_SHIFT + 0,\
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EWB_BEAT_FILTER_SEL_0_SHIFT)
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#define EWB_BEAT_SCALING_FACTOR_1_SHIFT (16)
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#define EWB_BEAT_SCALING_FACTOR_1_MASK GENMASK(EWB_BEAT_SCALING_FACTOR_1_SHIFT + 7,\
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EWB_BEAT_SCALING_FACTOR_1_SHIFT)
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#define EWB_BEAT_FILTER_EN_1_SHIFT (24)
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#define EWB_BEAT_FILTER_EN_1_EN BIT(EWB_BEAT_FILTER_EN_1_SHIFT)
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#define EWB_BEAT_FILTER_EN_1_MASK GENMASK(EWB_BEAT_FILTER_EN_1_SHIFT + 0,\
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EWB_BEAT_FILTER_EN_1_SHIFT)
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#define EWB_BEAT_FILTER_SEL_1_SHIFT (25)
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#define EWB_BEAT_FILTER_SEL_1_EN BIT(EWB_BEAT_FILTER_SEL_1_SHIFT)
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#define EWB_BEAT_FILTER_SEL_1_MASK GENMASK(EWB_BEAT_FILTER_SEL_1_SHIFT + 0,\
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EWB_BEAT_FILTER_SEL_1_SHIFT)
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#define EWB2LCP_BEAT_SCALING_FACTOR_SHIFT (0)
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#define EWB2LCP_BEAT_SCALING_FACTOR_MASK GENMASK(EWB2LCP_BEAT_SCALING_FACTOR_SHIFT + 7,\
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EWB2LCP_BEAT_SCALING_FACTOR_SHIFT)
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#define EWB2MC_BEAT_SCALING_FACTOR_SHIFT (8)
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#define EWB2MC_BEAT_SCALING_FACTOR_MASK GENMASK(EWB2MC_BEAT_SCALING_FACTOR_SHIFT + 7, \
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EWB2MC_BEAT_SCALING_FACTOR_SHIFT)
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/* LCP */
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#define LCP_PROFTAG_MATCH_SHIFT (0)
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#define LCP_PROFTAG_MATCH_MASK GENMASK(LCP_PROFTAG_MATCH_SHIFT + 1,\
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LCP_PROFTAG_MATCH_SHIFT)
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#define LCP_PROFTAG_MASK_SHIFT (2)
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#define LCP_PROFTAG_MASK_MASK GENMASK(LCP_PROFTAG_MASK_SHIFT + 1,\
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LCP_PROFTAG_MASK_SHIFT)
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#define LCP_FILTER_EN_SHIFT (31)
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#define LCP_FILTER_EN_MASK GENMASK(LCP_FILTER_EN_SHIFT + 0,\
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LCP_FILTER_EN_SHIFT)
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#define LCP_FILTER_EN BIT(31)
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#define LCP_FILTER_SEL_SHIFT (16)
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#define LCP_FILTER_SEL_MASK GENMASK(LCP_FILTER_SEL_SHIFT + 0,\
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LCP_FILTER_SEL_SHIFT)
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#define LCP_EVENT_SEL_SHIFT (0)
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#define LCP_EVENT_SEL_MASK GENMASK(LCP_EVENT_SEL_SHIFT + 6,\
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LCP_EVENT_SEL_SHIFT)
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/* BEAC */
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#define BEAC_PROFTAG_MASK_SHIFT (14)
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#define BEAC_PROFTAG_MASK_MASK GENMASK(BEAC_PROFTAG_MASK_SHIFT + 1,\
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BEAC_PROFTAG_MASK_SHIFT)
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#define BEAC_PROFTAG_MATCH_SHIFT (12)
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#define BEAC_PROFTAG_MATCH_MASK GENMASK(BEAC_PROFTAG_MATCH_SHIFT + 1,\
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BEAC_PROFTAG_MATCH_SHIFT)
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#define BEAC_MC_PROFTAG_SHIFT (1)
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#define BEAC_MC_PROFTAG_MASK GENMASK(BEAC_MC_PROFTAG_SHIFT + 1, BEAC_MC_PROFTAG_SHIFT)
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#define BEAC_WR_BEAT_FILTER_SEL_SHIFT (6)
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#define BEAC_WR_BEAT_FILTER_SEL_MASK GENMASK(BEAC_WR_BEAT_FILTER_SEL_SHIFT + 0,\
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BEAC_WR_BEAT_FILTER_SEL_SHIFT)
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#define BEAC_WR_BEAT_FILTER_EN_SHIFT (5)
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#define BEAC_WR_BEAT_FILTER_EN_MASK GENMASK(BEAC_WR_BEAT_FILTER_EN_SHIFT + 0,\
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BEAC_WR_BEAT_FILTER_EN_SHIFT)
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#define BEAC_WR_BEAT_FILTER_EN BIT(BEAC_WR_BEAT_FILTER_EN_SHIFT)
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#define BEAC_RD_BEAT_FILTER_SEL_SHIFT (4)
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#define BEAC_RD_BEAT_FILTER_SEL_MASK GENMASK(BEAC_RD_BEAT_FILTER_SEL_SHIFT + 0,\
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BEAC_RD_BEAT_FILTER_SEL_SHIFT)
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#define BEAC_RD_BEAT_FILTER_EN_SHIFT (3)
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#define BEAC_RD_BEAT_FILTER_EN_MASK GENMASK(BEAC_RD_BEAT_FILTER_EN_SHIFT + 0,\
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BEAC_RD_BEAT_FILTER_EN_SHIFT)
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#define BEAC_RD_BEAT_FILTER_EN BIT(BEAC_RD_BEAT_FILTER_EN_SHIFT)
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#define BEAC_ADDR_LOWER_MATCH_SHIFT (0)
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#define BEAC_ADDR_LOWER_MATCH_MASK GENMASK(BEAC_ADDR_LOWER_MATCH_SHIFT + 31,\
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BEAC_ADDR_LOWER_MATCH_SHIFT)
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#define BEAC_ADDR_LOWER_MASK_SHIFT (0)
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#define BEAC_ADDR_LOWER_MASK_MASK GENMASK(BEAC_ADDR_LOWER_MASK_SHIFT + 31,\
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BEAC_ADDR_LOWER_MASK_SHIFT)
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#define BEAC_ADDR_UPPER_MATCH_SHIFT (0)
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#define BEAC_ADDR_UPPER_MATCH_MASK GENMASK(BEAC_ADDR_UPPER_MATCH_SHIFT + 4,\
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BEAC_ADDR_UPPER_MATCH_SHIFT)
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#define BEAC_ADDR_UPPER_MASK_SHIFT (4)
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#define BEAC_ADDR_UPPER_MASK_MASK GENMASK(BEAC_ADDR_UPPER_MASK_SHIFT + 4,\
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BEAC_ADDR_UPPER_MASK_SHIFT)
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/* TRP */
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#define TRP_SCID_MATCH_SHIFT (0)
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#define TRP_SCID_MATCH_MASK GENMASK(TRP_SCID_MATCH_SHIFT + 4, TRP_SCID_MATCH_SHIFT)
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#define TRP_SCID_MASK_SHIFT (8)
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#define TRP_SCID_MASK_MASK GENMASK(TRP_SCID_MASK_SHIFT + 4, TRP_SCID_MASK_SHIFT)
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#define TRP_WAY_ID_MATCH_SHIFT (0)
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#define TRP_WAY_ID_MATCH_MASK GENMASK(TRP_WAY_ID_MATCH_SHIFT + 4, TRP_WAY_ID_MATCH_SHIFT)
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#define TRP_WAY_ID_MASK_SHIFT (8)
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#define TRP_WAY_ID_MASK_MASK GENMASK(TRP_WAY_ID_MASK_SHIFT + 4, TRP_WAY_ID_MASK_SHIFT)
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#define TRP_PROFTAG_MATCH_SHIFT (24)
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#define TRP_PROFTAG_MATCH_MASK GENMASK(TRP_PROFTAG_MATCH_SHIFT + 1,\
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TRP_PROFTAG_MATCH_SHIFT)
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#define TRP_PROFTAG_MASK_SHIFT (28)
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#define TRP_PROFTAG_MASK_MASK GENMASK(TRP_PROFTAG_MASK_SHIFT + 1, TRP_PROFTAG_MASK_SHIFT)
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#define TRP_SCID_STATUS_ACTIVE_SHIFT (0)
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#define TRP_SCID_STATUS_ACTIVE_MASK GENMASK(TRP_SCID_STATUS_ACTIVE_SHIFT + 0,\
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TRP_SCID_STATUS_ACTIVE_SHIFT)
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#define TRP_SCID_STATUS_DEACTIVE_SHIFT (1)
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#define TRP_SCID_STATUS_CURRENT_CAP_SHIFT (16)
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#define TRP_SCID_STATUS_CURRENT_CAP_MASK GENMASK(TRP_SCID_STATUS_CURRENT_CAP_SHIFT + 15,\
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TRP_SCID_STATUS_CURRENT_CAP_SHIFT)
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#define ADDR_LOWER_MASK (0xFFFFFFFF)
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#define ADDR_UPPER_MASK (0xF00000000)
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#define ADDR_UPPER_SHIFT (32)
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#define MAJOR_VER_MASK (0xFF000000)
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#define BRANCH_MASK (0x00FF0000)
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#define MINOR_MASK (0x0000FF00)
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#define LLCC_VERSION_0 (0x00000000)
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#define LLCC_VERSION_1 (0x01010200)
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#define LLCC_VERSION_2 (0x02000000)
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#define LLCC_VERSION_2_1 (0x02010000)
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#define LLCC_VERSION_3 (0x03000000)
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#define LLCC_VERSION_3_1 (0x03010000)
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#define LLCC_VERSION_4 (0x04000000)
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#define LLCC_VERSION_5 (0x05000000)
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#define LLCC_VERSION_6 (0x06000000)
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#define MAJOR_REV_NO(v) ((v & MAJOR_VER_MASK) >> 24)
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#define BRANCH_NO(v) ((v & BRANCH_MASK) >> 16)
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#define MINOR_NO(v) ((v & MINOR_MASK) >> 8)
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#define REV_0 (0x0)
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#define REV_1 (0x1)
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#define REV_2 (0x2)
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#define REV_4 (0x4)
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#define REV_5 (0x5)
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#define REV_6 (0x6)
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#define BANK_OFFSET (0x80000)
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#endif /* _SOC_QCOM_LLCC_PERFMON_H_ */
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