377 lines
13 KiB
C
Executable File
377 lines
13 KiB
C
Executable File
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
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* Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef __SMBLITE_CHARGER_REG_H
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#define __SMBLITE_CHARGER_REG_H
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#include <linux/bitops.h>
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#define PERPH_TYPE_OFFSET 0x04
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#define TYPE_MASK GENMASK(7, 0)
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#define PERPH_SUBTYPE_OFFSET 0x05
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#define SUBTYPE_MASK GENMASK(7, 0)
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#define INT_RT_STS_OFFSET 0x10
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#define REVID_REVISION4 0x103
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/********************************
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* CHGR Peripheral Registers *
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********************************/
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#define BATTERY_CHARGER_STATUS_1_REG(base) (base.chg_base + 0x06)
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#define BATTERY_CHARGER_STATUS_MASK GENMASK(2, 0)
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enum {
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INHIBIT_CHARGE = 0,
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TRICKLE_CHARGE,
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PRE_CHARGE,
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FULLON_CHARGE,
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TAPER_CHARGE,
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TERMINATE_CHARGE,
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PAUSE_CHARGE,
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DISABLE_CHARGE,
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};
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#define CHGR_CHG_EN_STATUS_REG(base) (base.chg_base + 0x07)
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#define CHARGING_DISABLED_FROM_BOOST_BIT BIT(6)
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#define CHARGER_VBAT_STATUS_REG(base) (base.chg_base + 0x08)
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#define BAT_OV_BIT BIT(7)
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#define BATTERY_TEMP_STATUS_REG(base) (base.batif_base + 0x0C)
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#define BAT_TEMP_STATUS_TOO_HOT_AFP_BIT BIT(5)
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#define BAT_TEMP_STATUS_TOO_HOT_BIT BIT(4)
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#define BAT_TEMP_STATUS_HOT_SOFT_BIT BIT(3)
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#define BAT_TEMP_STATUS_COLD_SOFT_BIT BIT(2)
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#define BAT_TEMP_STATUS_TOO_COLD_BIT BIT(1)
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#define BAT_TEMP_STATUS_TOO_COLD_AFP_BIT BIT(0)
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#define CHARGING_ENABLE_CMD_REG(base) (base.chg_base + 0x46)
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#define CHARGING_ENABLE_CMD_BIT BIT(0)
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#define CHARGING_PAUSE_CMD_BIT BIT(4)
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#define CHGR_FAST_CHARGE_CURRENT_CFG_REG(base) (base.chg_base + 0x54)
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#define CHGR_FLOAT_VOLTAGE_CFG_REG(base) (base.chg_base + 0x58)
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#define CHGR_TERM_CFG_REG(base) (base.chg_base + 0x60)
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#define CHGR_ITERM_USE_ANALOG_BIT BIT(3)
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#define CHGR_ADC_ITERM_UP_THD_MSB_REG(base) (base.chg_base + 0x64)
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#define CHGR_ADC_ITERM_UP_THD_LSB_REG(base) (base.chg_base + 0x65)
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#define CHGR_ADC_ITERM_LO_THD_MSB_REG(base) (base.chg_base + 0x66)
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#define CHGR_ADC_ITERM_LO_THD_LSB_REG(base) (base.chg_base + 0x67)
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#define CHGR_RECHG_CFG_REG(base) (base.chg_base + 0x70)
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#define RECHG_MASK GENMASK(7, 6)
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#define VBAT_BASED_RECHG_BIT BIT(7)
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#define SOC_BASED_RECHG_BIT GENMASK(7, 6)
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#define NO_OF_SAMPLE_FOR_RCHG GENMASK(1, 0)
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#define CHGR_ADC_RECHARGE_THRESHOLD_MSB_REG(base) (base.chg_base + 0x72)
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#define CHARGE_RCHG_SOC_THRESHOLD_CFG_REG(base) (base.chg_base + 0x74)
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#define CHGR_INHIBIT_REG(base) (base.chg_base + 0x78)
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#define CHGR_INHIBIT_BIT BIT(7)
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#define CHGR_INHIBIT_THRESHOLD_CFG_REG(base) (base.chg_base + 0x7A)
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#define CHGR_QG_SOC_REG(base) (base.chg_base + 0x84)
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#define CHGR_QG_SOC_UPDATE_REG(base) (base.chg_base + 0x85)
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#define SOC_UPDATE_PCT_BIT BIT(0)
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#define CHGR_FAST_CHARGE_SAFETY_TIMER_CFG_REG(base) (base.chg_base + 0x90)
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#define FAST_CHARGE_SAFETY_TIMER_EN_BIT BIT(3)
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#define FAST_CHARGE_SAFETY_TIMER_MASK GENMASK(1, 0)
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#define FAST_CHARGE_SAFETY_TIMER_192_MIN 0x0
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#define FAST_CHARGE_SAFETY_TIMER_384_MIN 0x1
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#define FAST_CHARGE_SAFETY_TIMER_768_MIN 0x2
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#define FAST_CHARGE_SAFETY_TIMER_1536_MIN 0x3
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/********************************
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* DCDC Peripheral Registers *
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********************************/
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#define ICL_MAX_STATUS_REG(base) (base.dcdc_base + 0x06)
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#define ICL_STATUS_REG(base) (base.dcdc_base + 0x09)
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#define POWER_PATH_STATUS_REG(base) (base.dcdc_base + 0x0B)
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#define VALID_INPUT_POWER_SOURCE_STS_BIT BIT(7)
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#define USE_USBIN_BIT BIT(5)
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#define USBIN_SUSPEND_STS_BIT BIT(3)
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#define POWER_PATH_MASK GENMASK(1, 0)
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#define DCDC_CMD_OTG_REG(base) (base.dcdc_base + 0x50)
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#define OTG_EN_BIT BIT(0)
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#define DCDC_BST_VREG_SEL(base) (base.dcdc_base + 0x52)
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#define VBOOST_MASK GENMASK(1, 0)
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#define DCDC_OTG_CFG_REG(base) (base.dcdc_base + 0x56)
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#define OTG_EN_SRC_CFG_BIT BIT(0)
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#define DCDC_LDO_CFG_REG(base) (base.dcdc_base + 0x70)
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#define LDO_MODE_BIT BIT(0)
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#define CONCURRENT_MODE_CFG_REG(base) (base.dcdc_base + 0x50)
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#define CONCURRENT_MODE_EN_BIT BIT(0)
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/********************************
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* BATIF Peripheral Registers *
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********************************/
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/* BATIF Interrupt Bits */
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#define BSM_ACTIVE_RT_STS_BIT BIT(4)
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#define BAT_OV_RT_STS_BIT BIT(3)
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#define BAT_LOW_RT_STS_BIT BIT(2)
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#define BAT_THERM_OR_ID_MISSING_RT_STS_BIT BIT(1)
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#define BAT_TEMP_RT_STS_BIT BIT(0)
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#define SHIP_MODE_REG(base) (base.batif_base + 0x52)
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#define SHIP_MODE_EN_BIT BIT(0)
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#define CHGR_JEITA_HOT_THRESHOLD_REG(base) (base.batif_base + 0x84)
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#define CHGR_JEITA_WARM_THRESHOLD_REG(base) (base.batif_base + 0x86)
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#define CHGR_JEITA_COOL_THRESHOLD_REG(base) (base.batif_base + 0x88)
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#define CHGR_JEITA_COLD_THRESHOLD_REG(base) (base.batif_base + 0x8A)
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#define BATIF_PULLDOWN_VPH_CONTROL(base) (base.batif_base + 0x55)
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#define PULLDOWN_VPH_SW_EN_BIT BIT(1)
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#define PULLDOWN_VPH_HW_EN_BIT BIT(0)
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#define BATIF_PULLDOWN_VPH_SEL_MASK GENMASK(1, 0)
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/********************************
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* USBIN Peripheral Registers *
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********************************/
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/* USBIN Interrupt Bits */
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#define USBIN_SOURCE_CHANGE_RT_STS_BIT BIT(7)
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#define USBIN_ICL_CHANGE_RT_STS_BIT BIT(6)
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#define USBIN_GT_VT_RT_STS_BIT BIT(4)
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#define USBIN_OV_RT_STS_BIT BIT(3)
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#define USBIN_UV_RT_STS_BIT BIT(2)
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#define USBIN_COLLAPSE_RT_STS_BIT BIT(1)
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#define USBIN_PLUGIN_RT_STS_BIT BIT(0)
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#define USBIN_QC23_EN_REG(base) (base.usbin_base + 0x48)
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#define HVDCP_EN_BIT BIT(2)
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#define HVDCP_NO_AUTH_QC3_CFG_BIT BIT(0)
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#define USBIN_ICL_OPTIONS_REG(base) (base.usbin_base + 0x50)
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#define USBIN_MODE_CHG_BIT BIT(2)
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#define USB51_MODE_BIT BIT(1)
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#define CFG_USB3P0_SEL_BIT BIT(0)
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#define CMD_ICL_OVERRIDE_REG(base) (base.usbin_base + 0x51)
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#define ICL_OVERRIDE_BIT BIT(0)
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#define USBIN_CURRENT_LIMIT_CFG_REG(base) (base.usbin_base + 0x52)
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#define USBIN_INPUT_SUSPEND_REG(base) (base.usbin_base + 0x54)
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#define SUSPEND_ON_COLLAPSE_USBIN_BIT BIT(7)
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#define USBIN_SUSPEND_BIT BIT(0)
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#define USBIN_AICL_OPTIONS_CFG_REG(base) (base.usbin_base + 0x60)
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#define USBIN_AICL_EN_BIT BIT(7)
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#define USBIN_AICL_START_AT_MAX BIT(4)
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#define USBIN_AICL_STEP_TIMING_SEL_MASK GENMASK(3, 2)
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#define USBIN_IN_COLLAPSE_GF_SEL_MASK GENMASK(1, 0)
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#define USBIN_LV_AICL_THRESHOLD_REG(base) (base.usbin_base + 0x63)
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#define USB_CMD_PULLDOWN_REG(base) (base.usbin_base + 0x70)
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#define EN_PULLDOWN_USB_IN_BIT BIT(0)
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#define APSD_STATUS_REG(base) (base.usbin_base + 0x0a)
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#define HVDCP_CHECK_TIMEOUT_BIT BIT(6)
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#define SLOW_PLUGIN_TIMEOUT_BIT BIT(5)
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#define ENUMERATION_DONE_BIT BIT(4)
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#define VADP_CHANGE_DONE_AFTER_AUTH_BIT BIT(3)
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#define QC_AUTH_DONE_STATUS_BIT BIT(2)
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#define QC_CHARGER_BIT BIT(1)
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#define APSD_DTC_STATUS_DONE_BIT BIT(0)
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#define APSD_RESULT_STATUS_REG(base) (base.usbin_base + 0x0b)
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#define APSD_RESULT_STATUS_MASK GENMASK(6, 0)
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#define QC_3P0_BIT BIT(6)
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#define FLOAT_CHARGER_BIT BIT(4)
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#define DCP_CHARGER_BIT BIT(3)
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#define CDP_CHARGER_BIT BIT(2)
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#define OCP_CHARGER_BIT BIT(1)
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#define SDP_CHARGER_BIT BIT(0)
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#define CMD_APSD_REG(base) (base.usbin_base + 0x45)
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#define APSD_RERUN_BIT BIT(0)
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#define USBIN_APSD_EN_REG(base) (base.usbin_base + 0x44)
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#define BC1P2_SRC_DETECT_BIT BIT(7)
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#define CMD_HVDCP_REG(base) (base.usbin_base + 0x4a)
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#define SINGLE_INCREMENT_BIT BIT(5)
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#define SINGLE_DECREMENT_BIT BIT(4)
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#define FORCE_5V_BIT BIT(1)
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#define IDLE_BIT BIT(0)
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#define USB_APSD_CFG_REG(base) (base.usbin_base + 0x46)
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#define FLOAT_OPTIONS_MASK GENMASK(2, 0)
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#define FLOAT_DIS_CHGING_CFG_BIT BIT(2)
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#define SUSPEND_FLOAT_CFG_BIT BIT(1)
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#define FORCE_FLOAT_SDP_CFG_BIT BIT(0)
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/********************************
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* TYPEC Peripheral Registers *
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********************************/
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#define TYPE_C_SNK_STATUS_REG(base) (base.typec_base + 0x06)
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#define DETECTED_SRC_TYPE_MASK GENMASK(6, 0)
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#define SNK_DAM_500MA_BIT BIT(6)
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#define SNK_DAM_1500MA_BIT BIT(5)
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#define SNK_DAM_3000MA_BIT BIT(4)
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#define SNK_RP_STD_BIT BIT(3)
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#define SNK_RP_1P5_BIT BIT(2)
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#define SNK_RP_3P0_BIT BIT(1)
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#define SNK_RP_SHORT_BIT BIT(0)
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#define TYPE_C_SRC_STATUS_REG(base) (base.typec_base + 0x08)
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#define DETECTED_SNK_TYPE_MASK GENMASK(4, 0)
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#define SRC_HIGH_BATT_BIT BIT(5)
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#define SRC_DEBUG_ACCESS_BIT BIT(4)
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#define SRC_RD_OPEN_BIT BIT(3)
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#define SRC_RA_OPEN_BIT BIT(1)
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#define AUDIO_ACCESS_RA_RA_BIT BIT(0)
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#define TYPE_C_STATE_MACHINE_STATUS_REG(base) (base.typec_base + 0x09)
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#define TYPEC_ATTACH_DETACH_STATE_BIT BIT(5)
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#define TYPE_C_MISC_STATUS_REG(base) (base.typec_base + 0x0B)
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#define SNK_SRC_MODE_BIT BIT(6)
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#define TYPEC_VBUS_ERROR_STATUS_BIT BIT(4)
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#define TYPEC_TCCDEBOUNCE_DONE_STATUS_BIT BIT(3)
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#define CC_ORIENTATION_BIT BIT(1)
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#define CC_ATTACHED_BIT BIT(0)
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#define LEGACY_CABLE_STATUS_REG(base) (base.typec_base + 0x0D)
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#define TYPEC_LEGACY_CABLE_STATUS_BIT BIT(1)
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#define TYPEC_NONCOMP_LEGACY_CABLE_STATUS_BIT BIT(0)
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#define TYPEC_U_USB_STATUS_REG(base) (base.typec_base + 0x0F)
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#define U_USB_GROUND_NOVBUS_BIT BIT(6)
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#define U_USB_GROUND_BIT BIT(4)
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#define U_USB_FLOAT1_BIT BIT(2)
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#define U_USB_FLOAT2_BIT BIT(0)
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#define TYPE_C_MODE_CFG_REG(base) (base.typec_base + 0x44)
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#define TYPEC_TRY_MODE_MASK GENMASK(4, 3)
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#define EN_TRY_SNK_BIT BIT(4)
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#define EN_TRY_SRC_BIT BIT(3)
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#define TYPEC_POWER_ROLE_CMD_MASK GENMASK(2, 0)
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#define EN_SRC_ONLY_BIT BIT(2)
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#define EN_SNK_ONLY_BIT BIT(1)
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#define TYPEC_DISABLE_CMD_BIT BIT(0)
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#define DEBUG_ACCESS_SRC_CFG_REG(base) (base.typec_base + 0x4C)
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#define EN_UNORIENTED_DEBUG_ACCESS_SRC_BIT BIT(0)
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#define TYPE_C_EXIT_STATE_CFG_REG(base) (base.typec_base + 0x50)
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#define BYPASS_VSAFE0V_DURING_ROLE_SWAP_BIT BIT(3)
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#define SEL_SRC_UPPER_REF_BIT BIT(2)
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#define EXIT_SNK_BASED_ON_CC_BIT BIT(0)
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#define TYPE_C_CURRSRC_CFG_REG(base) (base.typec_base + 0x52)
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#define TYPEC_SRC_RP_SEL_MASK GENMASK(1, 0)
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enum {
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TYPEC_SRC_RP_STD,
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TYPEC_SRC_RP_1P5A,
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TYPEC_SRC_RP_3A,
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TYPEC_SRC_RP_3A_DUPLICATE,
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TYPEC_SRC_RP_MAX_ELEMENTS
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};
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#define TYPE_C_INTERRUPT_EN_CFG_1_REG(base) (base.typec_base + 0x5E)
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#define TYPEC_LEGACY_CABLE_INT_EN_BIT BIT(7)
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#define TYPEC_NONCOMPLIANT_LEGACY_CABLE_INT_EN_BIT BIT(6)
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#define TYPEC_TRYSOURCE_DETECT_INT_EN_BIT BIT(5)
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#define TYPEC_TRYSINK_DETECT_INT_EN_BIT BIT(4)
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#define TYPEC_CCOUT_DETACH_INT_EN_BIT BIT(3)
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#define TYPEC_CCOUT_ATTACH_INT_EN_BIT BIT(2)
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#define TYPEC_VBUS_DEASSERT_INT_EN_BIT BIT(1)
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#define TYPEC_VBUS_ASSERT_INT_EN_BIT BIT(0)
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#define TYPE_C_INTERRUPT_EN_CFG_2_REG(base) (base.typec_base + 0x60)
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#define TYPEC_SRC_BATT_HPWR_INT_EN_BIT BIT(6)
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#define MICRO_USB_STATE_CHANGE_INT_EN_BIT BIT(5)
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#define TYPEC_STATE_MACHINE_CHANGE_INT_EN_BIT BIT(4)
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#define TYPEC_DEBUG_ACCESS_DETECT_INT_EN_BIT BIT(3)
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#define TYPEC_WATER_DETECTION_INT_EN_BIT BIT(2)
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#define TYPEC_VBUS_ERROR_INT_EN_BIT BIT(1)
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#define TYPEC_DEBOUNCE_DONE_INT_EN_BIT BIT(0)
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#define TYPEC_U_USB_CFG_REG(base) (base.typec_base + 0x70)
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#define EN_MICRO_USB_MODE_BIT BIT(0)
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/********************************
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* MISC Peripheral Registers *
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********************************/
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#define TEMP_RANGE_STATUS_REG(base) (base.misc_base + 0x08)
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#define THERM_REG_ACTIVE_BIT BIT(6)
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#define TLIM_BIT BIT(5)
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#define TEMP_RANGE_MASK GENMASK(4, 1)
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#define ALERT_LEVEL_BIT BIT(4)
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#define TEMP_ABOVE_RANGE_BIT BIT(3)
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#define TEMP_WITHIN_RANGE_BIT BIT(2)
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#define TEMP_BELOW_RANGE_BIT BIT(1)
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#define THERMREG_DISABLED_BIT BIT(0)
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#define DIE_TEMP_STATUS_REG(base) (base.misc_base + 0x09)
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#define DIE_TEMP_MASK GENMASK(3, 0)
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#define DIE_TEMP_SHDN_BIT BIT(3)
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#define DIE_TEMP_RST_BIT BIT(2)
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#define DIE_TEMP_UB_BIT BIT(1)
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#define DIE_TEMP_LB_BIT BIT(0)
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#define AICL_STATUS_REG(base) (base.misc_base + 0x06)
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#define SOFT_ILIMIT_BIT BIT(6)
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#define AICL_DONE_BIT BIT(0)
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#define AICL_CMD_REG(base) (base.misc_base + 0x50)
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#define RESTART_AICL_BIT BIT(1)
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#define RERUN_AICL_BIT BIT(0)
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#define MISC_SMB_EN_CMD_REG(base) (base.misc_base + 0x4C)
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#define SMB_EN_OVERRIDE_VALUE_BIT BIT(0)
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#define SMB_EN_OVERRIDE_BIT BIT(1)
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#define MISC_AICL_RERUN_CFG_REG(base) (base.misc_base + 0x54)
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#define USBIN_AICL_PERIODIC_RERUN_EN_BIT BIT(5)
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#define USBIN_AICL_RERUN_TIME_MASK GENMASK(1, 0)
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#define AICL_RERUN_TIME_12S_VAL 0x01
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#define WD_CFG_REG(base) (base.misc_base + 0x58)
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#define BITE_WDOG_DISABLE_CHARGING_CFG_BIT BIT(7)
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#define BARK_WDOG_INT_EN_BIT BIT(4)
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#define WDOG_TIMER_EN_ON_PLUGIN_BIT BIT(1)
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#define WDOG_TIMER_EN_BIT BIT(0)
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#define SNARL_BARK_BITE_WD_CFG_REG(base) (base.misc_base + 0x59)
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#define SNARL_WDOG_TIMEOUT_MASK GENMASK(2, 0)
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#define SNARL_WDOG_TMOUT_62P5MS 0x0
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#define SNARL_WDOG_TMOUT_1S 0x4
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#define SNARL_WDOG_TMOUT_8S 0x7
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#define BARK_WDOG_TIMEOUT_MASK GENMASK(5, 4)
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#define BARK_WDOG_TIMEOUT_SHIFT 4
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#define BITE_WDOG_TIMEOUT_MASK GENMASK(7, 6)
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#define BITE_WDOG_TIMEOUT_8S 0x3
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#define BITE_WDOG_TIMEOUT_SHIFT 6
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#define MIN_WD_BARK_TIME 16
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#define BARK_BITE_WDOG_PET_REG(base) (base.misc_base + 0x5A)
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#define BARK_BITE_WDOG_PET_BIT BIT(0)
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/********************************
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* BOOST Peripheral Registers *
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********************************/
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#define BOOST_BST_STATUS_REG(base) (base.boost_base + 0x0D)
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#define BOOST_SOFTSTART_DONE_BIT BIT(3)
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#define BOOST_BST_EN_REG(base) (base.boost_base + 0x46)
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#define DCIN_BST_EN_BIT BIT(1)
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#endif /* __SMBLITE_CHARGER_REG_H */
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