232 lines
6.0 KiB
C
Executable File
232 lines
6.0 KiB
C
Executable File
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2016, 2019-2021, Linux Foundation. All rights reserved.
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* All rights reserved.
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* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include "phy-qcom-ufs-qrbtc-sdm845.h"
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#define UFS_PHY_NAME "ufs_phy_qrbtc_sdm845"
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/* TCSR_SOC_EMULATION_TYPE register value for type of RUMI platform */
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#define RUMI_PLATFORM_TYPE_VU19P 0xA0000001
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#define RUMI_PLATFORM_TYPE_VU440P 0xB0000001
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static
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int ufs_qcom_phy_qrbtc_sdm845_phy_calibrate(struct phy *generic_phy)
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{
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int err;
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int tbl_size_A, tbl_size_B;
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struct ufs_qcom_phy_calibration *tbl_A, *tbl_B;
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struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
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bool is_rate_B;
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tbl_A = phy_cal_table_rate_A;
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tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A);
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tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B);
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tbl_B = phy_cal_table_rate_B;
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is_rate_B = (ufs_qcom_phy->mode == PHY_MODE_UFS_HS_B) ? true : false;
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err = ufs_qcom_phy_calibrate(ufs_qcom_phy,
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tbl_A, tbl_size_A,
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tbl_B, tbl_size_B,
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is_rate_B);
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if (err)
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dev_err(ufs_qcom_phy->dev,
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"%s: ufs_qcom_phy_calibrate() failed %d\n",
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__func__, err);
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return err;
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}
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static int
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ufs_qcom_phy_qrbtc_sdm845_is_pcs_ready(struct ufs_qcom_phy *phy_common)
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{
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int err = 0;
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u32 val;
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/*
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* New RH132 UFS Card which suports Gear-1 RATE-B
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* does not use QSERDES_COM_RESET_SM
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* For VU19P RUMI Platform Value = 0xA0000001
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* For VU440P RUMI Platform Value = 0xB0000001
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*
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* New RH132 UFS Card available only for VU440P
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*/
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if (phy_common->soc_emulation_type == RUMI_PLATFORM_TYPE_VU440P)
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return 0;
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/*
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* The value we are polling for is 0x3D which represents the
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* following masks:
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* RESET_SM field: 0x5
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* RESTRIMDONE bit: BIT(3)
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* PLLLOCK bit: BIT(4)
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* READY bit: BIT(5)
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*/
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#define QSERDES_COM_RESET_SM_REG_POLL_VAL 0x3D
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err = readl_poll_timeout(phy_common->mmio + QSERDES_COM_RESET_SM,
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val, (val == QSERDES_COM_RESET_SM_REG_POLL_VAL), 10, 1000000);
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if (err)
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dev_err(phy_common->dev, "%s: poll for pcs failed err = %d\n",
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__func__, err);
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return err;
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}
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static void ufs_qcom_phy_qrbtc_sdm845_start_serdes(struct ufs_qcom_phy *phy)
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{
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u32 temp;
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writel_relaxed(0x01, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
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temp = readl_relaxed(phy->mmio + UFS_PHY_PHY_START);
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temp |= 0x1;
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writel_relaxed(temp, phy->mmio + UFS_PHY_PHY_START);
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/* Ensure register value is committed */
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mb();
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}
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/*
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* Dynamically detect whether RH132 card based sequences to be used or
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* legacy UFS card sequences to be used via reading TCSR_SOC_EMULATION_TYPE
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*/
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static int ufs_qcom_parse_soc_emulation_type(struct ufs_qcom_phy *phy_common)
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{
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struct device *dev = phy_common->dev;
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struct device_node *np = dev->of_node;
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void __iomem *reg_base = NULL;
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u32 soc_emulation_type_addr = 0;
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u32 soc_emulation_type_bits = 0;
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int ret = 0;
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if (!of_property_read_u32(np, "qcom,soc_emulation_type_addr", &soc_emulation_type_addr)) {
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ret = of_property_read_u32(np, "qcom,soc_emulation_type_bits",
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&soc_emulation_type_bits);
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if (ret < 0) {
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dev_err(phy_common->dev, "can't get soc_emulation_type bits\n");
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return -EINVAL;
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}
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reg_base = ioremap(soc_emulation_type_addr, soc_emulation_type_bits);
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if (!reg_base) {
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dev_err(phy_common->dev, "can't map soc_emulation_type addr\n");
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return -EINVAL;
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}
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phy_common->soc_emulation_type = readl_relaxed(reg_base);
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dev_dbg(phy_common->dev, "soc_emulation_type value [0x%x]\n",
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phy_common->soc_emulation_type);
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iounmap(reg_base);
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}
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return ret;
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}
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static int ufs_qcom_phy_qrbtc_sdm845_init(struct phy *generic_phy)
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{
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struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
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int ret;
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ret = ufs_qcom_parse_soc_emulation_type(phy_common);
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if (ret)
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dev_dbg(phy_common->dev, "unable to get soc_emulation_type %d\n", ret);
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ret = ufs_qcom_phy_get_reset(phy_common);
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if (ret)
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dev_err(phy_common->dev, "Failed to get reset control %d\n", ret);
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return ret;
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}
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static int ufs_qcom_phy_qrbtc_sdm845_exit(struct phy *generic_phy)
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{
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return 0;
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}
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static
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int ufs_qcom_phy_qrbtc_sdm845_set_mode(struct phy *generic_phy,
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enum phy_mode mode, int submode)
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{
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struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
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phy_common->mode = PHY_MODE_INVALID;
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if (mode > 0)
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phy_common->mode = mode;
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phy_common->submode = submode;
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return 0;
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}
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static const struct phy_ops ufs_qcom_phy_qrbtc_sdm845_phy_ops = {
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.init = ufs_qcom_phy_qrbtc_sdm845_init,
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.exit = ufs_qcom_phy_qrbtc_sdm845_exit,
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.set_mode = ufs_qcom_phy_qrbtc_sdm845_set_mode,
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.calibrate = ufs_qcom_phy_qrbtc_sdm845_phy_calibrate,
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.owner = THIS_MODULE,
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};
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static struct ufs_qcom_phy_specific_ops phy_qrbtc_sdm845_ops = {
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.start_serdes = ufs_qcom_phy_qrbtc_sdm845_start_serdes,
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.is_physical_coding_sublayer_ready =
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ufs_qcom_phy_qrbtc_sdm845_is_pcs_ready,
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};
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static int ufs_qcom_phy_qrbtc_sdm845_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct phy *generic_phy;
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struct ufs_qcom_phy_qrbtc_sdm845 *phy;
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int err = 0;
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phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
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if (!phy) {
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err = -ENOMEM;
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goto out;
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}
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generic_phy = ufs_qcom_phy_generic_probe(pdev, &phy->common_cfg,
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&ufs_qcom_phy_qrbtc_sdm845_phy_ops, &phy_qrbtc_sdm845_ops);
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if (!generic_phy) {
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dev_err(dev, "%s: ufs_qcom_phy_generic_probe() failed\n",
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__func__);
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err = -EIO;
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goto out;
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}
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phy_set_drvdata(generic_phy, phy);
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strscpy(phy->common_cfg.name, UFS_PHY_NAME,
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sizeof(phy->common_cfg.name));
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out:
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return err;
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}
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static const struct of_device_id ufs_qcom_phy_qrbtc_sdm845_of_match[] = {
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{.compatible = "qcom,ufs-phy-qrbtc-sdm845"},
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{},
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};
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MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qrbtc_sdm845_of_match);
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static struct platform_driver ufs_qcom_phy_qrbtc_sdm845_driver = {
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.probe = ufs_qcom_phy_qrbtc_sdm845_probe,
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.driver = {
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.of_match_table = ufs_qcom_phy_qrbtc_sdm845_of_match,
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.name = "ufs_qcom_phy_qrbtc_sdm845",
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},
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};
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module_platform_driver(ufs_qcom_phy_qrbtc_sdm845_driver);
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MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QRBTC SDM845");
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MODULE_LICENSE("GPL");
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