304 lines
14 KiB
C
Executable File
304 lines
14 KiB
C
Executable File
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef UFS_QCOM_PHY_QMP_V4_H_
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#define UFS_QCOM_PHY_QMP_V4_H_
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#include "phy-qcom-ufs-i.h"
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/* QCOM UFS PHY control registers */
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#define COM_BASE 0x000
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#define COM_SIZE 0x2000
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#define PHY_BASE 0x400
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#define PHY_SIZE 0x258
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#define PCS2_BASE 0x800
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#define PCS2_SIZE 0x6C
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#define TX_BASE(n) (0x1000 + (0x800 * n))
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#define TX_SIZE 0x134
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#define RX_BASE(n) (0x1200 + (0x800 * n))
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#define RX_SIZE 0x3D8
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#define COM_OFF(x) (COM_BASE + x)
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#define PHY_OFF(x) (PHY_BASE + x)
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#define TX_OFF(n, x) (TX_BASE(n) + x)
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#define RX_OFF(n, x) (RX_BASE(n) + x)
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#define UFS_PHY_SW_RESET PHY_OFF(0x8)
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#define UFS_PHY_POWER_DOWN_CONTROL PHY_OFF(0x4)
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#define UFS_PHY_TX_LARGE_AMP_DRV_LVL PHY_OFF(0x30)
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#define UFS_PHY_RX_SIGDET_CTRL2 PHY_OFF(0x18C)
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#define QSERDES_COM_CMN_IPTRIM COM_OFF(0x100)
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#define QSERDES_COM_SYSCLK_EN_SEL COM_OFF(0x110)
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#define QSERDES_COM_CMN_CONFIG_1 COM_OFF(0x174)
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#define QSERDES_COM_HSCLK_SEL_1 COM_OFF(0x3C)
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#define QSERDES_COM_HSCLK_HS_SWITCH_SEL_1 COM_OFF(0x9C)
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#define QSERDES_COM_LOCK_CMP_EN COM_OFF(0x120)
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#define QSERDES_COM_PLL_IVCO COM_OFF(0xF4)
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#define QSERDES_COM_PLL_IVCO_MODE1 COM_OFF(0xF8)
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#define QSERDES_COM_CMN_IETRIM COM_OFF(0xFC)
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#define QSERDES_COM_VCO_TUNE_INITVAL2 COM_OFF(0x148)
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#define QSERDES_COM_DEC_START_MODE0 COM_OFF(0x88)
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#define QSERDES_COM_CP_CTRL_MODE0 COM_OFF(0x70)
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#define QSERDES_COM_PLL_RCTRL_MODE0 COM_OFF(0x74)
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#define QSERDES_COM_PLL_CCTRL_MODE0 COM_OFF(0x78)
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#define QSERDES_COM_LOCK_CMP1_MODE0 COM_OFF(0x80)
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#define QSERDES_COM_LOCK_CMP2_MODE0 COM_OFF(0x84)
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#define QSERDES_COM_DEC_START_MODE1 COM_OFF(0x28)
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#define QSERDES_COM_CP_CTRL_MODE1 COM_OFF(0x10)
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#define QSERDES_COM_PLL_RCTRL_MODE1 COM_OFF(0x14)
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#define QSERDES_COM_PLL_CCTRL_MODE1 COM_OFF(0x18)
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#define QSERDES_COM_LOCK_CMP1_MODE1 COM_OFF(0x20)
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#define QSERDES_COM_LOCK_CMP2_MODE1 COM_OFF(0x24)
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#define QSERDES_COM_VCO_TUNE_MAP COM_OFF(0x140)
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#define QSERDES_TX0_TX_FR_DCC_CTRL TX_OFF(0, 0x108)
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#define QSERDES_TX0_LANE_MODE_1 TX_OFF(0, 0x7C)
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#define QSERDES_TX0_RES_CODE_LANE_OFFSET_TX TX_OFF(0, 0x30)
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#define QSERDES_TX0_RES_CODE_LANE_OFFSET_RX TX_OFF(0, 0x34)
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#define QSERDES_RX0_UCDR_SO_SATURATION RX_OFF(0, 0x28)
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#define QSERDES_RX0_UCDR_PI_CTRL1 RX_OFF(0, 0x58)
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#define QSERDES_RX0_RX_TERM_BW_CTRL0 RX_OFF(0, 0xC4)
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#define QSERDES_RX0_RX_MODE_RATE_0_1_B0 RX_OFF(0, 0x208)
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#define QSERDES_RX0_RX_MODE_RATE_0_1_B1 RX_OFF(0, 0x20C)
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#define QSERDES_RX0_RX_MODE_RATE_0_1_B2 RX_OFF(0, 0x210)
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#define QSERDES_RX0_RX_MODE_RATE_0_1_B3 RX_OFF(0, 0x214)
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#define QSERDES_RX0_RX_MODE_RATE_0_1_B4 RX_OFF(0, 0x218)
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#define QSERDES_RX0_RX_MODE_RATE_0_1_B6 RX_OFF(0, 0x220)
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#define QSERDES_RX0_RX_MODE_RATE2_B3 RX_OFF(0, 0x238)
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#define QSERDES_RX0_RX_MODE_RATE2_B6 RX_OFF(0, 0x244)
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#define QSERDES_RX0_RX_MODE_RATE3_B3 RX_OFF(0, 0x25C)
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#define QSERDES_RX0_RX_MODE_RATE3_B4 RX_OFF(0, 0x260)
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#define QSERDES_RX0_RX_MODE_RATE3_B5 RX_OFF(0, 0x264)
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#define QSERDES_RX0_RX_MODE_RATE3_B8 RX_OFF(0, 0x270)
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#define QSERDES_RX0_RX_MODE_RATE4_B0 RX_OFF(0, 0x274)
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#define QSERDES_RX0_RX_MODE_RATE4_B1 RX_OFF(0, 0x278)
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#define QSERDES_RX0_RX_MODE_RATE4_B2 RX_OFF(0, 0x27C)
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#define QSERDES_RX0_RX_MODE_RATE4_B3 RX_OFF(0, 0x280)
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#define QSERDES_RX0_RX_MODE_RATE4_B4 RX_OFF(0, 0x284)
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#define QSERDES_RX0_DLL0_FTUNE_CTRL RX_OFF(0, 0x2F8)
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#define QSERDES_RX0_RX_INTERFACE_MODE RX_OFF(0, 0x1E0)
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#define QSERDES_RX0_UCDR_FO_GAIN_RATE2 RX_OFF(0, 0xD4)
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#define QSERDES_RX0_UCDR_FO_GAIN_RATE4 RX_OFF(0, 0xDC)
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#define QSERDES_RX0_UCDR_SO_GAIN_RATE4 RX_OFF(0, 0xF0)
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#define QSERDES_RX0_UCDR_PI_CONTROLS RX_OFF(0, 0xF4)
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#define QSERDES_RX0_UCDR_FASTLOCK_COUNT_HIGH_RATE4 RX_OFF(0, 0x54)
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#define QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN_RATE4 RX_OFF(0, 0x10)
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#define QSERDES_RX0_UCDR_FASTLOCK_SO_GAIN_RATE4 RX_OFF(0, 0x24)
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#define QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1 RX_OFF(0, 0x1BC)
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#define QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL3 RX_OFF(0, 0x1C4)
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#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4 RX_OFF(0, 0x1AC)
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#define QSERDES_RX0_VGA_CAL_MAN_VAL RX_OFF(0, 0x178)
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#define QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN_RATE4 RX_OFF(1, 0x10)
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#define QSERDES_RX1_UCDR_FASTLOCK_SO_GAIN_RATE4 RX_OFF(1, 0x24)
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#define QSERDES_RX1_UCDR_SO_SATURATION RX_OFF(1, 0x28)
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#define QSERDES_RX1_UCDR_SO_GAIN_RATE4 RX_OFF(1, 0xF0)
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#define QSERDES_RX1_UCDR_PI_CTRL1 RX_OFF(1, 0x58)
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#define QSERDES_RX1_UCDR_FASTLOCK_COUNT_HIGH_RATE4 RX_OFF(1, 0x54)
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#define QSERDES_RX1_RX_TERM_BW_CTRL0 RX_OFF(1, 0xC4)
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#define QSERDES_RX1_UCDR_PI_CONTROLS RX_OFF(1, 0xF4)
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#define QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1 RX_OFF(1, 0x1BC)
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#define QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4 RX_OFF(1, 0x1AC)
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#define QSERDES_RX1_RX_OFFSET_ADAPTOR_CNTRL3 RX_OFF(1, 0x1C4)
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#define QSERDES_RX1_RX_MODE_RATE_0_1_B0 RX_OFF(1, 0x208)
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#define QSERDES_RX1_RX_MODE_RATE_0_1_B2 RX_OFF(1, 0x210)
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#define QSERDES_RX1_RX_MODE_RATE_0_1_B1 RX_OFF(1, 0x20C)
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#define QSERDES_RX1_RX_MODE_RATE_0_1_B3 RX_OFF(1, 0x214)
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#define QSERDES_RX1_RX_MODE_RATE_0_1_B4 RX_OFF(1, 0x218)
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#define QSERDES_RX1_RX_MODE_RATE_0_1_B6 RX_OFF(1, 0x220)
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#define QSERDES_RX1_RX_MODE_RATE2_B3 RX_OFF(1, 0x238)
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#define QSERDES_RX1_RX_MODE_RATE2_B6 RX_OFF(1, 0x244)
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#define QSERDES_RX1_RX_MODE_RATE3_B3 RX_OFF(1, 0x25C)
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#define QSERDES_RX1_RX_MODE_RATE3_B4 RX_OFF(1, 0x260)
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#define QSERDES_RX1_RX_MODE_RATE3_B5 RX_OFF(1, 0x264)
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#define QSERDES_RX1_RX_MODE_RATE3_B8 RX_OFF(1, 0x270)
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#define QSERDES_RX1_RX_MODE_RATE4_B0 RX_OFF(1, 0x274)
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#define QSERDES_RX1_RX_MODE_RATE4_B1 RX_OFF(1, 0x278)
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#define QSERDES_RX1_RX_MODE_RATE4_B2 RX_OFF(1, 0x27C)
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#define QSERDES_RX1_RX_MODE_RATE4_B3 RX_OFF(1, 0x280)
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#define QSERDES_RX1_RX_MODE_RATE4_B4 RX_OFF(1, 0x284)
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#define QSERDES_RX1_DLL0_FTUNE_CTRL RX_OFF(1, 0x2F8)
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#define QSERDES_RX1_RX_INTERFACE_MODE RX_OFF(1, 0x1E0)
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#define QSERDES_RX1_UCDR_FO_GAIN_RATE2 RX_OFF(1, 0xD4)
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#define QSERDES_RX1_UCDR_FO_GAIN_RATE4 RX_OFF(1, 0xDC)
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#define QSERDES_RX1_VGA_CAL_MAN_VAL RX_OFF(1, 0x178)
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#define QSERDES_TX1_RES_CODE_LANE_OFFSET_RX TX_OFF(1, 0x34)
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#define QSERDES_TX1_LANE_MODE_1 TX_OFF(1, 0x7C)
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#define QSERDES_TX1_TX_FR_DCC_CTRL TX_OFF(1, 0x108)
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#define QSERDES_TX1_RES_CODE_LANE_OFFSET_TX TX_OFF(1, 0x30)
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#define UFS_PHY_MULTI_LANE_CTRL1 PHY_OFF(0x1FC)
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#define UFS_PHY_TX_MID_TERM_CTRL1 PHY_OFF(0x1F4)
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#define UFS_PHY_PCS_CTRL1 PHY_OFF(0x20)
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#define UFS_PHY_PLL_CNTL PHY_OFF(0x2C)
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#define UFS_PHY_TX_HSGEAR_CAPABILITY PHY_OFF(0x74)
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#define UFS_PHY_RX_HSGEAR_CAPABILITY PHY_OFF(0xBC)
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#define UFS_PHY_RX_HS_G5_SYNC_LENGTH_CAPABILITY PHY_OFF(0x12C)
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#define UFS_PHY_RX_HSG5_SYNC_WAIT_TIME PHY_OFF(0x220)
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#define UFS_PHY_PHY_START PHY_OFF(0x0)
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#define UFS_PHY_PCS_READY_STATUS PHY_OFF(0x1A8)
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#define UFS_PHY_LINECFG_DISABLE PHY_OFF(0x17C)
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#define UFS_PHY_RX_LINECFG_DISABLE_BIT BIT(1)
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#define QSERDES_RX_INTERFACE_MODE_CLOCK_EDGE_BIT BIT(6)
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/*
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* This structure represents the v4 specific phy.
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* common_cfg MUST remain the first field in this structure
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* in case extra fields are added. This way, when calling
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* get_ufs_qcom_phy() of generic phy, we can extract the
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* common phy structure (struct ufs_qcom_phy) out of it
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* regardless of the relevant specific phy.
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*/
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struct ufs_qcom_phy_qmp_v4 {
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struct ufs_qcom_phy common_cfg;
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};
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static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_g5[] = {
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UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x1),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0xD9),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_CONFIG_1, 0x16),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_SEL_1, 0x11),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_EN, 0x01),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IVCO, 0x1F),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IVCO_MODE1, 0x1F),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_IETRIM, 0x0A),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_IPTRIM, 0x17),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x04),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE0, 0x41),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE0, 0x06),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE0, 0x18),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE0, 0x14),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0x7F),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x06),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE1, 0x4C),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE1, 0x06),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE1, 0x18),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE1, 0x14),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x99),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x07),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_LANE_MODE_1, 0x01),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x07),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_RES_CODE_LANE_OFFSET_RX, 0x0E),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FO_GAIN_RATE2, 0x0C),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FO_GAIN_RATE4, 0x0C),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_GAIN_RATE4, 0x04),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_PI_CONTROLS, 0x07),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL3, 0x0E),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1C),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_VGA_CAL_MAN_VAL, 0x3E),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x0F),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE_0_1_B0, 0xCE),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE_0_1_B1, 0xCE),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE_0_1_B2, 0x18),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE_0_1_B3, 0x1A),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE_0_1_B4, 0x0F),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE_0_1_B6, 0x60),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE2_B3, 0x9E),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE2_B6, 0x60),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE3_B3, 0x9E),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE3_B4, 0x0E),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE3_B5, 0x36),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE3_B8, 0x02),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE4_B0, 0x24),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE4_B1, 0x24),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE4_B2, 0x20),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE4_B3, 0xB9),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE4_B4, 0x4F),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_SATURATION, 0x1F),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_PI_CTRL1, 0x94),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_TERM_BW_CTRL0, 0xFA),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_DLL0_FTUNE_CTRL, 0x30),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_LANE_MODE_1, 0x01),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_RES_CODE_LANE_OFFSET_TX, 0x07),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_RES_CODE_LANE_OFFSET_RX, 0x0E),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FO_GAIN_RATE2, 0x0C),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FO_GAIN_RATE4, 0x0C),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_GAIN_RATE4, 0x04),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_PI_CONTROLS, 0x7),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_OFFSET_ADAPTOR_CNTRL3, 0x0E),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x2),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1C),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_VGA_CAL_MAN_VAL, 0x3E),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4, 0x0F),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE_0_1_B0, 0xCE),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE_0_1_B1, 0xCE),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE_0_1_B2, 0x18),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE_0_1_B3, 0x1A),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE_0_1_B4, 0x0F),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE_0_1_B6, 0x60),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE2_B3, 0x9E),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE2_B6, 0x60),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE3_B3, 0x9E),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE3_B4, 0x0E),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE3_B5, 0x36),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE3_B8, 0x02),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE4_B0, 0x24),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE4_B1, 0x24),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE4_B2, 0x20),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE4_B3, 0xB9),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE4_B4, 0x4F),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_SATURATION, 0x1F),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_PI_CTRL1, 0x94),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_TERM_BW_CTRL0, 0xFA),
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_DLL0_FTUNE_CTRL, 0x30),
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UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_MULTI_LANE_CTRL1, 0x00),
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UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_MID_TERM_CTRL1, 0x43),
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UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PCS_CTRL1, 0xC0),
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UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PLL_CNTL, 0x33),
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UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_HSGEAR_CAPABILITY, 0x05),
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UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HSGEAR_CAPABILITY, 0x05),
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UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0F),
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UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x68),
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UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4D),
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UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HSG5_SYNC_WAIT_TIME, 0x9E),
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};
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static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_g4[] = {
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UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_HSGEAR_CAPABILITY, 0x04),
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UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HSGEAR_CAPABILITY, 0x04),
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};
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static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane[] = {
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UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_MULTI_LANE_CTRL1, 0x02),
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};
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static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = {
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UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x04),
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UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PCS_CTRL1, 0xC1),
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};
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#endif
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