145 lines
3.1 KiB
C
Executable File
145 lines
3.1 KiB
C
Executable File
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2013, The Linux Foundation. All rights reserved.
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* Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/bitops.h>
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#include <linux/export.h>
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#include <linux/regmap.h>
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#include <linux/reset-controller.h>
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#include <linux/delay.h>
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#include <linux/pm_runtime.h>
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#include "reset.h"
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#include "trace.h"
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static int
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qcom_reset_runtime_get(struct qcom_reset_controller *rst)
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{
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int ret;
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if (pm_runtime_enabled(rst->dev)) {
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ret = pm_runtime_resume_and_get(rst->dev);
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if (ret < 0) {
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WARN(1, "ret=%d\n", ret);
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return ret;
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}
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}
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return 0;
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}
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static void
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qcom_reset_runtime_put(struct qcom_reset_controller *rst)
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{
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int ret;
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if (pm_runtime_enabled(rst->dev)) {
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ret = pm_runtime_put_sync(rst->dev);
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if (ret < 0)
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WARN(1, "ret=%d\n", ret);
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}
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}
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static void qcom_reset_delay(const struct qcom_reset_map *map)
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{
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/*
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* XO div-4 is commonly used for the reset demets, so by default allow
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* enough time for 4 demet cycles at 1.2MHz.
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*/
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fsleep(map->udelay ?: 4);
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}
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static int qcom_reset(struct reset_controller_dev *rcdev, unsigned long id)
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{
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struct qcom_reset_controller *rst = to_qcom_reset_controller(rcdev);
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rcdev->ops->assert(rcdev, id);
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qcom_reset_delay(&rst->reset_map[id]);
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rcdev->ops->deassert(rcdev, id);
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return 0;
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}
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static int qcom_reset_set_assert(struct reset_controller_dev *rcdev,
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unsigned long id, bool assert)
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{
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struct qcom_reset_controller *rst;
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const struct qcom_reset_map *map;
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u32 mask, val;
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int ret = 0;
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rst = to_qcom_reset_controller(rcdev);
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map = &rst->reset_map[id];
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mask = map->bitmask ? map->bitmask : BIT(map->bit);
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ret = qcom_reset_runtime_get(rst);
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if (ret < 0)
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return ret;
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trace_clk_reset(rst, id, assert);
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ret = regmap_update_bits(rst->regmap, map->reg, mask, assert ? mask : 0);
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if (ret)
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goto err;
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/* Ensure the write is fully propagated to the register. */
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ret = regmap_read(rst->regmap, map->reg, &val);
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if (ret)
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goto err;
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/* Give demets a chance to propagate the signal. */
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qcom_reset_delay(map);
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err:
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qcom_reset_runtime_put(rst);
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return ret;
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}
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static int
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qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
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{
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return qcom_reset_set_assert(rcdev, id, true);
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}
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static int qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
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{
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return qcom_reset_set_assert(rcdev, id, false);
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}
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static int
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qcom_reset_status(struct reset_controller_dev *rcdev, unsigned long id)
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{
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struct qcom_reset_controller *rst;
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const struct qcom_reset_map *map;
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u32 mask, reg;
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int ret;
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rst = to_qcom_reset_controller(rcdev);
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map = &rst->reset_map[id];
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mask = map->bitmask ? map->bitmask : BIT(map->bit);
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ret = qcom_reset_runtime_get(rst);
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if (ret < 0)
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return ret;
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ret = regmap_read(rst->regmap, map->reg, ®);
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if (ret) {
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qcom_reset_runtime_put(rst);
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return ret;
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}
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qcom_reset_runtime_put(rst);
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return (reg & mask);
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}
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const struct reset_control_ops qcom_reset_ops = {
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.reset = qcom_reset,
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.assert = qcom_reset_assert,
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.deassert = qcom_reset_deassert,
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.status = qcom_reset_status,
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};
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EXPORT_SYMBOL_GPL(qcom_reset_ops);
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