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android_kernel_samsung_sm8750/drivers/clk/qcom/gcc-monaco.c
SaschaNes 94a2807785 add samsung opensource kernel
2025-08-12 22:16:57 +02:00

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,gcc-monaco.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "reset.h"
#include "vdd-level-monaco.h"
#include "clk-pm.h"
static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner);
static DEFINE_VDD_REGULATORS(vdd_mx, VDD_NUM, 1, vdd_corner);
static struct clk_vdd_class *gcc_monaco_regulators[] = {
&vdd_cx,
&vdd_mx,
};
enum {
P_BI_TCXO,
P_GPLL0_OUT_EVEN,
P_GPLL0_OUT_MAIN,
P_GPLL10_OUT_EVEN,
P_GPLL10_OUT_MAIN,
P_GPLL3_OUT_EVEN,
P_GPLL3_OUT_MAIN,
P_GPLL4_OUT_EVEN,
P_GPLL6_OUT_EVEN,
P_GPLL6_OUT_MAIN,
P_GPLL7_OUT_EVEN,
P_GPLL8_OUT_EVEN,
P_GPLL8_OUT_MAIN,
P_GPLL9_OUT_EVEN,
P_GPLL9_OUT_MAIN,
P_SLEEP_CLK,
};
static struct pll_vco lucid_evo_vco[] = {
{ 249600000, 2000000000, 0 },
};
static struct pll_vco zonda_evo_vco[] = {
{ 600000000, 3600000000ULL, 0 },
};
static struct clk_alpha_pll gpll0 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
},
.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER_D1] = 500000000,
[VDD_LOWER] = 615000000,
[VDD_LOW] = 1066000000,
[VDD_LOW_L1] = 1500000000,
[VDD_NOMINAL] = 1800000000,
[VDD_HIGH] = 2000000000},
},
},
};
static const struct clk_div_table post_div_table_gpll0_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv gpll0_out_even = {
.offset = 0x0,
.post_div_shift = 10,
.post_div_table = post_div_table_gpll0_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0_out_even",
.parent_data = &(const struct clk_parent_data){
.hw = &gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
},
};
static struct alpha_pll_config gpll10_config = {
.l = 0x1E,
.cal_l = 0x44,
.alpha = 0x0,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x32AA299C,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000805,
};
static struct clk_alpha_pll gpll10 = {
.offset = 0xa000,
.vco_table = lucid_evo_vco,
.num_vco = ARRAY_SIZE(lucid_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.config = &gpll10_config,
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gpll10",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
.vdd_data = {
.vdd_class = &vdd_mx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER_D1] = 500000000,
[VDD_LOWER] = 615000000,
[VDD_LOW] = 1066000000,
[VDD_LOW_L1] = 1500000000,
[VDD_NOMINAL] = 1800000000,
[VDD_HIGH] = 2000000000},
},
},
};
static struct clk_alpha_pll gpll3 = {
.offset = 0x3000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gpll3",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
},
.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER_D1] = 500000000,
[VDD_LOWER] = 615000000,
[VDD_LOW] = 1066000000,
[VDD_LOW_L1] = 1500000000,
[VDD_NOMINAL] = 1800000000,
[VDD_HIGH] = 2000000000},
},
},
};
static const struct clk_div_table post_div_table_gpll3_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv gpll3_out_even = {
.offset = 0x3000,
.post_div_shift = 10,
.post_div_table = post_div_table_gpll3_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_gpll3_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll3_out_even",
.parent_data = &(const struct clk_parent_data){
.hw = &gpll3.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
},
};
static struct clk_alpha_pll gpll4 = {
.offset = 0x4000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gpll4",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
},
.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER_D1] = 500000000,
[VDD_LOWER] = 615000000,
[VDD_LOW] = 1066000000,
[VDD_LOW_L1] = 1500000000,
[VDD_NOMINAL] = 1800000000,
[VDD_HIGH] = 2000000000},
},
},
};
static struct clk_alpha_pll gpll6 = {
.offset = 0x6000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gpll6",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
},
.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER_D1] = 500000000,
[VDD_LOWER] = 615000000,
[VDD_LOW] = 1066000000,
[VDD_LOW_L1] = 1500000000,
[VDD_NOMINAL] = 1800000000,
[VDD_HIGH] = 2000000000},
},
},
};
static const struct clk_div_table post_div_table_gpll6_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv gpll6_out_even = {
.offset = 0x6000,
.post_div_shift = 10,
.post_div_table = post_div_table_gpll6_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll6_out_even",
.parent_data = &(const struct clk_parent_data){
.hw = &gpll6.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
},
};
static struct clk_alpha_pll gpll7 = {
.offset = 0x7000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gpll7",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
},
.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER_D1] = 500000000,
[VDD_LOWER] = 615000000,
[VDD_LOW] = 1066000000,
[VDD_LOW_L1] = 1500000000,
[VDD_NOMINAL] = 1800000000,
[VDD_HIGH] = 2000000000},
},
},
};
static struct alpha_pll_config gpll8_config = {
.l = 0x14,
.cal_l = 0x44,
.alpha = 0xD555,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x32AA299C,
.user_ctl_val = 0x00000400,
.user_ctl_hi_val = 0x00000805,
};
static struct clk_alpha_pll gpll8 = {
.offset = 0x8000,
.vco_table = lucid_evo_vco,
.num_vco = ARRAY_SIZE(lucid_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.config = &gpll8_config,
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gpll8",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER_D1] = 500000000,
[VDD_LOWER] = 615000000,
[VDD_LOW] = 1066000000,
[VDD_LOW_L1] = 1500000000,
[VDD_NOMINAL] = 1800000000,
[VDD_HIGH] = 2000000000},
},
},
};
static const struct clk_div_table post_div_table_gpll8_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv gpll8_out_even = {
.offset = 0x8000,
.post_div_shift = 10,
.post_div_table = post_div_table_gpll8_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll8_out_even",
.parent_data = &(const struct clk_parent_data){
.hw = &gpll8.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
},
};
static struct alpha_pll_config gpll9_config = {
.l = 0x32,
.alpha = 0x0,
.config_ctl_val = 0x08200800,
.config_ctl_hi_val = 0x05028011,
.config_ctl_hi1_val = 0x08000000,
.user_ctl_val = 0x00000001,
.user_ctl_hi_val = 0x00000000,
};
static struct clk_alpha_pll gpll9 = {
.offset = 0x9000,
.vco_table = zonda_evo_vco,
.num_vco = ARRAY_SIZE(zonda_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA_EVO],
.config = &gpll9_config,
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gpll9",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_zonda_evo_ops,
},
.vdd_data = {
.vdd_class = &vdd_mx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 1450000000,
[VDD_LOW] = 2000000000,
[VDD_NOMINAL] = 2900000000ULL,
[VDD_HIGH] = 3600000000ULL},
},
},
};
static const struct clk_div_table post_div_table_gpll9_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv gpll9_out_even = {
.offset = 0x9000,
.post_div_shift = 12,
.post_div_table = post_div_table_gpll9_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_even),
.width = 2,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA_EVO],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll9_out_even",
.parent_data = &(const struct clk_parent_data){
.hw = &gpll9.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_zonda_evo_ops,
},
};
static const struct parent_map gcc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_EVEN, 2 },
};
static const struct clk_parent_data gcc_parent_data_0[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct clk_parent_data gcc_parent_data_0_ao[] = {
{ .fw_name = "bi_tcxo_ao" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_EVEN, 2 },
{ P_GPLL6_OUT_EVEN, 4 },
};
static const struct clk_parent_data gcc_parent_data_1[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
{ .hw = &gpll6_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_EVEN, 2 },
{ P_SLEEP_CLK, 5 },
};
static const struct clk_parent_data gcc_parent_data_2[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
{ .fw_name = "sleep_clk" },
};
static const struct parent_map gcc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL9_OUT_MAIN, 2 },
{ P_GPLL10_OUT_EVEN, 3 },
{ P_GPLL9_OUT_EVEN, 5 },
{ P_GPLL3_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_3[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll9.clkr.hw },
{ .hw = &gpll10.clkr.hw },
{ .hw = &gpll9_out_even.clkr.hw },
{ .hw = &gpll3_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_EVEN, 2 },
{ P_GPLL10_OUT_EVEN, 3 },
{ P_GPLL4_OUT_EVEN, 5 },
{ P_GPLL3_OUT_MAIN, 6 },
};
static const struct clk_parent_data gcc_parent_data_4[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
{ .hw = &gpll10.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll3.clkr.hw },
};
static const struct parent_map gcc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_EVEN, 2 },
{ P_GPLL4_OUT_EVEN, 5 },
{ P_GPLL3_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_5[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll3_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_6[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL8_OUT_MAIN, 2 },
{ P_GPLL10_OUT_EVEN, 3 },
{ P_GPLL8_OUT_EVEN, 4 },
{ P_GPLL9_OUT_EVEN, 5 },
{ P_GPLL3_OUT_MAIN, 6 },
};
static const struct clk_parent_data gcc_parent_data_6[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll8.clkr.hw },
{ .hw = &gpll10.clkr.hw },
{ .hw = &gpll8_out_even.clkr.hw },
{ .hw = &gpll9_out_even.clkr.hw },
{ .hw = &gpll3.clkr.hw },
};
static const struct parent_map gcc_parent_map_7[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL8_OUT_MAIN, 2 },
{ P_GPLL10_OUT_MAIN, 3 },
{ P_GPLL8_OUT_EVEN, 4 },
{ P_GPLL9_OUT_EVEN, 5 },
{ P_GPLL3_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_7[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll8.clkr.hw },
{ .hw = &gpll10.clkr.hw },
{ .hw = &gpll8_out_even.clkr.hw },
{ .hw = &gpll9_out_even.clkr.hw },
{ .hw = &gpll3_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_8[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL8_OUT_MAIN, 2 },
{ P_GPLL10_OUT_EVEN, 3 },
{ P_GPLL6_OUT_EVEN, 4 },
{ P_GPLL9_OUT_EVEN, 5 },
{ P_GPLL3_OUT_MAIN, 6 },
};
static const struct clk_parent_data gcc_parent_data_8[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll8.clkr.hw },
{ .hw = &gpll10.clkr.hw },
{ .hw = &gpll6_out_even.clkr.hw },
{ .hw = &gpll9_out_even.clkr.hw },
{ .hw = &gpll3.clkr.hw },
};
static const struct parent_map gcc_parent_map_9[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_EVEN, 2 },
{ P_GPLL10_OUT_EVEN, 3 },
{ P_GPLL8_OUT_EVEN, 4 },
{ P_GPLL9_OUT_EVEN, 5 },
{ P_GPLL3_OUT_MAIN, 6 },
};
static const struct clk_parent_data gcc_parent_data_9[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
{ .hw = &gpll10.clkr.hw },
{ .hw = &gpll8_out_even.clkr.hw },
{ .hw = &gpll9_out_even.clkr.hw },
{ .hw = &gpll3.clkr.hw },
};
static const struct parent_map gcc_parent_map_10[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL8_OUT_MAIN, 2 },
{ P_GPLL10_OUT_EVEN, 3 },
{ P_GPLL6_OUT_MAIN, 5 },
{ P_GPLL3_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_10[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll8.clkr.hw },
{ .hw = &gpll10.clkr.hw },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll3_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_11[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_EVEN, 2 },
{ P_GPLL7_OUT_EVEN, 3 },
{ P_GPLL4_OUT_EVEN, 5 },
};
static const struct clk_parent_data gcc_parent_data_11[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
{ .hw = &gpll7.clkr.hw },
{ .hw = &gpll4.clkr.hw },
};
static const struct parent_map gcc_parent_map_12[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL6_OUT_MAIN, 5 },
};
static const struct clk_parent_data gcc_parent_data_12[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll6.clkr.hw },
};
static const struct freq_tbl ftbl_gcc_camss_axi_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0),
F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_axi_clk_src = {
.cmd_rcgr = 0x58034,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_camss_axi_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_axi_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_rcg2_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 19200000,
[VDD_LOW] = 150000000,
[VDD_NOMINAL] = 300000000},
},
};
static const struct freq_tbl ftbl_gcc_camss_cci_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_cci_clk_src = {
.cmd_rcgr = 0x56000,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_9,
.freq_tbl = ftbl_gcc_camss_cci_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cci_clk_src",
.parent_data = gcc_parent_data_9,
.num_parents = ARRAY_SIZE(gcc_parent_data_9),
.ops = &clk_rcg2_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 19200000,
[VDD_LOW] = 37500000},
},
};
static const struct freq_tbl ftbl_gcc_camss_csi0phytimer_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = {
.cmd_rcgr = 0x45000,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0phytimer_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
.ops = &clk_rcg2_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 19200000,
[VDD_LOW] = 300000000},
},
};
static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = {
.cmd_rcgr = 0x4501c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1phytimer_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
.ops = &clk_rcg2_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 19200000,
[VDD_LOW] = 300000000},
},
};
static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = {
F(19200000, P_GPLL9_OUT_MAIN, 2, 1, 25),
F(24000000, P_GPLL9_OUT_MAIN, 2, 1, 20),
F(64000000, P_GPLL9_OUT_MAIN, 1, 1, 15),
{ }
};
static struct clk_rcg2 gcc_camss_mclk0_clk_src = {
.cmd_rcgr = 0x51000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk0_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.flags = CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 64000000},
},
};
static struct clk_rcg2 gcc_camss_mclk1_clk_src = {
.cmd_rcgr = 0x5101c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk1_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.flags = CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 64000000},
},
};
static struct clk_rcg2 gcc_camss_mclk2_clk_src = {
.cmd_rcgr = 0x51038,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk2_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.flags = CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 64000000},
},
};
static struct clk_rcg2 gcc_camss_mclk3_clk_src = {
.cmd_rcgr = 0x51054,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk3_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.flags = CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 64000000},
},
};
static const struct freq_tbl ftbl_gcc_camss_ope_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_ope_ahb_clk_src = {
.cmd_rcgr = 0x55024,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_6,
.freq_tbl = ftbl_gcc_camss_ope_ahb_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_ope_ahb_clk_src",
.parent_data = gcc_parent_data_6,
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
.ops = &clk_rcg2_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 19200000,
[VDD_LOW] = 171428571,
[VDD_NOMINAL] = 240000000},
},
};
static const struct freq_tbl ftbl_gcc_camss_ope_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(200000000, P_GPLL8_OUT_EVEN, 1, 0, 0),
F(465000000, P_GPLL8_OUT_EVEN, 1, 0, 0),
F(580000000, P_GPLL8_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_ope_clk_src = {
.cmd_rcgr = 0x55004,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_6,
.freq_tbl = ftbl_gcc_camss_ope_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_ope_clk_src",
.parent_data = gcc_parent_data_6,
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 19200000,
[VDD_LOW] = 200000000,
[VDD_NOMINAL] = 465000000,
[VDD_HIGH] = 580000000},
},
};
static const struct freq_tbl ftbl_gcc_camss_tfe_0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(288000000, P_GPLL10_OUT_MAIN, 4, 0, 0),
F(576000000, P_GPLL10_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_tfe_0_clk_src = {
.cmd_rcgr = 0x52004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_7,
.freq_tbl = ftbl_gcc_camss_tfe_0_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_0_clk_src",
.parent_data = gcc_parent_data_7,
.num_parents = ARRAY_SIZE(gcc_parent_data_7),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 19200000,
[VDD_LOW] = 288000000,
[VDD_NOMINAL] = 576000000},
},
};
static const struct freq_tbl ftbl_gcc_camss_tfe_0_csid_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(256000000, P_GPLL6_OUT_EVEN, 1.5, 0, 0),
F(384000000, P_GPLL6_OUT_EVEN, 1, 0, 0),
F(426400000, P_GPLL3_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_tfe_0_csid_clk_src = {
.cmd_rcgr = 0x52094,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_0_csid_clk_src",
.parent_data = gcc_parent_data_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
.ops = &clk_rcg2_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 19200000,
[VDD_LOW] = 256000000,
[VDD_NOMINAL] = 384000000,
[VDD_HIGH] = 426400000},
},
};
static struct clk_rcg2 gcc_camss_tfe_1_clk_src = {
.cmd_rcgr = 0x52024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_7,
.freq_tbl = ftbl_gcc_camss_tfe_0_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_1_clk_src",
.parent_data = gcc_parent_data_7,
.num_parents = ARRAY_SIZE(gcc_parent_data_7),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 19200000,
[VDD_LOW] = 288000000,
[VDD_NOMINAL] = 576000000},
},
};
static struct clk_rcg2 gcc_camss_tfe_1_csid_clk_src = {
.cmd_rcgr = 0x520b4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_1_csid_clk_src",
.parent_data = gcc_parent_data_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
.ops = &clk_rcg2_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 19200000,
[VDD_LOW] = 256000000,
[VDD_NOMINAL] = 384000000,
[VDD_HIGH] = 426400000},
},
};
static const struct freq_tbl ftbl_gcc_camss_tfe_cphy_rx_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(256000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
F(384000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_tfe_cphy_rx_clk_src = {
.cmd_rcgr = 0x52064,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_10,
.freq_tbl = ftbl_gcc_camss_tfe_cphy_rx_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_cphy_rx_clk_src",
.parent_data = gcc_parent_data_10,
.num_parents = ARRAY_SIZE(gcc_parent_data_10),
.ops = &clk_rcg2_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 19200000,
[VDD_LOW] = 256000000,
[VDD_NOMINAL] = 384000000},
},
};
static const struct freq_tbl ftbl_gcc_camss_top_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0),
F(80000000, P_GPLL0_OUT_MAIN, 7.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_top_ahb_clk_src = {
.cmd_rcgr = 0x58018,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_camss_top_ahb_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_top_ahb_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_rcg2_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 19200000,
[VDD_LOW] = 80000000},
},
};
static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
.cmd_rcgr = 0x2b13c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_ahb_clk_src",
.parent_data = gcc_parent_data_0_ao,
.num_parents = ARRAY_SIZE(gcc_parent_data_0_ao),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_gp1_clk_src = {
.cmd_rcgr = 0x4d004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 50000000,
[VDD_LOW] = 100000000,
[VDD_NOMINAL] = 200000000},
},
};
static struct clk_rcg2 gcc_gp2_clk_src = {
.cmd_rcgr = 0x4e004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 50000000,
[VDD_LOW] = 100000000,
[VDD_NOMINAL] = 200000000},
},
};
static struct clk_rcg2 gcc_gp3_clk_src = {
.cmd_rcgr = 0x4f004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 50000000,
[VDD_LOW] = 100000000,
[VDD_NOMINAL] = 200000000},
},
};
static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pdm2_clk_src = {
.cmd_rcgr = 0x20010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pdm2_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 19200000,
[VDD_LOW] = 60000000},
},
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
{ }
};
static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
.name = "gcc_qupv3_wrap0_s0_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
.cmd_rcgr = 0x1f154,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 75000000,
[VDD_LOW] = 100000000},
},
};
static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
.name = "gcc_qupv3_wrap0_s1_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
.cmd_rcgr = 0x1f288,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 75000000,
[VDD_LOW] = 100000000},
},
};
static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
.name = "gcc_qupv3_wrap0_s2_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
.cmd_rcgr = 0x1f3bc,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 75000000,
[VDD_LOW] = 100000000},
},
};
static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
.name = "gcc_qupv3_wrap0_s3_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
.cmd_rcgr = 0x1f4f0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 75000000,
[VDD_LOW] = 100000000},
},
};
static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
.name = "gcc_qupv3_wrap0_s4_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
.cmd_rcgr = 0x1f624,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 75000000,
[VDD_LOW] = 100000000},
},
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s5_clk_src[] = {
F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
{ }
};
static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
.name = "gcc_qupv3_wrap0_s5_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
.cmd_rcgr = 0x1f758,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s5_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 75000000,
[VDD_LOW] = 120000000},
},
};
static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
.name = "gcc_qupv3_wrap0_s6_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
.cmd_rcgr = 0x1f88c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s5_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 75000000,
[VDD_LOW] = 120000000},
},
};
static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
.name = "gcc_qupv3_wrap0_s7_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
.cmd_rcgr = 0x1f9c0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 75000000,
[VDD_LOW] = 100000000},
},
};
static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
F(144000, P_BI_TCXO, 16, 3, 25),
F(400000, P_BI_TCXO, 12, 1, 4),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3),
F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
F(192000000, P_GPLL6_OUT_EVEN, 2, 0, 0),
F(384000000, P_GPLL6_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
.cmd_rcgr = 0x38030,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_floor_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 100000000,
[VDD_NOMINAL] = 384000000},
},
};
static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
.cmd_rcgr = 0x38018,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ice_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 100000000,
[VDD_LOW] = 150000000,
[VDD_NOMINAL] = 300000000},
},
};
static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
F(202000000, P_GPLL7_OUT_EVEN, 4, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
.cmd_rcgr = 0x1e010,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_11,
.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk_src",
.parent_data = gcc_parent_data_11,
.num_parents = ARRAY_SIZE(gcc_parent_data_11),
.ops = &clk_rcg2_floor_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 100000000,
[VDD_NOMINAL] = 202000000},
},
};
static const struct freq_tbl ftbl_gcc_usb20_master_clk_src[] = {
F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb20_master_clk_src = {
.cmd_rcgr = 0x1c028,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb20_master_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb20_master_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 60000000,
[VDD_NOMINAL] = 120000000},
},
};
static const struct freq_tbl ftbl_gcc_usb20_mock_utmi_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb20_mock_utmi_clk_src = {
.cmd_rcgr = 0x1c040,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb20_mock_utmi_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb20_mock_utmi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 19200000},
},
};
static const struct freq_tbl ftbl_gcc_video_venus_clk_src[] = {
F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
F(384000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_video_venus_clk_src = {
.cmd_rcgr = 0x5806c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_12,
.freq_tbl = ftbl_gcc_video_venus_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_video_venus_clk_src",
.parent_data = gcc_parent_data_12,
.num_parents = ARRAY_SIZE(gcc_parent_data_12),
.ops = &clk_rcg2_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 133333333,
[VDD_LOW] = 240000000,
[VDD_NOMINAL] = 384000000},
},
};
static struct clk_regmap_div gcc_cpuss_ahb_postdiv_clk_src = {
.reg = 0x2b154,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gcc_cpuss_ahb_postdiv_clk_src",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_cpuss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap_div gcc_usb20_mock_utmi_postdiv_clk_src = {
.reg = 0x1c058,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gcc_usb20_mock_utmi_postdiv_clk_src",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_usb20_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch gcc_ahb2phy_csi_clk = {
.halt_reg = 0x1c074,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x1c074,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1c074,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ahb2phy_csi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_bimc_gpu_axi_clk = {
.halt_reg = 0x71154,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x71154,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x71154,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_bimc_gpu_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x23004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x23004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cam_throttle_nrt_clk = {
.halt_reg = 0x17078,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17078,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(27),
.hw.init = &(struct clk_init_data){
.name = "gcc_cam_throttle_nrt_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cam_throttle_rt_clk = {
.halt_reg = 0x17074,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17074,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){
.name = "gcc_cam_throttle_rt_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_axi_clk = {
.halt_reg = 0x5804c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5804c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_axi_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_camnoc_atb_clk = {
.halt_reg = 0x58054,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x58054,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x58054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_camnoc_atb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_camnoc_nts_xo_clk = {
.halt_reg = 0x5805c,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x5805c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x5805c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_camnoc_nts_xo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cci_0_clk = {
.halt_reg = 0x56018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x56018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cci_0_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_cci_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cphy_0_clk = {
.halt_reg = 0x52088,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x52088,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cphy_0_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cphy_1_clk = {
.halt_reg = 0x5208c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5208c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cphy_1_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi0phytimer_clk = {
.halt_reg = 0x45018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x45018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0phytimer_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_csi0phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi1phytimer_clk = {
.halt_reg = 0x45034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x45034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1phytimer_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_csi1phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_mclk0_clk = {
.halt_reg = 0x51018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x51018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk0_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_mclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_mclk1_clk = {
.halt_reg = 0x51034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x51034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk1_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_mclk1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_mclk2_clk = {
.halt_reg = 0x51050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x51050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk2_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_mclk2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_mclk3_clk = {
.halt_reg = 0x5106c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5106c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk3_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_mclk3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_nrt_axi_clk = {
.halt_reg = 0x58060,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x58060,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_nrt_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_ope_ahb_clk = {
.halt_reg = 0x5503c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5503c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_ope_ahb_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_ope_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_ope_clk = {
.halt_reg = 0x5501c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5501c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_ope_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_ope_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_rt_axi_clk = {
.halt_reg = 0x58068,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x58068,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_rt_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_tfe_0_clk = {
.halt_reg = 0x5201c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5201c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_0_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_tfe_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_tfe_0_cphy_rx_clk = {
.halt_reg = 0x5207c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5207c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_0_cphy_rx_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_tfe_0_csid_clk = {
.halt_reg = 0x520ac,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x520ac,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_0_csid_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_tfe_0_csid_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_tfe_1_clk = {
.halt_reg = 0x5203c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5203c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_1_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_tfe_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_tfe_1_cphy_rx_clk = {
.halt_reg = 0x52080,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x52080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_1_cphy_rx_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_tfe_1_csid_clk = {
.halt_reg = 0x520cc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x520cc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_1_csid_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_tfe_1_csid_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_top_ahb_clk = {
.halt_reg = 0x58030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x58030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_top_ahb_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb2_prim_axi_clk = {
.halt_reg = 0x1c068,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1c068,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1c068,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_usb2_prim_axi_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_usb20_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_gpll0_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(20),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_gpll0_clk_src",
.parent_data = &(const struct clk_parent_data){
.hw = &gpll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_hf_axi_clk = {
.halt_reg = 0x1701c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x1701c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1701c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_hf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_throttle_core_clk = {
.halt_reg = 0x1706c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1706c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_throttle_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x4d000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x4e000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4e000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x4f000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4f000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_clk_src",
.parent_data = &(const struct clk_parent_data){
.hw = &gpll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_div_clk_src",
.parent_data = &(const struct clk_parent_data){
.hw = &gpll0_out_even.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
.halt_reg = 0x3600c,
.halt_check = BRANCH_VOTED,
.hwcg_reg = 0x3600c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x3600c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_memnoc_gfx_clk",
.flags = CLK_DONT_HOLD_STATE,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
.halt_reg = 0x36018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x36018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_snoc_dvm_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_throttle_core_clk = {
.halt_reg = 0x36048,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x36048,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(31),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_throttle_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x2000c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2000c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x20004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x20004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x20004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_xo4_clk = {
.halt_reg = 0x20008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x20008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_xo4_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pwm0_xo512_clk = {
.halt_reg = 0x2002c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2002c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pwm0_xo512_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
.halt_reg = 0x17014,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_camera_nrt_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
.halt_reg = 0x17068,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17068,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_camera_rt_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_disp_ahb_clk = {
.halt_reg = 0x17018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_disp_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_gpu_cfg_ahb_clk = {
.halt_reg = 0x36040,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x36040,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_gpu_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
.halt_reg = 0x17010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_video_vcodec_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
.halt_reg = 0x1f018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_core_clk = {
.halt_reg = 0x1f00c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
.halt_reg = 0x1f14c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s0_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
.halt_reg = 0x1f280,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s1_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
.halt_reg = 0x1f3b4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s2_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
.halt_reg = 0x1f4e8,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s3_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
.halt_reg = 0x1f61c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s4_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
.halt_reg = 0x1f750,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s5_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
.halt_reg = 0x1f884,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s6_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
.halt_reg = 0x1f9b8,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s7_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
.halt_reg = 0x1f004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1f004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_0_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
.halt_reg = 0x1f008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1f008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_0_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0x3800c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3800c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_apps_clk = {
.halt_reg = 0x38004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x38004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_sdcc1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ice_core_clk = {
.halt_reg = 0x38010,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x38010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x38010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ice_core_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_sdcc1_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x1e00c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1e00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_apps_clk = {
.halt_reg = 0x1e004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1e004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_sdcc2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
.halt_reg = 0x2b06c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2b06c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_cpuss_ahb_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_usb2_prim_axi_clk = {
.halt_reg = 0x1c07c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1c07c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1c07c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_usb2_prim_axi_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_usb20_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb20_master_clk = {
.halt_reg = 0x1c018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1c018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb20_master_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_usb20_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb20_mock_utmi_clk = {
.halt_reg = 0x1c024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1c024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb20_mock_utmi_clk",
.parent_data = &(const struct clk_parent_data){
.hw =
&gcc_usb20_mock_utmi_postdiv_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb20_sleep_clk = {
.halt_reg = 0x1c020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1c020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb20_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
/* Always ON clk required by USB driver */
static struct clk_branch gcc_usb2_prim_clkref_clk = {
.halt_reg = 0x9f000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9f000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb2_prim_clkref_clk",
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gcc_vcodec0_axi_clk = {
.halt_reg = 0x6e008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6e008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_vcodec0_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_venus_ahb_clk = {
.halt_reg = 0x6e010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6e010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_venus_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_venus_ctl_axi_clk = {
.halt_reg = 0x6e004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6e004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_venus_ctl_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_ahb_clk = {
.halt_reg = 0x17004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x17004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x17004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_throttle_core_clk = {
.halt_reg = 0x17070,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17070,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(28),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_throttle_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_vcodec0_sys_clk = {
.halt_reg = 0x580c0,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x580c0,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x580c0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_vcodec0_sys_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_video_venus_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_venus_ctl_clk = {
.halt_reg = 0x580a0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x580a0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_venus_ctl_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_video_venus_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_xo_clk = {
.halt_reg = 0x17024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x17024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_xo_clk",
.ops = &clk_branch2_ops,
},
},
};
/*
* Keep the clocks always-ON
* GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK,
* GCC_DISP_AHB_CLK, GCC_DISP_XO_CLK, GCC_AHB2PHY_USB_CLK,
* GCC_CPUSS_GNOC_CLK, GCC_CPUSS_TRIG_CLK,GCC_GPU_CFG_AHB_CLK,
* GCC_GPU_IREF_CLK
*/
static struct critical_clk_offset critical_clk_list[] = {
{ .offset = 0x17008, .mask = BIT(0) },
{ .offset = 0x17028, .mask = BIT(0) },
{ .offset = 0x1700c, .mask = BIT(0) },
{ .offset = 0x1702c, .mask = BIT(0) },
{ .offset = 0x1c078, .mask = BIT(0) },
{ .offset = 0x2b004, .mask = BIT(0) },
{ .offset = 0x2b008, .mask = BIT(0) },
{ .offset = 0x36004, .mask = BIT(0) },
{ .offset = 0x36100, .mask = BIT(0) },
};
static struct clk_regmap *gcc_monaco_clocks[] = {
[GCC_AHB2PHY_CSI_CLK] = &gcc_ahb2phy_csi_clk.clkr,
[GCC_BIMC_GPU_AXI_CLK] = &gcc_bimc_gpu_axi_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr,
[GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr,
[GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr,
[GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr,
[GCC_CAMSS_CAMNOC_ATB_CLK] = &gcc_camss_camnoc_atb_clk.clkr,
[GCC_CAMSS_CAMNOC_NTS_XO_CLK] = &gcc_camss_camnoc_nts_xo_clk.clkr,
[GCC_CAMSS_CCI_0_CLK] = &gcc_camss_cci_0_clk.clkr,
[GCC_CAMSS_CCI_CLK_SRC] = &gcc_camss_cci_clk_src.clkr,
[GCC_CAMSS_CPHY_0_CLK] = &gcc_camss_cphy_0_clk.clkr,
[GCC_CAMSS_CPHY_1_CLK] = &gcc_camss_cphy_1_clk.clkr,
[GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
[GCC_CAMSS_CSI0PHYTIMER_CLK_SRC] = &gcc_camss_csi0phytimer_clk_src.clkr,
[GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
[GCC_CAMSS_CSI1PHYTIMER_CLK_SRC] = &gcc_camss_csi1phytimer_clk_src.clkr,
[GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
[GCC_CAMSS_MCLK0_CLK_SRC] = &gcc_camss_mclk0_clk_src.clkr,
[GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
[GCC_CAMSS_MCLK1_CLK_SRC] = &gcc_camss_mclk1_clk_src.clkr,
[GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr,
[GCC_CAMSS_MCLK2_CLK_SRC] = &gcc_camss_mclk2_clk_src.clkr,
[GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr,
[GCC_CAMSS_MCLK3_CLK_SRC] = &gcc_camss_mclk3_clk_src.clkr,
[GCC_CAMSS_NRT_AXI_CLK] = &gcc_camss_nrt_axi_clk.clkr,
[GCC_CAMSS_OPE_AHB_CLK] = &gcc_camss_ope_ahb_clk.clkr,
[GCC_CAMSS_OPE_AHB_CLK_SRC] = &gcc_camss_ope_ahb_clk_src.clkr,
[GCC_CAMSS_OPE_CLK] = &gcc_camss_ope_clk.clkr,
[GCC_CAMSS_OPE_CLK_SRC] = &gcc_camss_ope_clk_src.clkr,
[GCC_CAMSS_RT_AXI_CLK] = &gcc_camss_rt_axi_clk.clkr,
[GCC_CAMSS_TFE_0_CLK] = &gcc_camss_tfe_0_clk.clkr,
[GCC_CAMSS_TFE_0_CLK_SRC] = &gcc_camss_tfe_0_clk_src.clkr,
[GCC_CAMSS_TFE_0_CPHY_RX_CLK] = &gcc_camss_tfe_0_cphy_rx_clk.clkr,
[GCC_CAMSS_TFE_0_CSID_CLK] = &gcc_camss_tfe_0_csid_clk.clkr,
[GCC_CAMSS_TFE_0_CSID_CLK_SRC] = &gcc_camss_tfe_0_csid_clk_src.clkr,
[GCC_CAMSS_TFE_1_CLK] = &gcc_camss_tfe_1_clk.clkr,
[GCC_CAMSS_TFE_1_CLK_SRC] = &gcc_camss_tfe_1_clk_src.clkr,
[GCC_CAMSS_TFE_1_CPHY_RX_CLK] = &gcc_camss_tfe_1_cphy_rx_clk.clkr,
[GCC_CAMSS_TFE_1_CSID_CLK] = &gcc_camss_tfe_1_csid_clk.clkr,
[GCC_CAMSS_TFE_1_CSID_CLK_SRC] = &gcc_camss_tfe_1_csid_clk_src.clkr,
[GCC_CAMSS_TFE_CPHY_RX_CLK_SRC] = &gcc_camss_tfe_cphy_rx_clk_src.clkr,
[GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
[GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr,
[GCC_CFG_NOC_USB2_PRIM_AXI_CLK] = &gcc_cfg_noc_usb2_prim_axi_clk.clkr,
[GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
[GCC_CPUSS_AHB_POSTDIV_CLK_SRC] = &gcc_cpuss_ahb_postdiv_clk_src.clkr,
[GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
[GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
[GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
[GCC_PWM0_XO512_CLK] = &gcc_pwm0_xo512_clk.clkr,
[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
[GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr,
[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
[GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
[GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
[GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
[GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
[GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
[GCC_SYS_NOC_USB2_PRIM_AXI_CLK] = &gcc_sys_noc_usb2_prim_axi_clk.clkr,
[GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
[GCC_USB20_MASTER_CLK_SRC] = &gcc_usb20_master_clk_src.clkr,
[GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
[GCC_USB20_MOCK_UTMI_CLK_SRC] = &gcc_usb20_mock_utmi_clk_src.clkr,
[GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC] =
&gcc_usb20_mock_utmi_postdiv_clk_src.clkr,
[GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
[GCC_USB2_PRIM_CLKREF_CLK] = &gcc_usb2_prim_clkref_clk.clkr,
[GCC_VCODEC0_AXI_CLK] = &gcc_vcodec0_axi_clk.clkr,
[GCC_VENUS_AHB_CLK] = &gcc_venus_ahb_clk.clkr,
[GCC_VENUS_CTL_AXI_CLK] = &gcc_venus_ctl_axi_clk.clkr,
[GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
[GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr,
[GCC_VIDEO_VCODEC0_SYS_CLK] = &gcc_video_vcodec0_sys_clk.clkr,
[GCC_VIDEO_VENUS_CLK_SRC] = &gcc_video_venus_clk_src.clkr,
[GCC_VIDEO_VENUS_CTL_CLK] = &gcc_video_venus_ctl_clk.clkr,
[GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
[GPLL0] = &gpll0.clkr,
[GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
[GPLL10] = &gpll10.clkr,
[GPLL3] = &gpll3.clkr,
[GPLL3_OUT_EVEN] = &gpll3_out_even.clkr,
[GPLL4] = &gpll4.clkr,
[GPLL6] = &gpll6.clkr,
[GPLL6_OUT_EVEN] = &gpll6_out_even.clkr,
[GPLL7] = &gpll7.clkr,
[GPLL8] = &gpll8.clkr,
[GPLL8_OUT_EVEN] = &gpll8_out_even.clkr,
[GPLL9] = &gpll9.clkr,
[GPLL9_OUT_EVEN] = &gpll9_out_even.clkr,
};
static const struct qcom_reset_map gcc_monaco_resets[] = {
[GCC_CAMSS_OPE_BCR] = { 0x55000 },
[GCC_CAMSS_TFE_BCR] = { 0x52000 },
[GCC_CAMSS_TOP_BCR] = { 0x58000 },
[GCC_GPU_BCR] = { 0x36000 },
[GCC_MMSS_BCR] = { 0x17000 },
[GCC_PDM_BCR] = { 0x20000 },
[GCC_QUPV3_WRAPPER_0_BCR] = { 0x1f000 },
[GCC_QUSB2PHY_PRIM_BCR] = { 0x1c05c },
[GCC_QUSB2PHY_SEC_BCR] = { 0x1c060 },
[GCC_SDCC1_BCR] = { 0x38000 },
[GCC_SDCC2_BCR] = { 0x1e000 },
[GCC_USB20_PRIM_BCR] = { 0x1c000 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1c064 },
[GCC_VCODEC0_BCR] = { 0x580a8 },
[GCC_VENUS_BCR] = { 0x58084 },
[GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 },
};
static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
};
static const struct regmap_config gcc_monaco_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0xc7000,
.fast_io = true,
};
static struct qcom_cc_desc gcc_monaco_desc = {
.config = &gcc_monaco_regmap_config,
.clks = gcc_monaco_clocks,
.num_clks = ARRAY_SIZE(gcc_monaco_clocks),
.resets = gcc_monaco_resets,
.num_resets = ARRAY_SIZE(gcc_monaco_resets),
.clk_regulators = gcc_monaco_regulators,
.num_clk_regulators = ARRAY_SIZE(gcc_monaco_regulators),
.critical_clk_en = critical_clk_list,
.num_critical_clk = ARRAY_SIZE(critical_clk_list),
};
static const struct of_device_id gcc_monaco_match_table[] = {
{ .compatible = "qcom,monaco-gcc" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_monaco_match_table);
static int gcc_monaco_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gcc_monaco_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_lucid_evo_pll_configure(&gpll10, regmap, &gpll10_config);
clk_lucid_evo_pll_configure(&gpll8, regmap, &gpll8_config);
clk_zonda_evo_pll_configure(&gpll9, regmap, &gpll9_config);
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
return ret;
/* Configure WAKEUP cycle for gcc_gpu_memnoc_gfx_clk */
regmap_update_bits(regmap, 0x3600c, 0xF00, 0xF00);
ret = register_qcom_clks_pm(pdev, false, &gcc_monaco_desc);
if (ret)
dev_err(&pdev->dev, "Failed register gcc_pm_rt_ops clocks\n");
/* Enabling always ON clocks */
clk_restore_critical_clocks(&pdev->dev);
ret = qcom_cc_really_probe(pdev, &gcc_monaco_desc, regmap);
if (ret) {
dev_err(&pdev->dev, "Failed to register GCC clocks\n");
return ret;
}
dev_info(&pdev->dev, "Registered GCC clocks\n");
return ret;
}
static void gcc_monaco_sync_state(struct device *dev)
{
qcom_cc_sync_state(dev, &gcc_monaco_desc);
}
static struct platform_driver gcc_monaco_driver = {
.probe = gcc_monaco_probe,
.driver = {
.name = "gcc-monaco",
.of_match_table = gcc_monaco_match_table,
.sync_state = gcc_monaco_sync_state,
},
};
static int __init gcc_monaco_init(void)
{
return platform_driver_register(&gcc_monaco_driver);
}
subsys_initcall(gcc_monaco_init);
static void __exit gcc_monaco_exit(void)
{
platform_driver_unregister(&gcc_monaco_driver);
}
module_exit(gcc_monaco_exit);
MODULE_DESCRIPTION("QTI GCC MONACO Driver");
MODULE_LICENSE("GPL");
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