2331 lines
64 KiB
C
Executable File
2331 lines
64 KiB
C
Executable File
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of.h>
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#include <linux/regmap.h>
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#include <linux/pm_runtime.h>
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#include <dt-bindings/clock/qcom,dispcc-sun.h>
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-pll.h"
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#include "clk-rcg.h"
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#include "clk-regmap.h"
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#include "clk-regmap-divider.h"
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#include "clk-regmap-mux.h"
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#include "common.h"
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#include "gdsc.h"
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#include "reset.h"
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#include "vdd-level.h"
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#define DISP_CC_MISC_CMD 0xF000
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static DEFINE_VDD_REGULATORS(vdd_mm, VDD_NOMINAL_L1 + 1, 1, vdd_corner);
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static DEFINE_VDD_REGULATORS(vdd_mx, VDD_NOMINAL_L1 + 1, 1, vdd_corner);
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static DEFINE_VDD_REGULATORS(vdd_mxa, VDD_NOMINAL_L1 + 1, 1, vdd_corner);
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static struct clk_vdd_class *disp_cc_sun_regulators[] = {
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&vdd_mm,
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&vdd_mx,
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};
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static struct clk_vdd_class *disp_cc_mx_sun_regulators[] = {
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&vdd_mxa,
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};
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static struct clk_crm disp_crm = {
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.name = "disp_crm",
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.num_perf_ol = 10,
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.regs = {
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.cfg_rcgr = 0xd8,
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.l_val = 0xdc,
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.curr_perf = 0x18,
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},
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.offsets = {
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.vcd = 0x268,
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.level = 0x28,
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},
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};
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enum {
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P_BI_TCXO,
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P_DISP_CC_PLL0_OUT_MAIN,
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P_DISP_CC_PLL1_OUT_EVEN,
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P_DISP_CC_PLL1_OUT_MAIN,
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P_DISP_CC_PLL2_OUT_MAIN,
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P_DP0_PHY_PLL_LINK_CLK,
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P_DP0_PHY_PLL_VCO_DIV_CLK,
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P_DP1_PHY_PLL_LINK_CLK,
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P_DP1_PHY_PLL_VCO_DIV_CLK,
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P_DP2_PHY_PLL_LINK_CLK,
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P_DP2_PHY_PLL_VCO_DIV_CLK,
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P_DP3_PHY_PLL_LINK_CLK,
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P_DP3_PHY_PLL_VCO_DIV_CLK,
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P_DSI0_PHY_PLL_OUT_BYTECLK,
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P_DSI0_PHY_PLL_OUT_DSICLK,
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P_DSI1_PHY_PLL_OUT_BYTECLK,
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P_DSI1_PHY_PLL_OUT_DSICLK,
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P_SLEEP_CLK,
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};
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static const struct pll_vco pongo_elu_vco[] = {
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{ 38400000, 38400000, 0 },
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};
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static const struct pll_vco taycan_elu_vco[] = {
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{ 249600000, 2500000000, 0 },
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};
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static const struct alpha_pll_config disp_cc_pll0_config = {
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.l = 0xd,
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.cal_l = 0x44,
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.alpha = 0x6492,
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.config_ctl_val = 0x19660387,
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.config_ctl_hi_val = 0x098060a0,
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.config_ctl_hi1_val = 0xb416cb20,
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.user_ctl_val = 0x00000000,
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.user_ctl_hi_val = 0x00000002,
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};
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static struct clk_alpha_pll disp_cc_pll0 = {
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.offset = 0x0,
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.vco_table = taycan_elu_vco,
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.num_vco = ARRAY_SIZE(taycan_elu_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU],
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.clkr = {
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.hw.init = &(const struct clk_init_data) {
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.name = "disp_cc_pll0",
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.parent_data = &(const struct clk_parent_data) {
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.fw_name = "bi_tcxo",
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.name = "bi_tcxo",
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},
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.num_parents = 1,
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.flags = CLK_GET_RATE_NOCACHE,
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.ops = &clk_alpha_pll_crm_taycan_elu_ops,
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},
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.vdd_data = {
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.vdd_class = &vdd_mm,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOWER_D1] = 621000000,
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[VDD_LOW] = 1066000000,
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[VDD_LOW_L1] = 1600000000,
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[VDD_NOMINAL] = 2000000000,
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[VDD_HIGH] = 2500000000},
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},
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},
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};
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static const struct alpha_pll_config disp_cc_pll1_config = {
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.l = 0x1f,
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.cal_l = 0x44,
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.alpha = 0x4000,
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.config_ctl_val = 0x19660387,
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.config_ctl_hi_val = 0x098060a0,
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.config_ctl_hi1_val = 0xb416cb20,
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.user_ctl_val = 0x00000000,
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.user_ctl_hi_val = 0x00000002,
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};
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static struct clk_alpha_pll disp_cc_pll1 = {
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.offset = 0x1000,
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.vco_table = taycan_elu_vco,
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.num_vco = ARRAY_SIZE(taycan_elu_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU],
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.flags = DISABLE_TO_OFF,
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.clkr = {
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.hw.init = &(const struct clk_init_data) {
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.name = "disp_cc_pll1",
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.parent_data = &(const struct clk_parent_data) {
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.fw_name = "bi_tcxo",
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.name = "bi_tcxo",
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_taycan_elu_ops,
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},
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.vdd_data = {
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.vdd_class = &vdd_mm,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOWER_D1] = 621000000,
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[VDD_LOW] = 1066000000,
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[VDD_LOW_L1] = 1600000000,
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[VDD_NOMINAL] = 2000000000,
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[VDD_HIGH] = 2500000000},
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},
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},
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};
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static const struct alpha_pll_config disp_cc_pll2_config = {
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.l = 0x493,
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.cal_l = 0x493,
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.alpha = 0x0,
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.config_ctl_val = 0x60000f68,
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.config_ctl_hi_val = 0x0001c808,
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.config_ctl_hi1_val = 0x00000000,
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.config_ctl_hi2_val = 0x040082f4,
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.test_ctl_val = 0x00008000,
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.test_ctl_hi_val = 0x0080c496,
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.test_ctl_hi1_val = 0x40100180,
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.test_ctl_hi2_val = 0x441001bc,
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.test_ctl_hi3_val = 0x002003d8,
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.user_ctl_val = 0x00000400,
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.user_ctl_hi_val = 0x00e50302,
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};
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static struct clk_alpha_pll disp_cc_pll2 = {
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.offset = 0x2000,
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.vco_table = pongo_elu_vco,
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.num_vco = ARRAY_SIZE(pongo_elu_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_PONGO_ELU],
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.clkr = {
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.hw.init = &(const struct clk_init_data) {
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.name = "disp_cc_pll2",
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.parent_data = &(const struct clk_parent_data) {
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.fw_name = "sleep_clk",
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.name = "sleep_clk",
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_pongo_elu_ops,
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},
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.vdd_data = {
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.vdd_class = &vdd_mxa,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOWER_D1] = 38400000},
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},
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},
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};
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static const struct parent_map disp_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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};
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static const struct clk_parent_data disp_cc_parent_data_0[] = {
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{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
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};
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static const struct clk_parent_data disp_cc_parent_data_0_ao[] = {
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{ .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" },
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};
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static const struct parent_map disp_cc_parent_map_1[] = {
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{ P_BI_TCXO, 0 },
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{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
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{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
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{ P_DSI1_PHY_PLL_OUT_DSICLK, 3 },
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{ P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
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};
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static const struct clk_parent_data disp_cc_parent_data_1[] = {
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{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
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{ .fw_name = "dsi0_phy_pll_out_dsiclk", .name = "dsi0_phy_pll_out_dsiclk" },
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{ .fw_name = "dsi0_phy_pll_out_byteclk", .name = "dsi0_phy_pll_out_byteclk" },
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{ .fw_name = "dsi1_phy_pll_out_dsiclk", .name = "dsi1_phy_pll_out_dsiclk" },
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{ .fw_name = "dsi1_phy_pll_out_byteclk", .name = "dsi1_phy_pll_out_byteclk" },
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};
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static const struct parent_map disp_cc_parent_map_2[] = {
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{ P_BI_TCXO, 0 },
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{ P_DP3_PHY_PLL_VCO_DIV_CLK, 3 },
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{ P_DP1_PHY_PLL_VCO_DIV_CLK, 4 },
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{ P_DP2_PHY_PLL_VCO_DIV_CLK, 6 },
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};
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static const struct clk_parent_data disp_cc_parent_data_2[] = {
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{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
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{ .fw_name = "dp3_phy_pll_vco_div_clk", .name = "dp3_phy_pll_vco_div_clk" },
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{ .fw_name = "dp1_phy_pll_vco_div_clk", .name = "dp1_phy_pll_vco_div_clk" },
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{ .fw_name = "dp2_phy_pll_vco_div_clk", .name = "dp2_phy_pll_vco_div_clk" },
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};
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static const struct parent_map disp_cc_parent_map_3[] = {
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{ P_BI_TCXO, 0 },
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{ P_DP1_PHY_PLL_LINK_CLK, 2 },
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{ P_DP2_PHY_PLL_LINK_CLK, 3 },
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{ P_DP3_PHY_PLL_LINK_CLK, 4 },
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};
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static const struct clk_parent_data disp_cc_parent_data_3[] = {
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{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
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{ .fw_name = "dp1_phy_pll_link_clk", .name = "dp1_phy_pll_link_clk" },
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{ .fw_name = "dp2_phy_pll_link_clk", .name = "dp2_phy_pll_link_clk" },
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{ .fw_name = "dp3_phy_pll_link_clk", .name = "dp3_phy_pll_link_clk" },
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};
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static const struct parent_map disp_cc_parent_map_4[] = {
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{ P_BI_TCXO, 0 },
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{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
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{ P_DISP_CC_PLL2_OUT_MAIN, 2 },
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{ P_DSI1_PHY_PLL_OUT_DSICLK, 3 },
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};
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static const struct clk_parent_data disp_cc_parent_data_4[] = {
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{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
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{ .fw_name = "dsi0_phy_pll_out_dsiclk", .name = "dsi0_phy_pll_out_dsiclk" },
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{ .hw = &disp_cc_pll2.clkr.hw },
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{ .fw_name = "dsi1_phy_pll_out_dsiclk", .name = "dsi1_phy_pll_out_dsiclk" },
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};
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static const struct parent_map disp_cc_parent_map_5[] = {
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{ P_BI_TCXO, 0 },
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{ P_DP0_PHY_PLL_LINK_CLK, 1 },
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{ P_DP0_PHY_PLL_VCO_DIV_CLK, 2 },
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{ P_DP3_PHY_PLL_VCO_DIV_CLK, 3 },
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{ P_DP1_PHY_PLL_VCO_DIV_CLK, 4 },
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{ P_DP2_PHY_PLL_VCO_DIV_CLK, 6 },
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};
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static const struct clk_parent_data disp_cc_parent_data_5[] = {
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{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
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{ .fw_name = "dp0_phy_pll_link_clk", .name = "dp0_phy_pll_link_clk" },
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{ .fw_name = "dp0_phy_pll_vco_div_clk", .name = "dp0_phy_pll_vco_div_clk" },
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{ .fw_name = "dp3_phy_pll_vco_div_clk", .name = "dp3_phy_pll_vco_div_clk" },
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{ .fw_name = "dp1_phy_pll_vco_div_clk", .name = "dp1_phy_pll_vco_div_clk" },
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{ .fw_name = "dp2_phy_pll_vco_div_clk", .name = "dp2_phy_pll_vco_div_clk" },
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};
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static const struct parent_map disp_cc_parent_map_6[] = {
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{ P_BI_TCXO, 0 },
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{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
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{ P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
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};
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static const struct clk_parent_data disp_cc_parent_data_6[] = {
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{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
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{ .fw_name = "dsi0_phy_pll_out_byteclk", .name = "dsi0_phy_pll_out_byteclk" },
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{ .fw_name = "dsi1_phy_pll_out_byteclk", .name = "dsi1_phy_pll_out_byteclk" },
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};
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static const struct parent_map disp_cc_parent_map_7[] = {
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{ P_BI_TCXO, 0 },
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{ P_DISP_CC_PLL1_OUT_MAIN, 4 },
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{ P_DISP_CC_PLL1_OUT_EVEN, 6 },
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};
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static const struct clk_parent_data disp_cc_parent_data_7[] = {
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{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
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{ .hw = &disp_cc_pll1.clkr.hw },
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{ .hw = &disp_cc_pll1.clkr.hw },
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};
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static const struct parent_map disp_cc_parent_map_8[] = {
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{ P_BI_TCXO, 0 },
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{ P_DP0_PHY_PLL_LINK_CLK, 1 },
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{ P_DP1_PHY_PLL_LINK_CLK, 2 },
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{ P_DP2_PHY_PLL_LINK_CLK, 3 },
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{ P_DP3_PHY_PLL_LINK_CLK, 4 },
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};
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static const struct clk_parent_data disp_cc_parent_data_8[] = {
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{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
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{ .fw_name = "dp0_phy_pll_link_clk", .name = "dp0_phy_pll_link_clk" },
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{ .fw_name = "dp1_phy_pll_link_clk", .name = "dp1_phy_pll_link_clk" },
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{ .fw_name = "dp2_phy_pll_link_clk", .name = "dp2_phy_pll_link_clk" },
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{ .fw_name = "dp3_phy_pll_link_clk", .name = "dp3_phy_pll_link_clk" },
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};
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static const struct parent_map disp_cc_parent_map_9[] = {
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{ P_BI_TCXO, 0 },
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{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
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{ P_DISP_CC_PLL1_OUT_MAIN, 4 },
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{ P_DISP_CC_PLL1_OUT_EVEN, 6 },
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};
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static const struct clk_parent_data disp_cc_parent_data_9[] = {
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{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
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{ .hw = &disp_cc_pll0.clkr.hw },
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{ .hw = &disp_cc_pll1.clkr.hw },
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{ .hw = &disp_cc_pll1.clkr.hw },
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};
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static const struct parent_map disp_cc_parent_map_10[] = {
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{ P_BI_TCXO, 0 },
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{ P_DISP_CC_PLL2_OUT_MAIN, 2 },
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};
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static const struct clk_parent_data disp_cc_parent_data_10[] = {
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{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
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{ .hw = &disp_cc_pll2.clkr.hw },
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};
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static const struct parent_map disp_cc_parent_map_11[] = {
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{ P_SLEEP_CLK, 0 },
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};
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static const struct clk_parent_data disp_cc_parent_data_11_ao[] = {
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{ .fw_name = "sleep_clk", .name = "sleep_clk" },
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};
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static const struct freq_tbl ftbl_disp_cc_esync0_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 disp_cc_esync0_clk_src = {
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.cmd_rcgr = 0x80c0,
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.mnd_width = 16,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_4,
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.freq_tbl = ftbl_disp_cc_esync0_clk_src,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "disp_cc_esync0_clk_src",
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.parent_data = disp_cc_parent_data_4,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_pixel_ops,
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},
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.clkr.vdd_data = {
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.vdd_class = &vdd_mx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOWER_D1] = 225000000,
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[VDD_LOWER] = 300000000,
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[VDD_LOW] = 480000000,
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[VDD_LOW_L1] = 625000000},
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},
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};
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static struct clk_rcg2 disp_cc_esync1_clk_src = {
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.cmd_rcgr = 0x80d8,
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.mnd_width = 16,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_4,
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.freq_tbl = ftbl_disp_cc_esync0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_esync1_clk_src",
|
|
.parent_data = disp_cc_parent_data_4,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_pixel_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_mx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER_D1] = 225000000,
|
|
[VDD_LOWER] = 300000000,
|
|
[VDD_LOW] = 480000000,
|
|
[VDD_LOW_L1] = 625000000},
|
|
},
|
|
};
|
|
|
|
static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
|
|
F(19200000, P_BI_TCXO, 1, 0, 0),
|
|
F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
|
|
F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
|
|
.cmd_rcgr = 0x8360,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_7,
|
|
.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
|
|
.enable_safe_config = true,
|
|
.flags = HW_CLK_CTRL_MODE,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_ahb_clk_src",
|
|
.parent_data = disp_cc_parent_data_7,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_7),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_mm,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER_D1] = 19200000,
|
|
[VDD_LOW] = 37500000,
|
|
[VDD_NOMINAL] = 75000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
|
|
.cmd_rcgr = 0x8180,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_1,
|
|
.freq_tbl = ftbl_disp_cc_esync0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_byte0_clk_src",
|
|
.parent_data = disp_cc_parent_data_1,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_byte2_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_classes = disp_cc_sun_regulators,
|
|
.num_vdd_classes = ARRAY_SIZE(disp_cc_sun_regulators),
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER_D1] = 140630000,
|
|
[VDD_LOWER] = 187500000,
|
|
[VDD_LOW] = 300000000,
|
|
[VDD_LOW_L1] = 358000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
|
|
.cmd_rcgr = 0x819c,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_1,
|
|
.freq_tbl = ftbl_disp_cc_esync0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_byte1_clk_src",
|
|
.parent_data = disp_cc_parent_data_1,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_byte2_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_classes = disp_cc_sun_regulators,
|
|
.num_vdd_classes = ARRAY_SIZE(disp_cc_sun_regulators),
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER_D1] = 140630000,
|
|
[VDD_LOWER] = 187500000,
|
|
[VDD_LOW] = 300000000,
|
|
[VDD_LOW_L1] = 358000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = {
|
|
.cmd_rcgr = 0x8234,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_0,
|
|
.freq_tbl = ftbl_disp_cc_esync0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx0_aux_clk_src",
|
|
.parent_data = disp_cc_parent_data_0,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_mm,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER_D1] = 19200000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = {
|
|
.cmd_rcgr = 0x81e8,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_8,
|
|
.freq_tbl = ftbl_disp_cc_esync0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx0_link_clk_src",
|
|
.parent_data = disp_cc_parent_data_8,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_8),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_byte2_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_classes = disp_cc_sun_regulators,
|
|
.num_vdd_classes = ARRAY_SIZE(disp_cc_sun_regulators),
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER_D1] = 19200000,
|
|
[VDD_LOWER] = 270000000,
|
|
[VDD_LOW_L1] = 540000000,
|
|
[VDD_NOMINAL] = 810000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src = {
|
|
.cmd_rcgr = 0x8204,
|
|
.mnd_width = 16,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_5,
|
|
.freq_tbl = ftbl_disp_cc_esync0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx0_pixel0_clk_src",
|
|
.parent_data = disp_cc_parent_data_5,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_dp_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_classes = disp_cc_sun_regulators,
|
|
.num_vdd_classes = ARRAY_SIZE(disp_cc_sun_regulators),
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER_D1] = 19200000,
|
|
[VDD_LOWER] = 337500000,
|
|
[VDD_LOW_L1] = 405000000,
|
|
[VDD_NOMINAL] = 675000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src = {
|
|
.cmd_rcgr = 0x821c,
|
|
.mnd_width = 16,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_5,
|
|
.freq_tbl = ftbl_disp_cc_esync0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx0_pixel1_clk_src",
|
|
.parent_data = disp_cc_parent_data_5,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_dp_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_classes = disp_cc_sun_regulators,
|
|
.num_vdd_classes = ARRAY_SIZE(disp_cc_sun_regulators),
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER_D1] = 19200000,
|
|
[VDD_LOWER] = 337500000,
|
|
[VDD_LOW_L1] = 405000000,
|
|
[VDD_NOMINAL] = 675000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = {
|
|
.cmd_rcgr = 0x8298,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_0,
|
|
.freq_tbl = ftbl_disp_cc_esync0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx1_aux_clk_src",
|
|
.parent_data = disp_cc_parent_data_0,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_mm,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER_D1] = 19200000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = {
|
|
.cmd_rcgr = 0x827c,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_3,
|
|
.freq_tbl = ftbl_disp_cc_esync0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx1_link_clk_src",
|
|
.parent_data = disp_cc_parent_data_3,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_byte2_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_mm,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER_D1] = 19200000,
|
|
[VDD_LOWER] = 270000000,
|
|
[VDD_LOW_L1] = 540000000,
|
|
[VDD_NOMINAL] = 810000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src = {
|
|
.cmd_rcgr = 0x824c,
|
|
.mnd_width = 16,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_2,
|
|
.freq_tbl = ftbl_disp_cc_esync0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx1_pixel0_clk_src",
|
|
.parent_data = disp_cc_parent_data_2,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_dp_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_mm,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER_D1] = 19200000,
|
|
[VDD_LOWER] = 337500000,
|
|
[VDD_LOW_L1] = 405000000,
|
|
[VDD_NOMINAL] = 675000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src = {
|
|
.cmd_rcgr = 0x8264,
|
|
.mnd_width = 16,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_2,
|
|
.freq_tbl = ftbl_disp_cc_esync0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx1_pixel1_clk_src",
|
|
.parent_data = disp_cc_parent_data_2,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_dp_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_mm,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER_D1] = 19200000,
|
|
[VDD_LOWER] = 337500000,
|
|
[VDD_LOW_L1] = 405000000,
|
|
[VDD_NOMINAL] = 675000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = {
|
|
.cmd_rcgr = 0x82fc,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_0,
|
|
.freq_tbl = ftbl_disp_cc_esync0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx2_aux_clk_src",
|
|
.parent_data = disp_cc_parent_data_0,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_mm,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER_D1] = 19200000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = {
|
|
.cmd_rcgr = 0x82b0,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_3,
|
|
.freq_tbl = ftbl_disp_cc_esync0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx2_link_clk_src",
|
|
.parent_data = disp_cc_parent_data_3,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_byte2_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_mm,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER_D1] = 19200000,
|
|
[VDD_LOWER] = 270000000,
|
|
[VDD_LOW_L1] = 540000000,
|
|
[VDD_NOMINAL] = 810000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src = {
|
|
.cmd_rcgr = 0x82cc,
|
|
.mnd_width = 16,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_2,
|
|
.freq_tbl = ftbl_disp_cc_esync0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx2_pixel0_clk_src",
|
|
.parent_data = disp_cc_parent_data_2,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_dp_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_mm,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER_D1] = 19200000,
|
|
[VDD_LOWER] = 337500000,
|
|
[VDD_LOW_L1] = 405000000,
|
|
[VDD_NOMINAL] = 675000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src = {
|
|
.cmd_rcgr = 0x82e4,
|
|
.mnd_width = 16,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_2,
|
|
.freq_tbl = ftbl_disp_cc_esync0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx2_pixel1_clk_src",
|
|
.parent_data = disp_cc_parent_data_2,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_dp_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_mm,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER_D1] = 19200000,
|
|
[VDD_LOWER] = 337500000,
|
|
[VDD_LOW_L1] = 405000000,
|
|
[VDD_NOMINAL] = 675000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = {
|
|
.cmd_rcgr = 0x8348,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_0,
|
|
.freq_tbl = ftbl_disp_cc_esync0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx3_aux_clk_src",
|
|
.parent_data = disp_cc_parent_data_0,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_mm,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER_D1] = 19200000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = {
|
|
.cmd_rcgr = 0x832c,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_3,
|
|
.freq_tbl = ftbl_disp_cc_esync0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx3_link_clk_src",
|
|
.parent_data = disp_cc_parent_data_3,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_byte2_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_mm,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER_D1] = 19200000,
|
|
[VDD_LOWER] = 270000000,
|
|
[VDD_LOW] = 594000000,
|
|
[VDD_NOMINAL] = 810000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src = {
|
|
.cmd_rcgr = 0x8314,
|
|
.mnd_width = 16,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_2,
|
|
.freq_tbl = ftbl_disp_cc_esync0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx3_pixel0_clk_src",
|
|
.parent_data = disp_cc_parent_data_2,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_dp_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_mm,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER_D1] = 19200000,
|
|
[VDD_LOWER] = 337500000,
|
|
[VDD_LOW_L1] = 405000000,
|
|
[VDD_NOMINAL] = 675000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
|
|
.cmd_rcgr = 0x81b8,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_6,
|
|
.freq_tbl = ftbl_disp_cc_esync0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_esc0_clk_src",
|
|
.parent_data = disp_cc_parent_data_6,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_classes = disp_cc_sun_regulators,
|
|
.num_vdd_classes = ARRAY_SIZE(disp_cc_sun_regulators),
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER_D1] = 19200000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
|
|
.cmd_rcgr = 0x81d0,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_6,
|
|
.freq_tbl = ftbl_disp_cc_esync0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_esc1_clk_src",
|
|
.parent_data = disp_cc_parent_data_6,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_classes = disp_cc_sun_regulators,
|
|
.num_vdd_classes = ARRAY_SIZE(disp_cc_sun_regulators),
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER_D1] = 19200000},
|
|
},
|
|
};
|
|
|
|
static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
|
|
F(19200000, P_BI_TCXO, 1, 0, 0),
|
|
F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
|
F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
|
F(156000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
|
F(207000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
|
F(337000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
|
F(417000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
|
F(532000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
|
F(575000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
|
|
.cmd_rcgr = 0x8150,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_9,
|
|
.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
|
|
.enable_safe_config = true,
|
|
.flags = HW_CLK_CTRL_MODE,
|
|
.clkr = {
|
|
.crm = &disp_crm,
|
|
.crm_vcd = 1,
|
|
.crm_num_node = 1,
|
|
},
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_mdp_clk_src",
|
|
.parent_data = disp_cc_parent_data_9,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_9),
|
|
.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_crmb_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_classes = disp_cc_sun_regulators,
|
|
.num_vdd_classes = ARRAY_SIZE(disp_cc_sun_regulators),
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER_D1] = 156000000,
|
|
[VDD_LOWER] = 207000000,
|
|
[VDD_LOW] = 337000000,
|
|
[VDD_LOW_L1] = 417000000,
|
|
[VDD_NOMINAL] = 532000000,
|
|
[VDD_NOMINAL_L1] = 575000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
|
|
.cmd_rcgr = 0x8108,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_1,
|
|
.freq_tbl = ftbl_disp_cc_esync0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_pclk0_clk_src",
|
|
.parent_data = disp_cc_parent_data_1,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_pixel_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_classes = disp_cc_sun_regulators,
|
|
.num_vdd_classes = ARRAY_SIZE(disp_cc_sun_regulators),
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER_D1] = 225000000,
|
|
[VDD_LOWER] = 300000000,
|
|
[VDD_LOW] = 480000000,
|
|
[VDD_LOW_L1] = 625000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {
|
|
.cmd_rcgr = 0x8120,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_1,
|
|
.freq_tbl = ftbl_disp_cc_esync0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_pclk1_clk_src",
|
|
.parent_data = disp_cc_parent_data_1,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_pixel_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_classes = disp_cc_sun_regulators,
|
|
.num_vdd_classes = ARRAY_SIZE(disp_cc_sun_regulators),
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER_D1] = 225000000,
|
|
[VDD_LOWER] = 300000000,
|
|
[VDD_LOW] = 480000000,
|
|
[VDD_LOW_L1] = 625000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_pclk2_clk_src = {
|
|
.cmd_rcgr = 0x8138,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_1,
|
|
.freq_tbl = ftbl_disp_cc_esync0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_pclk2_clk_src",
|
|
.parent_data = disp_cc_parent_data_1,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_pixel_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_mm,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER_D1] = 225000000,
|
|
[VDD_LOWER] = 300000000,
|
|
[VDD_LOW] = 480000000,
|
|
[VDD_LOW_L1] = 625000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
|
|
.cmd_rcgr = 0x8168,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_0,
|
|
.freq_tbl = ftbl_disp_cc_esync0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_vsync_clk_src",
|
|
.parent_data = disp_cc_parent_data_0,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_mm,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER_D1] = 19200000},
|
|
},
|
|
};
|
|
|
|
static const struct freq_tbl ftbl_disp_cc_osc_clk_src[] = {
|
|
F(38400000, P_DISP_CC_PLL2_OUT_MAIN, 1, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_osc_clk_src = {
|
|
.cmd_rcgr = 0x80f0,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_10,
|
|
.freq_tbl = ftbl_disp_cc_osc_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_osc_clk_src",
|
|
.parent_data = disp_cc_parent_data_10,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_10),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_mxa,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER_D1] = 38400000},
|
|
},
|
|
};
|
|
|
|
static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = {
|
|
F(32000, P_SLEEP_CLK, 1, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_sleep_clk_src = {
|
|
.cmd_rcgr = 0xe064,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_11,
|
|
.freq_tbl = ftbl_disp_cc_sleep_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_sleep_clk_src",
|
|
.parent_data = disp_cc_parent_data_11_ao,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_11_ao),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_xo_clk_src = {
|
|
.cmd_rcgr = 0xe044,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_0,
|
|
.freq_tbl = ftbl_disp_cc_esync0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_xo_clk_src",
|
|
.parent_data = disp_cc_parent_data_0_ao,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0_ao),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
|
|
.reg = 0x8198,
|
|
.shift = 0,
|
|
.width = 4,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_byte0_div_clk_src",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_byte0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_regmap_div_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
|
|
.reg = 0x81b4,
|
|
.shift = 0,
|
|
.width = 4,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_byte1_div_clk_src",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_byte1_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_regmap_div_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src = {
|
|
.reg = 0x8200,
|
|
.shift = 0,
|
|
.width = 4,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx0_link_div_clk_src",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_regmap_div_ro_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src = {
|
|
.reg = 0x8294,
|
|
.shift = 0,
|
|
.width = 4,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx1_link_div_clk_src",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_regmap_div_ro_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src = {
|
|
.reg = 0x82c8,
|
|
.shift = 0,
|
|
.width = 4,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx2_link_div_clk_src",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_regmap_div_ro_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src = {
|
|
.reg = 0x8344,
|
|
.shift = 0,
|
|
.width = 4,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx3_link_div_clk_src",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_regmap_div_ro_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_esync0_clk = {
|
|
.halt_reg = 0x80b8,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x80b8,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_esync0_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_esync0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_esync1_clk = {
|
|
.halt_reg = 0x80bc,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x80bc,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_esync1_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_esync1_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_accu_shift_clk = {
|
|
.halt_reg = 0xe060,
|
|
.halt_check = BRANCH_HALT_VOTED,
|
|
.clkr = {
|
|
.enable_reg = 0xe060,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_accu_shift_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_xo_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_ahb1_clk = {
|
|
.halt_reg = 0xa028,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0xa028,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_ahb1_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_ahb_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_DONT_HOLD_STATE | CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_ahb_clk = {
|
|
.halt_reg = 0x80b0,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x80b0,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_ahb_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_ahb_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_DONT_HOLD_STATE | CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_byte0_clk = {
|
|
.halt_reg = 0x8034,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8034,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_byte0_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_byte0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
|
|
.halt_reg = 0x8038,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8038,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_byte0_intf_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_byte0_div_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_byte1_clk = {
|
|
.halt_reg = 0x803c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x803c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_byte1_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_byte1_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_byte1_intf_clk = {
|
|
.halt_reg = 0x8040,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8040,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_byte1_intf_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_byte1_div_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx0_aux_clk = {
|
|
.halt_reg = 0x8064,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8064,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx0_aux_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_dptx0_aux_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx0_crypto_clk = {
|
|
.halt_reg = 0x8058,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8058,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx0_crypto_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx0_link_clk = {
|
|
.halt_reg = 0x804c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x804c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx0_link_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk = {
|
|
.halt_reg = 0x8054,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8054,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx0_link_intf_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = {
|
|
.halt_reg = 0x805c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x805c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx0_pixel0_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = {
|
|
.halt_reg = 0x8060,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8060,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx0_pixel1_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk = {
|
|
.halt_reg = 0x8050,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8050,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx1_aux_clk = {
|
|
.halt_reg = 0x8080,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8080,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx1_aux_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_dptx1_aux_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx1_crypto_clk = {
|
|
.halt_reg = 0x807c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x807c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx1_crypto_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx1_link_clk = {
|
|
.halt_reg = 0x8070,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8070,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx1_link_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk = {
|
|
.halt_reg = 0x8078,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8078,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx1_link_intf_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk = {
|
|
.halt_reg = 0x8068,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8068,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx1_pixel0_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk = {
|
|
.halt_reg = 0x806c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x806c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx1_pixel1_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk = {
|
|
.halt_reg = 0x8074,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8074,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx1_usb_router_link_intf_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx2_aux_clk = {
|
|
.halt_reg = 0x8098,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8098,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx2_aux_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_dptx2_aux_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx2_crypto_clk = {
|
|
.halt_reg = 0x8094,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8094,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx2_crypto_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx2_link_clk = {
|
|
.halt_reg = 0x808c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x808c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx2_link_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk = {
|
|
.halt_reg = 0x8090,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8090,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx2_link_intf_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk = {
|
|
.halt_reg = 0x8084,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8084,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx2_pixel0_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk = {
|
|
.halt_reg = 0x8088,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8088,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx2_pixel1_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx3_aux_clk = {
|
|
.halt_reg = 0x80a8,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x80a8,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx3_aux_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_dptx3_aux_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx3_crypto_clk = {
|
|
.halt_reg = 0x80ac,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x80ac,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx3_crypto_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx3_link_clk = {
|
|
.halt_reg = 0x80a0,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x80a0,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx3_link_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk = {
|
|
.halt_reg = 0x80a4,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x80a4,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx3_link_intf_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk = {
|
|
.halt_reg = 0x809c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x809c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx3_pixel0_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_esc0_clk = {
|
|
.halt_reg = 0x8044,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8044,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_esc0_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_esc0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_esc1_clk = {
|
|
.halt_reg = 0x8048,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8048,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_esc1_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_esc1_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_mdp1_clk = {
|
|
.halt_reg = 0xa004,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0xa004,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_mdp1_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_mdp_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_mdp_clk = {
|
|
.halt_reg = 0x8010,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8010,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_mdp_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_mdp_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_aon_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_mdp_lut1_clk = {
|
|
.halt_reg = 0xa014,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0xa014,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_mdp_lut1_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_mdp_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
|
|
.halt_reg = 0x8020,
|
|
.halt_check = BRANCH_HALT_VOTED,
|
|
.clkr = {
|
|
.enable_reg = 0x8020,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_mdp_lut_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_mdp_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
|
|
.halt_reg = 0xc004,
|
|
.halt_check = BRANCH_HALT_VOTED,
|
|
.clkr = {
|
|
.enable_reg = 0xc004,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_non_gdsc_ahb_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_ahb_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_pclk0_clk = {
|
|
.halt_reg = 0x8004,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8004,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_pclk0_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_pclk0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_pclk1_clk = {
|
|
.halt_reg = 0x8008,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8008,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_pclk1_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_pclk1_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_pclk2_clk = {
|
|
.halt_reg = 0x800c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x800c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_pclk2_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_pclk2_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_vsync1_clk = {
|
|
.halt_reg = 0xa024,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0xa024,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_vsync1_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_vsync_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_vsync_clk = {
|
|
.halt_reg = 0x8030,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8030,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_vsync_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_mdss_vsync_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_osc_clk = {
|
|
.halt_reg = 0x80b4,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x80b4,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_osc_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&disp_cc_osc_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct gdsc disp_cc_mdss_core_gdsc = {
|
|
.gdscr = 0x9000,
|
|
.en_rest_wait_val = 0x2,
|
|
.en_few_wait_val = 0x2,
|
|
.clk_dis_wait_val = 0xf,
|
|
.pd = {
|
|
.name = "disp_cc_mdss_core_gdsc",
|
|
},
|
|
.pwrsts = PWRSTS_OFF_ON,
|
|
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL | HW_CTRL_SKIP_DIS,
|
|
.supply = "vdd_mm",
|
|
};
|
|
|
|
static struct gdsc disp_cc_mdss_core_int2_gdsc = {
|
|
.gdscr = 0xb000,
|
|
.en_rest_wait_val = 0x2,
|
|
.en_few_wait_val = 0x2,
|
|
.clk_dis_wait_val = 0xf,
|
|
.pd = {
|
|
.name = "disp_cc_mdss_core_int2_gdsc",
|
|
},
|
|
.pwrsts = PWRSTS_OFF_ON,
|
|
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL | HW_CTRL_SKIP_DIS,
|
|
.supply = "vdd_mm",
|
|
};
|
|
|
|
static struct clk_regmap *disp_cc_sun_clocks[] = {
|
|
[DISP_CC_ESYNC0_CLK] = &disp_cc_esync0_clk.clkr,
|
|
[DISP_CC_ESYNC0_CLK_SRC] = &disp_cc_esync0_clk_src.clkr,
|
|
[DISP_CC_ESYNC1_CLK] = &disp_cc_esync1_clk.clkr,
|
|
[DISP_CC_ESYNC1_CLK_SRC] = &disp_cc_esync1_clk_src.clkr,
|
|
[DISP_CC_MDSS_ACCU_SHIFT_CLK] = &disp_cc_mdss_accu_shift_clk.clkr,
|
|
[DISP_CC_MDSS_AHB1_CLK] = &disp_cc_mdss_ahb1_clk.clkr,
|
|
[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
|
|
[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
|
|
[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
|
|
[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
|
|
[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
|
|
[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
|
|
[DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr,
|
|
[DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
|
|
[DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr,
|
|
[DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp_cc_mdss_dptx0_aux_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp_cc_mdss_dptx0_aux_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX0_CRYPTO_CLK] = &disp_cc_mdss_dptx0_crypto_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp_cc_mdss_dptx0_link_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp_cc_mdss_dptx0_link_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx0_link_div_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp_cc_mdss_dptx0_link_intf_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp_cc_mdss_dptx0_pixel0_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx0_pixel0_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp_cc_mdss_dptx0_pixel1_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx0_pixel1_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] =
|
|
&disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp_cc_mdss_dptx1_aux_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp_cc_mdss_dptx1_aux_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX1_CRYPTO_CLK] = &disp_cc_mdss_dptx1_crypto_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp_cc_mdss_dptx1_link_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp_cc_mdss_dptx1_link_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx1_link_div_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp_cc_mdss_dptx1_link_intf_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp_cc_mdss_dptx1_pixel0_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx1_pixel0_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp_cc_mdss_dptx1_pixel1_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx1_pixel1_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] =
|
|
&disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp_cc_mdss_dptx2_aux_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp_cc_mdss_dptx2_aux_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX2_CRYPTO_CLK] = &disp_cc_mdss_dptx2_crypto_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp_cc_mdss_dptx2_link_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp_cc_mdss_dptx2_link_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx2_link_div_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp_cc_mdss_dptx2_link_intf_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp_cc_mdss_dptx2_pixel0_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx2_pixel0_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp_cc_mdss_dptx2_pixel1_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx2_pixel1_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp_cc_mdss_dptx3_aux_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp_cc_mdss_dptx3_aux_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX3_CRYPTO_CLK] = &disp_cc_mdss_dptx3_crypto_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp_cc_mdss_dptx3_link_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp_cc_mdss_dptx3_link_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx3_link_div_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp_cc_mdss_dptx3_link_intf_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp_cc_mdss_dptx3_pixel0_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx3_pixel0_clk_src.clkr,
|
|
[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
|
|
[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
|
|
[DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr,
|
|
[DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr,
|
|
[DISP_CC_MDSS_MDP1_CLK] = &disp_cc_mdss_mdp1_clk.clkr,
|
|
[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
|
|
[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
|
|
[DISP_CC_MDSS_MDP_LUT1_CLK] = &disp_cc_mdss_mdp_lut1_clk.clkr,
|
|
[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
|
|
[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
|
|
[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
|
|
[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
|
|
[DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr,
|
|
[DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr,
|
|
[DISP_CC_MDSS_PCLK2_CLK] = &disp_cc_mdss_pclk2_clk.clkr,
|
|
[DISP_CC_MDSS_PCLK2_CLK_SRC] = &disp_cc_mdss_pclk2_clk_src.clkr,
|
|
[DISP_CC_MDSS_VSYNC1_CLK] = &disp_cc_mdss_vsync1_clk.clkr,
|
|
[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
|
|
[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
|
|
[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
|
|
[DISP_CC_PLL1] = &disp_cc_pll1.clkr,
|
|
[DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr,
|
|
[DISP_CC_XO_CLK_SRC] = &disp_cc_xo_clk_src.clkr,
|
|
};
|
|
|
|
static struct clk_regmap *disp_cc_mx_sun_clocks[] = {
|
|
[DISP_CC_OSC_CLK] = &disp_cc_osc_clk.clkr,
|
|
[DISP_CC_OSC_CLK_SRC] = &disp_cc_osc_clk_src.clkr,
|
|
[DISP_CC_PLL2] = &disp_cc_pll2.clkr,
|
|
};
|
|
|
|
static struct gdsc *disp_cc_sun_gdscs[] = {
|
|
[DISP_CC_MDSS_CORE_GDSC] = &disp_cc_mdss_core_gdsc,
|
|
[DISP_CC_MDSS_CORE_INT2_GDSC] = &disp_cc_mdss_core_int2_gdsc,
|
|
};
|
|
|
|
static const struct qcom_reset_map disp_cc_sun_resets[] = {
|
|
[DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
|
|
[DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },
|
|
[DISP_CC_MDSS_RSCC_BCR] = { 0xc000 },
|
|
};
|
|
|
|
static const struct regmap_config disp_cc_sun_regmap_config = {
|
|
.reg_bits = 32,
|
|
.reg_stride = 4,
|
|
.val_bits = 32,
|
|
.max_register = 0x11014,
|
|
.fast_io = true,
|
|
};
|
|
|
|
static struct qcom_cc_desc disp_cc_sun_desc = {
|
|
.config = &disp_cc_sun_regmap_config,
|
|
.clks = disp_cc_sun_clocks,
|
|
.num_clks = ARRAY_SIZE(disp_cc_sun_clocks),
|
|
.resets = disp_cc_sun_resets,
|
|
.num_resets = ARRAY_SIZE(disp_cc_sun_resets),
|
|
.clk_regulators = disp_cc_sun_regulators,
|
|
.num_clk_regulators = ARRAY_SIZE(disp_cc_sun_regulators),
|
|
.gdscs = disp_cc_sun_gdscs,
|
|
.num_gdscs = ARRAY_SIZE(disp_cc_sun_gdscs),
|
|
};
|
|
|
|
static struct qcom_cc_desc disp_cc_mx_sun_desc = {
|
|
.clks = disp_cc_mx_sun_clocks,
|
|
.num_clks = ARRAY_SIZE(disp_cc_mx_sun_clocks),
|
|
.clk_regulators = disp_cc_mx_sun_regulators,
|
|
.num_clk_regulators = ARRAY_SIZE(disp_cc_mx_sun_regulators),
|
|
};
|
|
|
|
static const struct of_device_id disp_cc_sun_match_table[] = {
|
|
{ .compatible = "qcom,sun-dispcc" },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, disp_cc_sun_match_table);
|
|
|
|
static int disp_cc_sun_probe(struct platform_device *pdev)
|
|
{
|
|
struct regmap *regmap;
|
|
int ret;
|
|
|
|
regmap = qcom_cc_map(pdev, &disp_cc_sun_desc);
|
|
if (IS_ERR(regmap))
|
|
return PTR_ERR(regmap);
|
|
|
|
ret = qcom_cc_runtime_init(pdev, &disp_cc_sun_desc);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = pm_runtime_get_sync(&pdev->dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
clk_taycan_elu_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
|
|
clk_taycan_elu_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
|
|
|
|
/* Enable clock gating for MDP clocks */
|
|
regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);
|
|
|
|
/*
|
|
* Keep clocks always enabled:
|
|
* disp_cc_sleep_clk
|
|
* disp_cc_xo_clk
|
|
* disp_cc_mdss_rscc_ahb_clk
|
|
* disp_cc_mdss_rscc_vsync_clk
|
|
*/
|
|
regmap_update_bits(regmap, 0xe07c, BIT(0), BIT(0));
|
|
regmap_update_bits(regmap, 0xe05c, BIT(0), BIT(0));
|
|
regmap_update_bits(regmap, 0xc00c, BIT(0), BIT(0));
|
|
regmap_update_bits(regmap, 0xc008, BIT(0), BIT(0));
|
|
|
|
ret = qcom_cc_really_probe(pdev, &disp_cc_sun_desc, regmap);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to register DISP CC clocks\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = devm_of_platform_populate(&pdev->dev);
|
|
|
|
pm_runtime_put_sync(&pdev->dev);
|
|
dev_info(&pdev->dev, "Registered DISP CC clocks\n");
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void disp_cc_sun_sync_state(struct device *dev)
|
|
{
|
|
qcom_cc_sync_state(dev, &disp_cc_sun_desc);
|
|
}
|
|
|
|
static const struct dev_pm_ops disp_cc_sun_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(qcom_cc_runtime_suspend, qcom_cc_runtime_resume, NULL)
|
|
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
|
pm_runtime_force_resume)
|
|
};
|
|
|
|
static struct platform_driver disp_cc_sun_driver = {
|
|
.probe = disp_cc_sun_probe,
|
|
.driver = {
|
|
.name = "disp_cc-sun",
|
|
.of_match_table = disp_cc_sun_match_table,
|
|
.sync_state = disp_cc_sun_sync_state,
|
|
.pm = &disp_cc_sun_pm_ops,
|
|
},
|
|
};
|
|
|
|
static const struct of_device_id disp_cc_mx_sun_match_table[] = {
|
|
{ .compatible = "qcom,sun-dispcc_mx" },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, disp_cc_mx_sun_match_table);
|
|
|
|
static int disp_cc_mx_sun_probe(struct platform_device *pdev)
|
|
{
|
|
struct regmap *regmap = dev_get_regmap(pdev->dev.parent, NULL);
|
|
int ret;
|
|
|
|
clk_pongo_elu_pll_configure(&disp_cc_pll2, regmap, &disp_cc_pll2_config);
|
|
|
|
ret = qcom_cc_really_probe(pdev, &disp_cc_mx_sun_desc, regmap);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to register DISP CC MX clocks\n");
|
|
return ret;
|
|
}
|
|
|
|
dev_info(&pdev->dev, "Registered DISP CC MX clocks\n");
|
|
return ret;
|
|
}
|
|
|
|
static void disp_cc_mx_sun_sync_state(struct device *dev)
|
|
{
|
|
qcom_cc_sync_state(dev, &disp_cc_mx_sun_desc);
|
|
}
|
|
|
|
static struct platform_driver disp_cc_mx_sun_driver = {
|
|
.probe = disp_cc_mx_sun_probe,
|
|
.driver = {
|
|
.name = "disp_cc_mx-sun",
|
|
.of_match_table = disp_cc_mx_sun_match_table,
|
|
.sync_state = disp_cc_mx_sun_sync_state,
|
|
},
|
|
};
|
|
|
|
static int __init disp_cc_sun_init(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = platform_driver_register(&disp_cc_sun_driver);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return platform_driver_register(&disp_cc_mx_sun_driver);
|
|
}
|
|
subsys_initcall(disp_cc_sun_init);
|
|
|
|
static void __exit disp_cc_sun_exit(void)
|
|
{
|
|
platform_driver_unregister(&disp_cc_mx_sun_driver);
|
|
platform_driver_unregister(&disp_cc_sun_driver);
|
|
}
|
|
module_exit(disp_cc_sun_exit);
|
|
|
|
MODULE_DESCRIPTION("QTI DISP_CC SUN Driver");
|
|
MODULE_LICENSE("GPL");
|