1819 lines
49 KiB
C
Executable File
1819 lines
49 KiB
C
Executable File
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2022, 2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of.h>
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#include <linux/regmap.h>
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#include <linux/pm_runtime.h>
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#include <dt-bindings/clock/qcom,dispcc-parrot.h>
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-rcg.h"
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#include "clk-regmap.h"
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#include "clk-regmap-divider.h"
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#include "common.h"
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#include "reset.h"
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#include "vdd-level.h"
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#define DISP_CC_MISC_CMD 0xF000
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static DEFINE_VDD_REGULATORS(vdd_cx, VDD_HIGH + 1, 1, vdd_corner);
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static DEFINE_VDD_REGULATORS(vdd_mxa, VDD_HIGH + 1, 1, vdd_corner);
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static struct clk_vdd_class *disp_cc_parrot_regulators[] = {
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&vdd_cx,
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&vdd_mxa,
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};
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enum {
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P_BI_TCXO,
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P_DISP_CC_PLL0_OUT_MAIN,
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P_DISP_CC_PLL1_OUT_EVEN,
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P_DISP_CC_PLL1_OUT_MAIN,
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P_DP0_PHY_PLL_LINK_CLK,
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P_DP0_PHY_PLL_VCO_DIV_CLK,
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P_DP1_PHY_PLL_LINK_CLK,
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P_DP1_PHY_PLL_VCO_DIV_CLK,
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P_DP2_PHY_PLL_LINK_CLK,
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P_DP2_PHY_PLL_VCO_DIV_CLK,
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P_DP3_PHY_PLL_LINK_CLK,
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P_DP3_PHY_PLL_VCO_DIV_CLK,
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P_DSI0_PHY_PLL_OUT_BYTECLK,
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P_DSI0_PHY_PLL_OUT_DSICLK,
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P_SLEEP_CLK,
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};
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static const struct pll_vco lucid_evo_vco[] = {
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{ 249600000, 2000000000, 0 },
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};
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/* 600MHz Configuration */
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static const struct alpha_pll_config disp_cc_pll0_config = {
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.l = 0x1F,
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.cal_l = 0x44,
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.alpha = 0x4000,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00182261,
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.config_ctl_hi1_val = 0x32AA299C,
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.user_ctl_val = 0x00000001,
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.user_ctl_hi_val = 0x00000805,
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};
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static struct clk_alpha_pll disp_cc_pll0 = {
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.offset = 0x0,
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.vco_table = lucid_evo_vco,
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.num_vco = ARRAY_SIZE(lucid_evo_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
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.clkr = {
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.hw.init = &(const struct clk_init_data){
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.name = "disp_cc_pll0",
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.parent_data = &(const struct clk_parent_data){
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.fw_name = "bi_tcxo",
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_lucid_evo_ops,
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},
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.vdd_data = {
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.vdd_class = &vdd_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOWER_D1] = 500000000,
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[VDD_LOWER] = 615000000,
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[VDD_LOW] = 1066000000,
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[VDD_LOW_L1] = 1500000000,
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[VDD_NOMINAL] = 1800000000,
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[VDD_HIGH] = 2000000000},
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},
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},
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};
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/* 600MHz Configuration */
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static const struct alpha_pll_config disp_cc_pll1_config = {
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.l = 0x1F,
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.cal_l = 0x44,
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.alpha = 0x4000,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00182261,
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.config_ctl_hi1_val = 0x32AA299C,
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.user_ctl_val = 0x00000001,
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.user_ctl_hi_val = 0x00000805,
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};
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static struct clk_alpha_pll disp_cc_pll1 = {
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.offset = 0x1000,
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.vco_table = lucid_evo_vco,
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.num_vco = ARRAY_SIZE(lucid_evo_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
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.clkr = {
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.hw.init = &(const struct clk_init_data){
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.name = "disp_cc_pll1",
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.parent_data = &(const struct clk_parent_data){
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.fw_name = "bi_tcxo",
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_lucid_evo_ops,
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},
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.vdd_data = {
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.vdd_class = &vdd_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOWER_D1] = 500000000,
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[VDD_LOWER] = 615000000,
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[VDD_LOW] = 1066000000,
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[VDD_LOW_L1] = 1500000000,
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[VDD_NOMINAL] = 1800000000,
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[VDD_HIGH] = 2000000000},
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},
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},
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};
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static const struct parent_map disp_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_DP0_PHY_PLL_LINK_CLK, 1 },
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{ P_DP0_PHY_PLL_VCO_DIV_CLK, 2 },
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{ P_DP3_PHY_PLL_VCO_DIV_CLK, 3 },
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{ P_DP1_PHY_PLL_VCO_DIV_CLK, 4 },
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{ P_DP2_PHY_PLL_VCO_DIV_CLK, 6 },
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};
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static const struct clk_parent_data disp_cc_parent_data_0[] = {
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{ .fw_name = "bi_tcxo" },
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{ .fw_name = "dp0_phy_pll_link_clk", .name = "dp0_phy_pll_link_clk" },
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{ .fw_name = "dp0_phy_pll_vco_div_clk", .name = "dp0_phy_pll_vco_div_clk" },
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{ .fw_name = "dp3_phy_pll_vco_div_clk", .name = "dp3_phy_pll_vco_div_clk" },
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{ .fw_name = "dp1_phy_pll_vco_div_clk", .name = "dp1_phy_pll_vco_div_clk" },
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{ .fw_name = "dp2_phy_pll_vco_div_clk", .name = "dp2_phy_pll_vco_div_clk" },
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};
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static const struct parent_map disp_cc_parent_map_1[] = {
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{ P_BI_TCXO, 0 },
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};
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static const struct clk_parent_data disp_cc_parent_data_1[] = {
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{ .fw_name = "bi_tcxo" },
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};
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static const struct clk_parent_data disp_cc_parent_data_1_ao[] = {
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{ .fw_name = "bi_tcxo_ao" },
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};
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static const struct parent_map disp_cc_parent_map_2[] = {
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{ P_BI_TCXO, 0 },
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{ P_DP0_PHY_PLL_LINK_CLK, 1 },
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{ P_DP1_PHY_PLL_LINK_CLK, 2 },
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{ P_DP2_PHY_PLL_LINK_CLK, 3 },
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{ P_DP3_PHY_PLL_LINK_CLK, 4 },
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};
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static const struct clk_parent_data disp_cc_parent_data_2[] = {
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{ .fw_name = "bi_tcxo" },
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{ .fw_name = "dp0_phy_pll_link_clk", .name = "dp0_phy_pll_link_clk" },
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{ .fw_name = "dp1_phy_pll_link_clk", .name = "dp1_phy_pll_link_clk" },
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{ .fw_name = "dp2_phy_pll_link_clk", .name = "dp2_phy_pll_link_clk" },
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{ .fw_name = "dp3_phy_pll_link_clk", .name = "dp3_phy_pll_link_clk" },
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};
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static const struct parent_map disp_cc_parent_map_3[] = {
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{ P_BI_TCXO, 0 },
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{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
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{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
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};
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static const struct clk_parent_data disp_cc_parent_data_3[] = {
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{ .fw_name = "bi_tcxo" },
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{ .fw_name = "dsi0_phy_pll_out_dsiclk", .name = "dsi0_phy_pll_out_dsiclk" },
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{ .fw_name = "dsi0_phy_pll_out_byteclk", .name = "dsi0_phy_pll_out_byteclk" },
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};
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static const struct parent_map disp_cc_parent_map_4[] = {
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{ P_BI_TCXO, 0 },
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{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
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{ P_DISP_CC_PLL1_OUT_MAIN, 4 },
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{ P_DISP_CC_PLL1_OUT_EVEN, 6 },
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};
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static const struct clk_parent_data disp_cc_parent_data_4[] = {
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{ .fw_name = "bi_tcxo" },
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{ .hw = &disp_cc_pll0.clkr.hw },
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{ .hw = &disp_cc_pll1.clkr.hw },
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{ .hw = &disp_cc_pll1.clkr.hw },
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};
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static const struct parent_map disp_cc_parent_map_5[] = {
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{ P_BI_TCXO, 0 },
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{ P_DISP_CC_PLL1_OUT_MAIN, 4 },
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{ P_DISP_CC_PLL1_OUT_EVEN, 6 },
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};
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static const struct clk_parent_data disp_cc_parent_data_5[] = {
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{ .fw_name = "bi_tcxo" },
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{ .hw = &disp_cc_pll1.clkr.hw },
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{ .hw = &disp_cc_pll1.clkr.hw },
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};
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static const struct parent_map disp_cc_parent_map_6[] = {
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{ P_BI_TCXO, 0 },
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{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
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};
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static const struct clk_parent_data disp_cc_parent_data_6[] = {
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{ .fw_name = "bi_tcxo" },
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{ .fw_name = "dsi0_phy_pll_out_byteclk", .name = "dsi0_phy_pll_out_byteclk" },
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};
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static const struct parent_map disp_cc_parent_map_7[] = {
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{ P_SLEEP_CLK, 0 },
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};
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static const struct clk_parent_data disp_cc_parent_data_7[] = {
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{ .fw_name = "sleep_clk" },
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};
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static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
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F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
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{ }
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};
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static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
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.cmd_rcgr = 0x82a4,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_5,
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.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
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.enable_safe_config = true,
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.clkr.hw.init = &(const struct clk_init_data){
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.name = "disp_cc_mdss_ahb_clk_src",
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.parent_data = disp_cc_parent_data_5,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
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.ops = &clk_rcg2_ops,
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},
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.clkr.vdd_data = {
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.vdd_class = &vdd_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOWER] = 19200000,
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[VDD_LOW] = 37500000,
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[VDD_NOMINAL] = 75000000},
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},
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};
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static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
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.cmd_rcgr = 0x80f8,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_3,
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.clkr.hw.init = &(const struct clk_init_data){
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.name = "disp_cc_mdss_byte0_clk_src",
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.parent_data = disp_cc_parent_data_3,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_byte2_ops,
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},
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.clkr.vdd_data = {
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.vdd_class = &vdd_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOWER] = 187500000,
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[VDD_LOW] = 300000000,
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[VDD_LOW_L1] = 358000000},
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},
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};
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static const struct freq_tbl ftbl_disp_cc_mdss_dptx0_aux_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = {
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.cmd_rcgr = 0x8178,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_1,
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.freq_tbl = ftbl_disp_cc_mdss_dptx0_aux_clk_src,
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.clkr.hw.init = &(const struct clk_init_data){
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.name = "disp_cc_mdss_dptx0_aux_clk_src",
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.parent_data = disp_cc_parent_data_1,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
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.ops = &clk_rcg2_ops,
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},
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.clkr.vdd_data = {
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.vdd_class = &vdd_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOWER] = 19200000},
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},
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};
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static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = {
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.cmd_rcgr = 0x812c,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_2,
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.clkr.hw.init = &(const struct clk_init_data){
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.name = "disp_cc_mdss_dptx0_link_clk_src",
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.parent_data = disp_cc_parent_data_2,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_byte2_ops,
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},
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.clkr.vdd_data = {
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.vdd_class = &vdd_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOWER] = 270000000,
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[VDD_LOW_L1] = 540000000,
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[VDD_NOMINAL] = 810000000},
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},
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};
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static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src = {
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.cmd_rcgr = 0x8148,
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.mnd_width = 16,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_0,
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.clkr.hw.init = &(const struct clk_init_data){
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.name = "disp_cc_mdss_dptx0_pixel0_clk_src",
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.parent_data = disp_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_dp_ops,
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},
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.clkr.vdd_data = {
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.vdd_class = &vdd_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOWER] = 337500000,
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[VDD_LOW_L1] = 405000000,
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[VDD_NOMINAL] = 675000000},
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},
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};
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static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src = {
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.cmd_rcgr = 0x8160,
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.mnd_width = 16,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_0,
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.clkr.hw.init = &(const struct clk_init_data){
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.name = "disp_cc_mdss_dptx0_pixel1_clk_src",
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.parent_data = disp_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_dp_ops,
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},
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.clkr.vdd_data = {
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.vdd_class = &vdd_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOWER] = 337500000,
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[VDD_LOW_L1] = 405000000,
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[VDD_NOMINAL] = 675000000},
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},
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};
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static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = {
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.cmd_rcgr = 0x81dc,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_1,
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.freq_tbl = ftbl_disp_cc_mdss_dptx0_aux_clk_src,
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.clkr.hw.init = &(const struct clk_init_data){
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.name = "disp_cc_mdss_dptx1_aux_clk_src",
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.parent_data = disp_cc_parent_data_1,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
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.ops = &clk_rcg2_ops,
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},
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.clkr.vdd_data = {
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.vdd_class = &vdd_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOWER] = 19200000},
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},
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};
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static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = {
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.cmd_rcgr = 0x81c0,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_2,
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.clkr.hw.init = &(const struct clk_init_data){
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.name = "disp_cc_mdss_dptx1_link_clk_src",
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.parent_data = disp_cc_parent_data_2,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_byte2_ops,
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},
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.clkr.vdd_data = {
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.vdd_class = &vdd_cx,
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.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 270000000,
|
|
[VDD_LOW_L1] = 540000000,
|
|
[VDD_NOMINAL] = 810000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src = {
|
|
.cmd_rcgr = 0x8190,
|
|
.mnd_width = 16,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_0,
|
|
.clkr.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_dptx1_pixel0_clk_src",
|
|
.parent_data = disp_cc_parent_data_0,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_dp_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_cx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 337500000,
|
|
[VDD_LOW_L1] = 405000000,
|
|
[VDD_NOMINAL] = 675000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src = {
|
|
.cmd_rcgr = 0x81a8,
|
|
.mnd_width = 16,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_0,
|
|
.clkr.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_dptx1_pixel1_clk_src",
|
|
.parent_data = disp_cc_parent_data_0,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_dp_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_cx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 337500000,
|
|
[VDD_LOW_L1] = 405000000,
|
|
[VDD_NOMINAL] = 675000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = {
|
|
.cmd_rcgr = 0x8240,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_1,
|
|
.freq_tbl = ftbl_disp_cc_mdss_dptx0_aux_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_dptx2_aux_clk_src",
|
|
.parent_data = disp_cc_parent_data_1,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_cx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 19200000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = {
|
|
.cmd_rcgr = 0x81f4,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_2,
|
|
.clkr.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_dptx2_link_clk_src",
|
|
.parent_data = disp_cc_parent_data_2,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_byte2_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_cx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 270000000,
|
|
[VDD_LOW_L1] = 540000000,
|
|
[VDD_NOMINAL] = 810000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src = {
|
|
.cmd_rcgr = 0x8210,
|
|
.mnd_width = 16,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_0,
|
|
.clkr.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_dptx2_pixel0_clk_src",
|
|
.parent_data = disp_cc_parent_data_0,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_dp_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_cx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 337500000,
|
|
[VDD_LOW_L1] = 405000000,
|
|
[VDD_NOMINAL] = 675000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src = {
|
|
.cmd_rcgr = 0x8228,
|
|
.mnd_width = 16,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_0,
|
|
.clkr.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_dptx2_pixel1_clk_src",
|
|
.parent_data = disp_cc_parent_data_0,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_dp_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_cx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 337500000,
|
|
[VDD_LOW_L1] = 405000000,
|
|
[VDD_NOMINAL] = 675000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = {
|
|
.cmd_rcgr = 0x828c,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_1,
|
|
.freq_tbl = ftbl_disp_cc_mdss_dptx0_aux_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_dptx3_aux_clk_src",
|
|
.parent_data = disp_cc_parent_data_1,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_cx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 19200000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = {
|
|
.cmd_rcgr = 0x8270,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_2,
|
|
.clkr.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_dptx3_link_clk_src",
|
|
.parent_data = disp_cc_parent_data_2,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_byte2_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_cx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 270000000,
|
|
[VDD_LOW] = 594000000,
|
|
[VDD_NOMINAL] = 810000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src = {
|
|
.cmd_rcgr = 0x8258,
|
|
.mnd_width = 16,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_0,
|
|
.clkr.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_dptx3_pixel0_clk_src",
|
|
.parent_data = disp_cc_parent_data_0,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_dp_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_cx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 337500000,
|
|
[VDD_LOW_L1] = 405000000,
|
|
[VDD_NOMINAL] = 675000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
|
|
.cmd_rcgr = 0x8114,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_6,
|
|
.freq_tbl = ftbl_disp_cc_mdss_dptx0_aux_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_esc0_clk_src",
|
|
.parent_data = disp_cc_parent_data_6,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_cx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 19200000},
|
|
},
|
|
};
|
|
|
|
static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
|
|
F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
|
F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
|
F(380000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
|
F(506000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
|
F(608000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
|
|
.cmd_rcgr = 0x80b0,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_4,
|
|
.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
|
|
.enable_safe_config = true,
|
|
.clkr.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_mdp_clk_src",
|
|
.parent_data = disp_cc_parent_data_4,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_classes = disp_cc_parrot_regulators,
|
|
.num_vdd_classes = ARRAY_SIZE(disp_cc_parrot_regulators),
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 200000000,
|
|
[VDD_LOW] = 325000000,
|
|
[VDD_LOW_L1] = 380000000,
|
|
[VDD_NOMINAL] = 506000000,
|
|
[VDD_HIGH] = 608000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
|
|
.cmd_rcgr = 0x8098,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_3,
|
|
.clkr.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_pclk0_clk_src",
|
|
.parent_data = disp_cc_parent_data_3,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_pixel_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_cx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 328125000,
|
|
[VDD_LOW] = 525000000,
|
|
[VDD_LOW_L1] = 625000000},
|
|
},
|
|
};
|
|
|
|
static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = {
|
|
F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0),
|
|
F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
|
|
.cmd_rcgr = 0x80c8,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_4,
|
|
.freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
|
|
.enable_safe_config = true,
|
|
.clkr.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_rot_clk_src",
|
|
.parent_data = disp_cc_parent_data_4,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_classes = disp_cc_parrot_regulators,
|
|
.num_vdd_classes = ARRAY_SIZE(disp_cc_parrot_regulators),
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 200000000,
|
|
[VDD_LOW] = 300000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
|
|
.cmd_rcgr = 0x80e0,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_1,
|
|
.freq_tbl = ftbl_disp_cc_mdss_dptx0_aux_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_vsync_clk_src",
|
|
.parent_data = disp_cc_parent_data_1,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_cx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 19200000},
|
|
},
|
|
};
|
|
|
|
static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = {
|
|
F(32000, P_SLEEP_CLK, 1, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_sleep_clk_src = {
|
|
.cmd_rcgr = 0xe058,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_7,
|
|
.freq_tbl = ftbl_disp_cc_sleep_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_sleep_clk_src",
|
|
.parent_data = disp_cc_parent_data_7,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_7),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_cx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 32000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 disp_cc_xo_clk_src = {
|
|
.cmd_rcgr = 0xe03c,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_parent_map_1,
|
|
.freq_tbl = ftbl_disp_cc_mdss_dptx0_aux_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_xo_clk_src",
|
|
.parent_data = disp_cc_parent_data_1_ao,
|
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1_ao),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
|
|
.reg = 0x8110,
|
|
.shift = 0,
|
|
.width = 4,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_byte0_div_clk_src",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_byte0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_regmap_div_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src = {
|
|
.reg = 0x8144,
|
|
.shift = 0,
|
|
.width = 4,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx0_link_div_clk_src",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_regmap_div_ro_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src = {
|
|
.reg = 0x81d8,
|
|
.shift = 0,
|
|
.width = 4,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx1_link_div_clk_src",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_regmap_div_ro_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src = {
|
|
.reg = 0x820c,
|
|
.shift = 0,
|
|
.width = 4,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx2_link_div_clk_src",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_regmap_div_ro_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src = {
|
|
.reg = 0x8288,
|
|
.shift = 0,
|
|
.width = 4,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "disp_cc_mdss_dptx3_link_div_clk_src",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_regmap_div_ro_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_ahb1_clk = {
|
|
.halt_reg = 0xa020,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0xa020,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_ahb1_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_ahb_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_DONT_HOLD_STATE | CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_ahb_clk = {
|
|
.halt_reg = 0x8094,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8094,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_ahb_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_ahb_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_DONT_HOLD_STATE | CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_byte0_clk = {
|
|
.halt_reg = 0x8024,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8024,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_byte0_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_byte0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
|
|
.halt_reg = 0x8028,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8028,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_byte0_intf_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_byte0_div_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx0_aux_clk = {
|
|
.halt_reg = 0x8048,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8048,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_dptx0_aux_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_dptx0_aux_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx0_crypto_clk = {
|
|
.halt_reg = 0x803c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x803c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_dptx0_crypto_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx0_link_clk = {
|
|
.halt_reg = 0x8030,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8030,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_dptx0_link_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk = {
|
|
.halt_reg = 0x8038,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8038,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_dptx0_link_intf_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = {
|
|
.halt_reg = 0x8040,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8040,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_dptx0_pixel0_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = {
|
|
.halt_reg = 0x8044,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8044,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_dptx0_pixel1_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk = {
|
|
.halt_reg = 0x8034,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8034,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx1_aux_clk = {
|
|
.halt_reg = 0x8064,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8064,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_dptx1_aux_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_dptx1_aux_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx1_crypto_clk = {
|
|
.halt_reg = 0x8060,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8060,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_dptx1_crypto_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx1_link_clk = {
|
|
.halt_reg = 0x8054,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8054,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_dptx1_link_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk = {
|
|
.halt_reg = 0x805c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x805c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_dptx1_link_intf_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk = {
|
|
.halt_reg = 0x804c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x804c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_dptx1_pixel0_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk = {
|
|
.halt_reg = 0x8050,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8050,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_dptx1_pixel1_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk = {
|
|
.halt_reg = 0x8058,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8058,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_dptx1_usb_router_link_intf_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx2_aux_clk = {
|
|
.halt_reg = 0x807c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x807c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_dptx2_aux_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_dptx2_aux_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx2_crypto_clk = {
|
|
.halt_reg = 0x8078,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8078,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_dptx2_crypto_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx2_link_clk = {
|
|
.halt_reg = 0x8070,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8070,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_dptx2_link_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk = {
|
|
.halt_reg = 0x8074,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8074,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_dptx2_link_intf_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk = {
|
|
.halt_reg = 0x8068,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8068,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_dptx2_pixel0_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk = {
|
|
.halt_reg = 0x806c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x806c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_dptx2_pixel1_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx3_aux_clk = {
|
|
.halt_reg = 0x808c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x808c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_dptx3_aux_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_dptx3_aux_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx3_crypto_clk = {
|
|
.halt_reg = 0x8090,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8090,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_dptx3_crypto_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx3_link_clk = {
|
|
.halt_reg = 0x8084,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8084,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_dptx3_link_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk = {
|
|
.halt_reg = 0x8088,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8088,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_dptx3_link_intf_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk = {
|
|
.halt_reg = 0x8080,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8080,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_dptx3_pixel0_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_esc0_clk = {
|
|
.halt_reg = 0x802c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x802c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_esc0_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_esc0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_mdp1_clk = {
|
|
.halt_reg = 0xa004,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0xa004,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_mdp1_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_mdp_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_mdp_clk = {
|
|
.halt_reg = 0x8008,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8008,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_mdp_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_mdp_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_mdp_lut1_clk = {
|
|
.halt_reg = 0xa014,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0xa014,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_mdp_lut1_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_mdp_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
|
|
.halt_reg = 0x8018,
|
|
.halt_check = BRANCH_HALT_VOTED,
|
|
.clkr = {
|
|
.enable_reg = 0x8018,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_mdp_lut_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_mdp_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
|
|
.halt_reg = 0xc004,
|
|
.halt_check = BRANCH_HALT_VOTED,
|
|
.clkr = {
|
|
.enable_reg = 0xc004,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_non_gdsc_ahb_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_ahb_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_pclk0_clk = {
|
|
.halt_reg = 0x8004,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8004,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_pclk0_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_pclk0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_rot1_clk = {
|
|
.halt_reg = 0xa00c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0xa00c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_rot1_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_rot_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_rot_clk = {
|
|
.halt_reg = 0x8010,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8010,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_rot_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_rot_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
|
|
.halt_reg = 0xc00c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0xc00c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_rscc_ahb_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_ahb_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
|
|
.halt_reg = 0xc008,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0xc008,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_rscc_vsync_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_vsync_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_vsync1_clk = {
|
|
.halt_reg = 0xa01c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0xa01c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_vsync1_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_vsync_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_vsync_clk = {
|
|
.halt_reg = 0x8020,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8020,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_mdss_vsync_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_vsync_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_sleep_clk = {
|
|
.halt_reg = 0xe070,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0xe070,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "disp_cc_sleep_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_sleep_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_regmap *disp_cc_parrot_clocks[] = {
|
|
[DISP_CC_MDSS_AHB1_CLK] = &disp_cc_mdss_ahb1_clk.clkr,
|
|
[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
|
|
[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
|
|
[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
|
|
[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
|
|
[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
|
|
[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp_cc_mdss_dptx0_aux_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp_cc_mdss_dptx0_aux_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX0_CRYPTO_CLK] = &disp_cc_mdss_dptx0_crypto_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp_cc_mdss_dptx0_link_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp_cc_mdss_dptx0_link_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx0_link_div_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp_cc_mdss_dptx0_link_intf_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp_cc_mdss_dptx0_pixel0_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx0_pixel0_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp_cc_mdss_dptx0_pixel1_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx0_pixel1_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] =
|
|
&disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp_cc_mdss_dptx1_aux_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp_cc_mdss_dptx1_aux_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX1_CRYPTO_CLK] = &disp_cc_mdss_dptx1_crypto_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp_cc_mdss_dptx1_link_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp_cc_mdss_dptx1_link_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx1_link_div_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp_cc_mdss_dptx1_link_intf_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp_cc_mdss_dptx1_pixel0_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx1_pixel0_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp_cc_mdss_dptx1_pixel1_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx1_pixel1_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] =
|
|
&disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp_cc_mdss_dptx2_aux_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp_cc_mdss_dptx2_aux_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX2_CRYPTO_CLK] = &disp_cc_mdss_dptx2_crypto_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp_cc_mdss_dptx2_link_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp_cc_mdss_dptx2_link_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx2_link_div_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp_cc_mdss_dptx2_link_intf_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp_cc_mdss_dptx2_pixel0_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx2_pixel0_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp_cc_mdss_dptx2_pixel1_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx2_pixel1_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp_cc_mdss_dptx3_aux_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp_cc_mdss_dptx3_aux_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX3_CRYPTO_CLK] = &disp_cc_mdss_dptx3_crypto_clk.clkr,
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[DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp_cc_mdss_dptx3_link_clk.clkr,
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[DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp_cc_mdss_dptx3_link_clk_src.clkr,
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[DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx3_link_div_clk_src.clkr,
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[DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp_cc_mdss_dptx3_link_intf_clk.clkr,
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[DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp_cc_mdss_dptx3_pixel0_clk.clkr,
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[DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx3_pixel0_clk_src.clkr,
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[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
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[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
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[DISP_CC_MDSS_MDP1_CLK] = &disp_cc_mdss_mdp1_clk.clkr,
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[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
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[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
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[DISP_CC_MDSS_MDP_LUT1_CLK] = &disp_cc_mdss_mdp_lut1_clk.clkr,
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[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
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[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
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[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
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[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
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[DISP_CC_MDSS_ROT1_CLK] = &disp_cc_mdss_rot1_clk.clkr,
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[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
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[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
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[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
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|
[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
|
|
[DISP_CC_MDSS_VSYNC1_CLK] = &disp_cc_mdss_vsync1_clk.clkr,
|
|
[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
|
|
[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
|
|
[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
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|
[DISP_CC_PLL1] = &disp_cc_pll1.clkr,
|
|
[DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr,
|
|
[DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr,
|
|
[DISP_CC_XO_CLK_SRC] = &disp_cc_xo_clk_src.clkr,
|
|
};
|
|
|
|
static const struct qcom_reset_map disp_cc_parrot_resets[] = {
|
|
[DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
|
|
[DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },
|
|
[DISP_CC_MDSS_RSCC_BCR] = { 0xc000 },
|
|
};
|
|
|
|
static const struct regmap_config disp_cc_parrot_regmap_config = {
|
|
.reg_bits = 32,
|
|
.reg_stride = 4,
|
|
.val_bits = 32,
|
|
.max_register = 0x11008,
|
|
.fast_io = true,
|
|
};
|
|
|
|
static struct qcom_cc_desc disp_cc_parrot_desc = {
|
|
.config = &disp_cc_parrot_regmap_config,
|
|
.clks = disp_cc_parrot_clocks,
|
|
.num_clks = ARRAY_SIZE(disp_cc_parrot_clocks),
|
|
.resets = disp_cc_parrot_resets,
|
|
.num_resets = ARRAY_SIZE(disp_cc_parrot_resets),
|
|
.clk_regulators = disp_cc_parrot_regulators,
|
|
.num_clk_regulators = ARRAY_SIZE(disp_cc_parrot_regulators),
|
|
};
|
|
|
|
static const struct of_device_id disp_cc_parrot_match_table[] = {
|
|
{ .compatible = "qcom,parrot-dispcc" },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, disp_cc_parrot_match_table);
|
|
|
|
static int disp_cc_parrot_probe(struct platform_device *pdev)
|
|
{
|
|
struct regmap *regmap;
|
|
int ret;
|
|
|
|
regmap = qcom_cc_map(pdev, &disp_cc_parrot_desc);
|
|
if (IS_ERR(regmap))
|
|
return PTR_ERR(regmap);
|
|
|
|
ret = qcom_cc_runtime_init(pdev, &disp_cc_parrot_desc);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = pm_runtime_get_sync(&pdev->dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
|
|
clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
|
|
|
|
/* Enable clock gating for MDP clocks */
|
|
regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);
|
|
|
|
/*
|
|
* Keep clocks always enabled:
|
|
* disp_cc_xo_clk
|
|
*/
|
|
regmap_update_bits(regmap, 0xe054, BIT(0), BIT(0));
|
|
|
|
ret = qcom_cc_really_probe(pdev, &disp_cc_parrot_desc, regmap);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to register DISP CC clocks\n");
|
|
return ret;
|
|
}
|
|
|
|
pm_runtime_put_sync(&pdev->dev);
|
|
dev_info(&pdev->dev, "Registered DISP CC clocks\n");
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void disp_cc_parrot_sync_state(struct device *dev)
|
|
{
|
|
qcom_cc_sync_state(dev, &disp_cc_parrot_desc);
|
|
}
|
|
|
|
static const struct dev_pm_ops disp_cc_parrot_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(qcom_cc_runtime_suspend, qcom_cc_runtime_resume, NULL)
|
|
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
|
pm_runtime_force_resume)
|
|
};
|
|
|
|
static struct platform_driver disp_cc_parrot_driver = {
|
|
.probe = disp_cc_parrot_probe,
|
|
.driver = {
|
|
.name = "disp_cc-parrot",
|
|
.of_match_table = disp_cc_parrot_match_table,
|
|
.sync_state = disp_cc_parrot_sync_state,
|
|
.pm = &disp_cc_parrot_pm_ops,
|
|
},
|
|
};
|
|
|
|
static int __init disp_cc_parrot_init(void)
|
|
{
|
|
return platform_driver_register(&disp_cc_parrot_driver);
|
|
}
|
|
subsys_initcall(disp_cc_parrot_init);
|
|
|
|
static void __exit disp_cc_parrot_exit(void)
|
|
{
|
|
platform_driver_unregister(&disp_cc_parrot_driver);
|
|
}
|
|
module_exit(disp_cc_parrot_exit);
|
|
|
|
MODULE_DESCRIPTION("QTI DISP_CC PARROT Driver");
|
|
MODULE_LICENSE("GPL");
|