/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ /* * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMIH010X_H #define _DT_BINDINGS_QCOM_SPMI_VADC_PMIH010X_H #ifndef PMIH010X_SID #define PMIH010X_SID 7 #endif #define PMI_SID (PMIH010X_SID << 8) /* ADC channels for PMIH010X_ADC for PMIC5 Gen4 */ #define PMIH010X_ADC5_GEN4_OFFSET_REF (PMI_SID | ADC5_GEN4_OFFSET_REF) #define PMIH010X_ADC5_GEN4_1P25VREF (PMI_SID | ADC5_GEN4_1P25VREF) #define PMIH010X_ADC5_GEN4_VREF_VADC (PMI_SID | ADC5_GEN4_VREF_VADC) #define PMIH010X_ADC5_GEN4_DIE_TEMP (PMI_SID | ADC5_GEN4_DIE_TEMP) #define PMIH010X_ADC5_GEN4_AMUX_THM1_BAT_THERM (PMI_SID | ADC5_GEN4_AMUX1_THM) #define PMIH010X_ADC5_GEN4_AMUX_THM2_BAT_ID (PMI_SID | ADC5_GEN4_AMUX2_THM) #define PMIH010X_ADC5_GEN4_AMUX_THM3_SMB_TEMP_V (PMI_SID | ADC5_GEN4_AMUX3_THM) #define PMIH010X_ADC5_GEN4_AMUX_THM4_USB_THERM (PMI_SID | ADC5_GEN4_AMUX4_THM) #define PMIH010X_ADC5_GEN4_AMUX_THM5_OPTION (PMI_SID | ADC5_GEN4_AMUX5_THM) #define PMIH010X_ADC5_GEN4_AMUX_THM6_OPTION2 (PMI_SID | ADC5_GEN4_AMUX6_THM) #define PMIH010X_ADC5_GEN4_AMUX1_GPIO6 (PMI_SID | ADC5_GEN4_AMUX1_GPIO) #define PMIH010X_ADC5_GEN4_AMUX2_BAT2_ID (PMI_SID | ADC5_GEN4_AMUX2_GPIO) #define PMIH010X_ADC5_GEN4_AMUX3_BAT2_THERM (PMI_SID | ADC5_GEN4_AMUX3_GPIO) #define PMIH010X_ADC5_GEN4_AMUX4_GPIO12 (PMI_SID | ADC5_GEN4_AMUX4_GPIO) #define PMIH010X_ADC5_GEN4_CHG_TEMP (PMI_SID | ADC5_GEN4_CHG_TEMP) #define PMIH010X_ADC5_GEN4_USB_SNS_DIV20 (PMI_SID | ADC5_GEN4_USB_SNS_DIV20) #define PMIH010X_ADC5_GEN4_VIN_DIV20_MUX (PMI_SID | ADC5_GEN4_VIN_DIV20_MUX) #define PMIH010X_ADC5_GEN4_USBC_MUX (PMI_SID | ADC5_GEN4_USBC_MUX) #define PMIH010X_ADC5_GEN4_VREF_BAT_THERM (PMI_SID | ADC5_GEN4_VREF_BAT_THERM) #define PMIH010X_ADC5_GEN4_IIN (PMI_SID | ADC5_GEN4_IIN) #define PMIH010X_ADC5_GEN4_TEMP_ALARM_LITE (PMI_SID | ADC5_GEN4_TEMP_ALARM_LITE) #define PMIH010X_ADC5_GEN4_VREF_BAT2_THERM (PMI_SID | ADC5_GEN4_VREF_BAT2_THERM) #define PMIH010X_ADC5_GEN4_ATEST1 (PMI_SID | ADC5_GEN4_ATEST1) #define PMIH010X_ADC5_GEN4_ATEST2 (PMI_SID | ADC5_GEN4_ATEST2) #define PMIH010X_ADC5_GEN4_VBAT_2S_MID_CHGR (PMI_SID | ADC5_GEN4_VBAT_2S_MID_CHGR) #define PMIH010X_ADC5_GEN4_AMUX5_GPIO18 (PMI_SID | ADC5_GEN4_AMUX5_GPIO) #define PMIH010X_ADC5_GEN4_ICHG_FB (PMI_SID | ADC5_GEN4_ICHG_FB) /* 10k pull-up */ #define PMIH010X_ADC5_GEN4_AMUX_THM1_BAT_THERM_10K_PU (PMI_SID | ADC5_GEN4_AMUX1_THM_10K_PU) #define PMIH010X_ADC5_GEN4_AMUX_THM2_BAT_ID_10K_PU (PMI_SID | ADC5_GEN4_AMUX2_THM_10K_PU) #define PMIH010X_ADC5_GEN4_AMUX_THM3_SMB_TEMP_V_10K_PU (PMI_SID | ADC5_GEN4_AMUX3_THM_10K_PU) #define PMIH010X_ADC5_GEN4_AMUX_THM4_USB_THERM_10K_PU (PMI_SID | ADC5_GEN4_AMUX4_THM_10K_PU) #define PMIH010X_ADC5_GEN4_AMUX_THM5_OPTION_10K_PU (PMI_SID | ADC5_GEN4_AMUX5_THM_10K_PU) #define PMIH010X_ADC5_GEN4_AMUX_THM6_OPTION2_10K_PU (PMI_SID | ADC5_GEN4_AMUX6_THM_10K_PU) #define PMIH010X_ADC5_GEN4_AMUX1_GPIO6_10K_PU (PMI_SID | ADC5_GEN4_AMUX1_GPIO_10K_PU) #define PMIH010X_ADC5_GEN4_AMUX2_BAT2_ID_10K_PU (PMI_SID | ADC5_GEN4_AMUX2_GPIO_10K_PU) #define PMIH010X_ADC5_GEN4_AMUX3_BAT2_THERM_10K_PU (PMI_SID | ADC5_GEN4_AMUX3_GPIO_10K_PU) #define PMIH010X_ADC5_GEN4_AMUX4_GPIO12_10K_PU (PMI_SID | ADC5_GEN4_AMUX4_GPIO_10K_PU) #define PMIH010X_ADC5_GEN4_USBC_MUX_10K_PU (PMI_SID | ADC5_GEN4_USBC_MUX_10K_PU) #define PMIH010X_ADC5_GEN4_AMUX5_GPIO18_10K_PU (PMI_SID | ADC5_GEN4_AMUX5_GPIO_10K_PU) /* 100k pull-up */ #define PMIH010X_ADC5_GEN4_AMUX_THM1_BAT_THERM_100K_PU (PMI_SID | ADC5_GEN4_AMUX1_THM_100K_PU) #define PMIH010X_ADC5_GEN4_AMUX_THM2_BAT_ID_100K_PU (PMI_SID | ADC5_GEN4_AMUX2_THM_100K_PU) #define PMIH010X_ADC5_GEN4_AMUX_THM3_SMB_TEMP_V_100K_PU (PMI_SID | ADC5_GEN4_AMUX3_THM_100K_PU) #define PMIH010X_ADC5_GEN4_AMUX_THM4_USB_THERM_100K_PU (PMI_SID | ADC5_GEN4_AMUX4_THM_100K_PU) #define PMIH010X_ADC5_GEN4_AMUX_THM5_OPTION_100K_PU (PMI_SID | ADC5_GEN4_AMUX5_THM_100K_PU) #define PMIH010X_ADC5_GEN4_AMUX_THM6_OPTION2_100K_PU (PMI_SID | ADC5_GEN4_AMUX6_THM_100K_PU) #define PMIH010X_ADC5_GEN4_AMUX1_GPIO6_100K_PU (PMI_SID | ADC5_GEN4_AMUX1_GPIO_100K_PU) #define PMIH010X_ADC5_GEN4_AMUX2_BAT2_ID_100K_PU (PMI_SID | ADC5_GEN4_AMUX2_GPIO_100K_PU) #define PMIH010X_ADC5_GEN4_AMUX3_BAT2_THERM_100K_PU (PMI_SID | ADC5_GEN4_AMUX3_GPIO_100K_PU) #define PMIH010X_ADC5_GEN4_AMUX4_GPIO12_100K_PU (PMI_SID | ADC5_GEN4_AMUX4_GPIO_100K_PU) #define PMIH010X_ADC5_GEN4_USBC_MUX_100K_PU (PMI_SID | ADC5_GEN4_USBC_MUX_100K_PU) #define PMIH010X_ADC5_GEN4_AMUX5_GPIO18_100K_PU (PMI_SID | ADC5_GEN4_AMUX5_GPIO_100K_PU) /* 400k pull-up */ #define PMIH010X_ADC5_GEN4_AMUX_THM1_BAT_THERM_400K_PU (PMI_SID | ADC5_GEN4_AMUX1_THM_400K_PU) #define PMIH010X_ADC5_GEN4_AMUX_THM2_BAT_ID_400K_PU (PMI_SID | ADC5_GEN4_AMUX2_THM_400K_PU) #define PMIH010X_ADC5_GEN4_AMUX_THM3_SMB_TEMP_V_400K_PU (PMI_SID | ADC5_GEN4_AMUX3_THM_400K_PU) #define PMIH010X_ADC5_GEN4_AMUX_THM4_USB_THERM_400K_PU (PMI_SID | ADC5_GEN4_AMUX4_THM_400K_PU) #define PMIH010X_ADC5_GEN4_AMUX_THM5_OPTION_400K_PU (PMI_SID | ADC5_GEN4_AMUX5_THM_400K_PU) #define PMIH010X_ADC5_GEN4_AMUX_THM6_OPTION2_400K_PU (PMI_SID | ADC5_GEN4_AMUX6_THM_400K_PU) #define PMIH010X_ADC5_GEN4_AMUX1_GPIO6_400K_PU (PMI_SID | ADC5_GEN4_AMUX1_GPIO_400K_PU) #define PMIH010X_ADC5_GEN4_AMUX2_BAT2_ID_400K_PU (PMI_SID | ADC5_GEN4_AMUX2_GPIO_400K_PU) #define PMIH010X_ADC5_GEN4_AMUX3_BAT2_THERM_400K_PU (PMI_SID | ADC5_GEN4_AMUX3_GPIO_400K_PU) #define PMIH010X_ADC5_GEN4_AMUX4_GPIO12_400K_PU (PMI_SID | ADC5_GEN4_AMUX4_GPIO_400K_PU) #define PMIH010X_ADC5_GEN4_USBC_MUX_400K_PU (PMI_SID | ADC5_GEN4_USBC_MUX_400K_PU) #define PMIH010X_ADC5_GEN4_AMUX5_GPIO18_400K_PU (PMI_SID | ADC5_GEN4_AMUX5_GPIO_400K_PU) /* 1/3 Divider */ #define PMIH010X_ADC5_GEN4_AMUX1_GPIO6_DIV3 (PMI_SID | ADC5_GEN4_AMUX1_GPIO_DIV3) #define PMIH010X_ADC5_GEN4_VPH_PWR (PMI_SID | ADC5_GEN4_VPH_PWR) #define PMIH010X_ADC5_GEN4_VBAT_SNS_QBG (PMI_SID | ADC5_GEN4_VBAT_SNS_QBG) #define PMIH010X_ADC5_GEN4_VBAT_SNS_CHG (PMI_SID | ADC5_GEN4_VBAT_SNS_CHG) #define PMIH010X_ADC5_GEN4_VBAT_2S_MID_QBG (PMI_SID | ADC5_GEN4_VBAT_2S_MID_QBG) #define PMIH010X_ADC5_GEN4_VPH2_PWR (PMI_SID | ADC5_GEN4_VPH2_PWR) #define PMIH010X_ADC5_GEN4_VBAT_2S_MID_CHGR_DIV3 (PMI_SID | ADC5_GEN4_VBAT_2S_MID_CHGR_DIV3) #define PMIH010X_ADC5_GEN4_VBAT_2S_MID2 (PMI_SID | ADC5_GEN4_VBAT_2S_MID2) #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMIH010X_H */