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staging: axis-fifo: Remove hardware resets for user errors

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commit c6e8d85fafa7193613db37da29c0e8d6e2515b13 upstream.

The axis-fifo driver performs a full hardware reset (via
reset_ip_core()) in several error paths within the read and write
functions. This reset flushes both TX and RX FIFOs and resets the
AXI-Stream links.

Allow the user to handle the error without causing hardware disruption
or data loss in other FIFO paths.

Fixes: 4a965c5f89 ("staging: add driver for Xilinx AXI-Stream FIFO v4.1 IP core")
Cc: stable@vger.kernel.org
Signed-off-by: Gabriel Shahrouzi <gshahrouzi@gmail.com>
Link: https://lore.kernel.org/r/20250419004306.669605-1-gshahrouzi@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Gabriel Shahrouzi
2025-04-18 20:43:06 -04:00
committed by Greg Kroah-Hartman
parent 90db122533
commit f4d6b9f413
1 changed files with 3 additions and 8 deletions
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11
drivers/staging/axis-fifo/axis-fifo.c
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@@ -398,16 +398,14 @@ static ssize_t axis_fifo_read(struct file *f, char __user *buf,
bytes_available = ioread32(fifo->base_addr + XLLF_RLR_OFFSET); bytes_available = ioread32(fifo->base_addr + XLLF_RLR_OFFSET);
if (!bytes_available) { if (!bytes_available) {
dev_err(fifo->dt_device, "received a packet of length 0 - fifo core will be reset\n"); dev_err(fifo->dt_device, "received a packet of length 0\n");
reset_ip_core(fifo);
ret = -EIO; ret = -EIO;
goto end_unlock; goto end_unlock;
} }
if (bytes_available > len) { if (bytes_available > len) {
dev_err(fifo->dt_device, "user read buffer too small (available bytes=%zu user buffer bytes=%zu) - fifo core will be reset\n", dev_err(fifo->dt_device, "user read buffer too small (available bytes=%zu user buffer bytes=%zu)\n",
bytes_available, len); bytes_available, len);
reset_ip_core(fifo);
ret = -EINVAL; ret = -EINVAL;
goto end_unlock; goto end_unlock;
} }
@@ -416,8 +414,7 @@ static ssize_t axis_fifo_read(struct file *f, char __user *buf,
/* this probably can't happen unless IP /* this probably can't happen unless IP
* registers were previously mishandled * registers were previously mishandled
*/ */
dev_err(fifo->dt_device, "received a packet that isn't word-aligned - fifo core will be reset\n"); dev_err(fifo->dt_device, "received a packet that isn't word-aligned\n");
reset_ip_core(fifo);
ret = -EIO; ret = -EIO;
goto end_unlock; goto end_unlock;
} }
@@ -438,7 +435,6 @@ static ssize_t axis_fifo_read(struct file *f, char __user *buf,
if (copy_to_user(buf + copied * sizeof(u32), tmp_buf, if (copy_to_user(buf + copied * sizeof(u32), tmp_buf,
copy * sizeof(u32))) { copy * sizeof(u32))) {
reset_ip_core(fifo);
ret = -EFAULT; ret = -EFAULT;
goto end_unlock; goto end_unlock;
} }
@@ -547,7 +543,6 @@ static ssize_t axis_fifo_write(struct file *f, const char __user *buf,
if (copy_from_user(tmp_buf, buf + copied * sizeof(u32), if (copy_from_user(tmp_buf, buf + copied * sizeof(u32),
copy * sizeof(u32))) { copy * sizeof(u32))) {
reset_ip_core(fifo);
ret = -EFAULT; ret = -EFAULT;
goto end_unlock; goto end_unlock;
} }